kopia lustrzana https://github.com/cariboulabs/cariboulite
re-added pmod sync-inout in firmware
modem spi freq 4MHzgr-cariboulite_tag_samples
rodzic
ffbd7afee8
commit
211e5a3ff2
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@ -254,7 +254,6 @@ static int set_state(smi_stream_state_en new_state)
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return 0;
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}
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// Only if the new state is not idle (rx0, rx1 ot tx) setup a new transfer
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if(new_state != smi_stream_idle)
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{
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@ -262,7 +261,23 @@ static int set_state(smi_stream_state_en new_state)
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if (new_state == smi_stream_tx_channel)
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{
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ret = transfer_thread_init(inst, DMA_MEM_TO_DEV, stream_smi_write_dma_callback);
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// remove all data inside the tx_fifo
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if (mutex_lock_interruptible(&inst->write_lock))
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{
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return -EINTR;
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}
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kfifo_reset(&inst->tx_fifo);
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mutex_unlock(&inst->write_lock);
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inst->writeable = true;
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wake_up_interruptible(&inst->poll_event);
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//ret = transfer_thread_init(inst, DMA_MEM_TO_DEV, stream_smi_write_dma_callback);
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mb();
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spin_unlock(&inst->state_lock);
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// return the success
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return ret;
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}
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else
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{
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@ -734,7 +749,7 @@ int transfer_thread_init(struct bcm2835_smi_dev_instance *inst, enum dma_transfe
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struct dma_async_tx_descriptor *desc = NULL;
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struct bcm2835_smi_instance *smi_inst = inst->smi_inst;
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spin_lock(&smi_inst->transaction_lock);
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desc = stream_smi_dma_init_cyclic(smi_inst, dir, callback,inst);
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desc = stream_smi_dma_init_cyclic(smi_inst, dir, callback, inst);
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if(desc)
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{
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@ -886,15 +901,6 @@ static ssize_t smi_stream_write_file(struct file *f, const char __user *user_ptr
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return -EAGAIN;
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}
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if (kfifo_is_full(&inst->tx_fifo))
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{
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if(wait_event_interruptible(inst->poll_event, !kfifo_is_full(&inst->tx_fifo)))
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{
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mutex_unlock(&inst->write_lock);
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return -EAGAIN;
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}
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}
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// check how many bytes are available in the tx fifo
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num_bytes_available = kfifo_avail(&inst->tx_fifo);
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num_to_push = num_bytes_available > count ? count : num_bytes_available;
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@ -152,12 +152,12 @@ void dataConsumerThread(appContext_st* app)
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// Rx Callback (async)
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void receivedSamples(CaribouLiteRadio* radio, const std::complex<float>* samples, CaribouLiteMeta* sync, size_t num_samples)
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{
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for (int i = 0; i < 6; i ++)
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/*for (int i = 0; i < 6; i ++)
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{
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std::cout << "[" << samples[i].real() << ", " << samples[i].imag() << "]";
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}
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std::cout << std::endl;
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*/
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// push the received samples in the fifo
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app.rx_fifo->put(samples, num_samples);
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}
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@ -1,56 +0,0 @@
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# Prerequisites
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*.d
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# Object files
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*.o
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*.ko
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*.obj
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*.elf
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# Linker output
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*.ilk
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*.map
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*.exp
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# Precompiled Headers
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*.gch
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*.pch
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# Libraries
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*.lib
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*.a
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*.la
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*.lo
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# Shared objects (inc. Windows DLLs)
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*.dll
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*.so
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*.so.*
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*.dylib
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# Executables
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*.exe
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*.out
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*.app
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*.i*86
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*.x86_64
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*.hex
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# Debug files
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*.dSYM/
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*.su
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*.idb
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*.pdb
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# Kernel Module Compile Results
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*.mod*
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*.cmd
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.tmp_versions/
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modules.order
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Module.symvers
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Mkfile.old
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dkms.conf
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# build directories
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installations
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build
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@ -4,9 +4,9 @@ pcf_file = ./io.pcf
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top.bin:
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yosys -p 'synth_ice40 -top top -json $(filename).json -blif $(filename).blif' -p 'ice40_opt' -p 'fsm_opt' $(filename).v
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#nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc
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nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc --freq 80 --parallel-refine --opt-timing --seed 5 --timing-allow-fail
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#nextpnr-ice40 --json blinky.json --pcf blinky.pcf --asc blinky.asc --gui
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nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc --parallel-refine --opt-timing --seed 16 --timing-allow-fail
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icepack $(filename).asc $(filename).bin
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build: top.bin
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@ -15,9 +15,6 @@ module complex_fifo #(
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output reg full_o,
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output reg empty_o,
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input wire debug_pull,
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input wire debug_push,
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);
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reg [ADDR_WIDTH-1:0] wr_addr;
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@ -29,7 +26,15 @@ module complex_fifo #(
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reg [ADDR_WIDTH-1:0] rd_addr_gray_wr;
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reg [ADDR_WIDTH-1:0] rd_addr_gray_wr_r;
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reg [2*DATA_WIDTH-1:0] debug_buffer;
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// Initial conditions
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initial begin
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wr_addr <= 0;
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wr_addr_gray <= 0;
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full_o <= 0;
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rd_addr <= 0;
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rd_addr_gray <= 0;
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empty_o <= 1'b1;
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end
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function [ADDR_WIDTH-1:0] gray_conv;
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input [ADDR_WIDTH-1:0] in;
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@ -38,7 +43,7 @@ module complex_fifo #(
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end
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endfunction
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always @(posedge wr_clk_i) begin
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always @(posedge wr_clk_i/* or negedge wr_rst_b_i*/) begin
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if (wr_rst_b_i == 1'b0) begin
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wr_addr <= 0;
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wr_addr_gray <= 0;
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@ -54,7 +59,7 @@ module complex_fifo #(
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rd_addr_gray_wr_r <= rd_addr_gray_wr;
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end
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always @(posedge wr_clk_i) begin
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always @(posedge wr_clk_i/* or negedge wr_rst_b_i*/) begin
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if (wr_rst_b_i == 1'b0) begin
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full_o <= 0;
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end else if (wr_en_i) begin
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@ -64,11 +69,10 @@ module complex_fifo #(
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end
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end
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always @(posedge rd_clk_i) begin
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always @(posedge rd_clk_i/* or negedge rd_rst_b_i*/) begin
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if (rd_rst_b_i == 1'b0) begin
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rd_addr <= 0;
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rd_addr_gray <= 0;
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debug_buffer <= 32'hABCDEF01;
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end else if (rd_en_i) begin
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rd_addr <= rd_addr + 1'b1;
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rd_addr_gray <= gray_conv(rd_addr + 1'b1);
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@ -81,7 +85,7 @@ module complex_fifo #(
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wr_addr_gray_rd_r <= wr_addr_gray_rd;
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end
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always @(posedge rd_clk_i) begin
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always @(posedge rd_clk_i/* or negedge rd_rst_b_i*/) begin
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if (rd_rst_b_i == 1'b0) begin
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empty_o <= 1'b1;
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end else if (rd_en_i) begin
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@ -93,24 +97,15 @@ module complex_fifo #(
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always @(posedge rd_clk_i) begin
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if (rd_en_i) begin
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if (debug_pull) begin
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rd_data_o <= debug_buffer;
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end else begin
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rd_data_o[15:0] <= mem_q[rd_addr][15:0];
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rd_data_o[31:16] <= mem_i[rd_addr][15:0];
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end
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rd_data_o[15:0] <= mem_q[rd_addr][15:0];
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rd_data_o[31:16] <= mem_i[rd_addr][15:0];
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end
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end
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always @(posedge wr_clk_i) begin
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if (wr_en_i) begin
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if (debug_push) begin
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mem_q[wr_addr] <= debug_buffer[15:0];
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mem_i[wr_addr] <= debug_buffer[31:16];
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end else begin
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mem_q[wr_addr] <= wr_data_i[15:0];
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mem_i[wr_addr] <= wr_data_i[31:16];
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end
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mem_q[wr_addr] <= wr_data_i[15:0];
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mem_i[wr_addr] <= wr_data_i[31:16];
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end
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end
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Plik diff jest za duży
Load Diff
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@ -37,14 +37,14 @@ set_io i_glob_clock A29
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set_io i_rst_b A43
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# PMOD
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set_io io_pmod[0] B24
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set_io io_pmod[1] A31
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set_io io_pmod[2] B23
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set_io io_pmod[3] B21
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set_io io_pmod[4] A25
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set_io io_pmod[5] A26
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set_io io_pmod[6] A27
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set_io io_pmod[7] B20
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set_io io_pmod_out[0] B24
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set_io io_pmod_out[1] A31
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set_io io_pmod_out[2] B23
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set_io io_pmod_out[3] B21
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set_io io_pmod_in[0] A25
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set_io io_pmod_in[1] A26
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set_io io_pmod_in[2] A27
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set_io io_pmod_in[3] B20
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# MIXER
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set_io o_mixer_fm A32
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@ -27,14 +27,13 @@ module smi_ctrl
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input [7:0] i_smi_data_in,
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output o_smi_read_req,
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output o_smi_write_req,
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input i_smi_test,
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output o_channel,
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output o_dir,
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// TX CONDITIONAL
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output reg o_cond_tx,
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// Errors
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output reg o_address_error);
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output wire [1:0] o_state);
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// ---------------------------------
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@ -60,7 +59,6 @@ module smi_ctrl
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always @(posedge i_sys_clk or negedge i_rst_b)
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begin
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if (i_rst_b == 1'b0) begin
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o_address_error <= 1'b0;
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r_dir <= 1'b0;
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r_channel <= 1'b0;
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end else begin
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@ -78,7 +76,7 @@ module smi_ctrl
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o_data_out[0] <= i_rx_fifo_empty;
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o_data_out[1] <= i_tx_fifo_full;
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o_data_out[2] <= r_channel;
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o_data_out[3] <= i_smi_test;
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o_data_out[3] <= 1'b0;
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o_data_out[4] <= r_dir;
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o_data_out[7:4] <= 3'b000;
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end
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@ -118,7 +116,7 @@ module smi_ctrl
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wire soe_and_reset;
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assign soe_and_reset = i_rst_b & i_smi_soe_se;
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assign o_smi_read_req = (!i_rx_fifo_empty) || i_smi_test;
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assign o_smi_read_req = (!i_rx_fifo_empty);
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assign o_rx_fifo_pull = !r_fifo_pull_1 && r_fifo_pull && !i_rx_fifo_empty;
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always @(negedge soe_and_reset)
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@ -129,25 +127,15 @@ module smi_ctrl
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r_fifo_pulled_data <= 32'h00000000;
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end else begin
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// trigger the fifo pulling on the second byte
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w_fifo_pull_trigger <= (int_cnt_rx == 5'd8) && !i_smi_test;
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w_fifo_pull_trigger <= (int_cnt_rx == 5'd8);
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if ( i_smi_test ) begin
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if (r_smi_test_count == 0) begin
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r_smi_test_count <= 8'h56;
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end else begin
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o_smi_data_out <= r_smi_test_count;
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r_smi_test_count <= {((r_smi_test_count[2] ^ r_smi_test_count[3]) & 1'b1), r_smi_test_count[7:1]};
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end
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end else begin
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int_cnt_rx <= int_cnt_rx + 8;
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o_smi_data_out <= r_fifo_pulled_data[int_cnt_rx+7:int_cnt_rx];
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int_cnt_rx <= int_cnt_rx + 8;
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o_smi_data_out <= r_fifo_pulled_data[int_cnt_rx+7:int_cnt_rx];
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// update the internal register as soon as we reach the fourth byte
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if (int_cnt_rx == 5'd24) begin
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r_fifo_pulled_data <= i_rx_fifo_pulled_data;
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end
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// update the internal register as soon as we reach the fourth byte
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if (int_cnt_rx == 5'd24) begin
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r_fifo_pulled_data <= i_rx_fifo_pulled_data;
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end
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end
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end
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@ -185,6 +173,7 @@ module smi_ctrl
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assign o_tx_fifo_push = !r_fifo_push_1 && r_fifo_push && !i_tx_fifo_full;
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assign swe_and_reset = i_rst_b & i_smi_swe_srw;
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assign o_tx_fifo_clock = i_sys_clk;
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assign o_state = tx_reg_state;
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always @(negedge swe_and_reset)
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begin
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|
|
20945
firmware/top.asc
20945
firmware/top.asc
Plik diff jest za duży
Load Diff
BIN
firmware/top.bin
BIN
firmware/top.bin
Plik binarny nie jest wyświetlany.
3930
firmware/top.blif
3930
firmware/top.blif
Plik diff jest za duży
Load Diff
21806
firmware/top.json
21806
firmware/top.json
Plik diff jest za duży
Load Diff
|
@ -40,7 +40,9 @@ module top (
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// DIGITAL I/F
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input [3:0] i_config,
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input i_button,
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inout [7:0] io_pmod,
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//inout [7:0] io_pmod,
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output [3:0] io_pmod_out,
|
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input [3:0] io_pmod_in,
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output o_led0,
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output o_led1,
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@ -121,10 +123,10 @@ module top (
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wire w_tx_sync_input_09;
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wire w_tx_sync_input_24;
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assign w_rx_sync_input_09 = (w_rx_sync_type_09) ? io_pmod[7] : w_rx_sync_09;
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assign w_rx_sync_input_24 = (w_rx_sync_type_24) ? io_pmod[6] : w_rx_sync_24;
|
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assign w_tx_sync_input_09 = (w_tx_sync_type_09) ? io_pmod[5] : w_tx_sync_09;
|
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assign w_tx_sync_input_24 = (w_tx_sync_type_24) ? io_pmod[4] : w_tx_sync_24;
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assign w_rx_sync_input_09 = (w_rx_sync_type_09) ? io_pmod_in[3] : w_rx_sync_09;
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assign w_rx_sync_input_24 = (w_rx_sync_type_24) ? io_pmod_in[2] : w_rx_sync_24;
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assign w_tx_sync_input_09 = (w_tx_sync_type_09) ? io_pmod_in[1] : w_tx_sync_09;
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assign w_tx_sync_input_24 = (w_tx_sync_type_24) ? io_pmod_in[0] : w_tx_sync_24;
|
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|
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//=========================================================================
|
||||
// INSTANCES
|
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|
@ -179,7 +181,6 @@ module top (
|
|||
|
||||
wire w_debug_fifo_push;
|
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wire w_debug_fifo_pull;
|
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wire w_debug_smi_test;
|
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wire w_debug_lb_tx;
|
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wire [3:0] tx_sample_gap;
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|
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|
@ -199,7 +200,7 @@ module top (
|
|||
.i_config(i_config),
|
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.o_led0 (o_led0),
|
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.o_led1 (o_led1),
|
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.o_pmod (/*io_pmod[3:0]*/),
|
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.o_pmod (io_pmod_out[3:0]),
|
||||
|
||||
// Analog interfaces
|
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.o_mixer_fm(/*o_mixer_fm*/),
|
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|
@ -213,11 +214,6 @@ module top (
|
|||
.o_mixer_en(/*o_mixer_en*/)
|
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);
|
||||
|
||||
assign io_pmod[0] = ~lvds_clock_buf;
|
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assign io_pmod[1] = w_lvds_tx_d0;
|
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assign io_pmod[2] = w_lvds_tx_d1;
|
||||
assign io_pmod[3] = i_smi_swe_srw;
|
||||
|
||||
//=========================================================================
|
||||
// CONBINATORIAL ASSIGNMENTS
|
||||
//=========================================================================
|
||||
|
@ -401,21 +397,21 @@ module top (
|
|||
wire w_rx_fifo_empty;
|
||||
|
||||
complex_fifo #(
|
||||
.ADDR_WIDTH(10), // 1024 samples
|
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.ADDR_WIDTH(10), // 1024 samples
|
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.DATA_WIDTH(16), // 2x16 for I and Q
|
||||
) rx_fifo (
|
||||
.wr_rst_b_i(i_rst_b),
|
||||
.wr_clk_i(w_rx_fifo_write_clk),
|
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.wr_en_i(w_rx_fifo_push),
|
||||
.wr_data_i(w_rx_fifo_data),
|
||||
|
||||
.rd_rst_b_i(i_rst_b),
|
||||
.rd_clk_i(w_clock_sys),
|
||||
.rd_en_i(w_rx_fifo_pull),
|
||||
.rd_data_o(w_rx_fifo_pulled_data),
|
||||
|
||||
.full_o(w_rx_fifo_full),
|
||||
.empty_o(w_rx_fifo_empty),
|
||||
.debug_pull(1'b0/*w_debug_fifo_pull*/),
|
||||
.debug_push(1'b0/*w_debug_fifo_push*/)
|
||||
);
|
||||
|
||||
//=========================================================================
|
||||
|
@ -426,7 +422,7 @@ module top (
|
|||
|
||||
lvds_tx lvds_tx_inst (
|
||||
.i_rst_b(i_rst_b),
|
||||
.i_ddr_clk(~lvds_clock_buf),
|
||||
.i_ddr_clk(lvds_clock_buf),
|
||||
.o_ddr_data({w_lvds_tx_d0, w_lvds_tx_d1}),
|
||||
.i_fifo_empty(w_tx_fifo_empty),
|
||||
.o_fifo_read_clk(w_tx_fifo_read_clk),
|
||||
|
@ -440,11 +436,25 @@ module top (
|
|||
.o_sync_state_bit(),
|
||||
);
|
||||
|
||||
//assign io_pmod[0] = ~lvds_clock_buf;
|
||||
//assign io_pmod[1] = w_lvds_tx_d0;
|
||||
//assign io_pmod[2] = w_lvds_tx_d1;
|
||||
//assign io_pmod[0] = w_smi_write_req;
|
||||
//assign io_pmod[1] = i_smi_swe_srw;
|
||||
//assign io_pmod[2] = w_tx_fifo_push;
|
||||
//assign io_pmod[3] = w_smi_tx_state[0];
|
||||
//assign io_pmod[4] = w_smi_tx_state[1];
|
||||
//assign io_pmod[5] = w_tx_fifo_full;
|
||||
//assign io_pmod[6] = w_tx_fifo_empty;
|
||||
//assign io_pmod[7] = w_tx_fifo_pull;
|
||||
|
||||
//assign io_pmod[7:0] = w_smi_data_input;
|
||||
assign o_smi_write_req = i_smi_swe_srw;
|
||||
|
||||
wire w_tx_fifo_full;
|
||||
wire w_tx_fifo_empty;
|
||||
wire w_tx_fifo_read_clk;
|
||||
wire w_tx_fifo_push;
|
||||
wire w_tx_fifo_clock;
|
||||
wire [31:0] w_tx_fifo_data;
|
||||
wire w_tx_fifo_pull;
|
||||
wire [31:0] w_tx_fifo_pulled_data;
|
||||
|
@ -455,25 +465,21 @@ module top (
|
|||
) tx_fifo (
|
||||
// smi clock is writing
|
||||
.wr_rst_b_i(i_rst_b),
|
||||
.wr_clk_i(w_tx_fifo_clock),
|
||||
.wr_clk_i(w_clock_sys),
|
||||
.wr_en_i(w_tx_fifo_push),
|
||||
.wr_data_i(w_tx_fifo_data),
|
||||
.full_o(w_tx_fifo_full),
|
||||
|
||||
// lvds clock is pulling (reading)
|
||||
.rd_rst_b_i(i_rst_b),
|
||||
.rd_clk_i(w_tx_fifo_read_clk),
|
||||
.rd_clk_i(~lvds_clock_buf),
|
||||
.rd_en_i(w_tx_fifo_pull),
|
||||
.rd_data_o(w_tx_fifo_pulled_data),
|
||||
.full_o(w_tx_fifo_full),
|
||||
.empty_o(w_tx_fifo_empty),
|
||||
.debug_pull(1'b0),
|
||||
.debug_push(1'b0)
|
||||
);
|
||||
|
||||
wire channel;
|
||||
wire w_smi_data_direction;
|
||||
//assign channel = i_smi_a3;
|
||||
//assign w_smi_data_direction = i_smi_a2;
|
||||
|
||||
smi_ctrl smi_ctrl_ins (
|
||||
.i_rst_b(i_rst_b),
|
||||
|
@ -494,7 +500,7 @@ module top (
|
|||
.o_tx_fifo_push(w_tx_fifo_push),
|
||||
.o_tx_fifo_pushed_data(w_tx_fifo_data),
|
||||
.i_tx_fifo_full(w_tx_fifo_full),
|
||||
.o_tx_fifo_clock(w_tx_fifo_clock),
|
||||
.o_tx_fifo_clock(/*w_tx_fifo_clock*/),
|
||||
|
||||
.i_smi_soe_se(i_smi_soe_se),
|
||||
.i_smi_swe_srw(i_smi_swe_srw),
|
||||
|
@ -504,15 +510,15 @@ module top (
|
|||
.o_smi_write_req(w_smi_write_req),
|
||||
.o_channel(channel),
|
||||
.o_dir (w_smi_data_direction),
|
||||
.i_smi_test(1'b0/*w_debug_smi_test*/),
|
||||
.o_cond_tx(),
|
||||
.o_address_error()
|
||||
.o_state(w_smi_tx_state)
|
||||
);
|
||||
|
||||
wire [7:0] w_smi_data_output;
|
||||
wire [7:0] w_smi_data_input;
|
||||
wire w_smi_read_req;
|
||||
wire w_smi_write_req;
|
||||
wire [1:0] w_smi_tx_state;
|
||||
|
||||
// the "Writing" flag indicates that the data[7:0] direction (inout)
|
||||
// from the FPGA's SMI module should be "output". This happens when the
|
||||
|
@ -594,7 +600,7 @@ module top (
|
|||
);
|
||||
|
||||
assign o_smi_read_req = (w_smi_data_direction) ? w_smi_read_req : w_smi_write_req;
|
||||
assign o_smi_write_req = 1'bZ;
|
||||
//assign o_smi_write_req = 1'bZ;
|
||||
|
||||
//assign o_led0 = w_smi_data_direction;
|
||||
//assign o_led1 = channel;
|
||||
|
|
|
@ -0,0 +1,22 @@
|
|||
#! /usr/bin/bash
|
||||
|
||||
# Decimate
|
||||
FSTART="125"
|
||||
FSTOP="125"
|
||||
MOD="top"
|
||||
|
||||
f=${FSTART}
|
||||
while [ $f -le ${FSTOP} ]
|
||||
do
|
||||
i=1
|
||||
while [ $i -le 30 ]
|
||||
do
|
||||
echo "freq $f seed $i"
|
||||
nextpnr-ice40 --lp1k --package qn84 --asc ${MOD}.asc --pcf io.pcf --json ${MOD}.json --seed $i --parallel-refine --opt-timing --timing-allow-fail 2>&1 | fgrep 'Info: Max frequency for clock'
|
||||
|
||||
icetime -d lp1k -P qn84 -p io.pcf -t ${MOD}.asc 2>&1 | fgrep 'Total path delay'
|
||||
#icepack ${MOD}.asc ${MOD}.bin
|
||||
i=$((i+1))
|
||||
done
|
||||
f=$((f+5))
|
||||
done
|
|
@ -181,7 +181,7 @@ int at86rf215_init(at86rf215_st* dev,
|
|||
|
||||
ZF_LOGD("Adding chip definition to io_utils_spi");
|
||||
io_utils_hard_spi_st hard_dev_modem = { .spi_dev_id = dev->spi_dev, .spi_dev_channel = dev->spi_channel, };
|
||||
dev->io_spi_handle = io_utils_spi_add_chip(dev->io_spi, dev->cs_pin, 1000000, 0, 0,
|
||||
dev->io_spi_handle = io_utils_spi_add_chip(dev->io_spi, dev->cs_pin, 4000000, 0, 0,
|
||||
io_utils_spi_chip_type_modem,
|
||||
&hard_dev_modem);
|
||||
|
||||
|
|
|
@ -690,10 +690,17 @@ static void caribou_smi_generate_data(caribou_smi_st* dev, uint8_t* data, size_t
|
|||
caribou_smi_sample_complex_int16* cmplx_vec = sample_offset;
|
||||
uint32_t *samples = (uint32_t*)(data);
|
||||
|
||||
// Sample Structure
|
||||
// [ BYTE 0 ] [ BYTE 1 ] [ BYTE 2 ] [ BYTE 3 ]
|
||||
// [SOF TXC CTX I12 I11 I10 I9 I8] [0 I7 I6 I5 I4 I3 I2 I1] [0 I0 Q12 Q11 Q10 Q9 Q8 Q7] [0 Q6 Q5 Q4 Q3 Q2 Q1 Q0]
|
||||
// 1 0/1 0/1
|
||||
|
||||
for (unsigned int i = 0; i < (data_length / CARIBOU_SMI_BYTES_PER_SAMPLE); i++)
|
||||
{
|
||||
int32_t ii = cmplx_vec[i].i;
|
||||
int32_t qq = cmplx_vec[i].q;
|
||||
int32_t ii = 0xFFFF; //cmplx_vec[i].i;
|
||||
int32_t qq = 0; //cmplx_vec[i].q;
|
||||
ii &= 0x1FFF;
|
||||
qq &= 0x1FFF;
|
||||
|
||||
uint32_t s = SMI_TX_SAMPLE_SOF | SMI_TX_SAMPLE_MODEM_TX_CTRL | SMI_TX_SAMPLE_COND_TX_CTRL; s <<= 5;
|
||||
s |= (ii >> 8) & 0x1F; s <<= 8;
|
||||
|
@ -705,6 +712,7 @@ static void caribou_smi_generate_data(caribou_smi_st* dev, uint8_t* data, size_t
|
|||
//if (i < 2) printf("0x%08X\n", s);
|
||||
|
||||
samples[i] = __builtin_bswap32(s);
|
||||
//samples[i] = s;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
Ładowanie…
Reference in New Issue