re-added pmod sync-inout in firmware

modem spi freq 4MHz

driver/smi_stream_dev.c

@@ -254,7 +254,6 @@ static int set_state(smi_stream_state_en new_state)
         return 0;
     }
     
-
     // Only if the new state is not idle (rx0, rx1 ot tx) setup a new transfer
     if(new_state != smi_stream_idle)
     {
@@ -262,7 +261,23 @@ static int set_state(smi_stream_state_en new_state)
 
         if (new_state == smi_stream_tx_channel)
         {
-            ret = transfer_thread_init(inst, DMA_MEM_TO_DEV, stream_smi_write_dma_callback);
+            // remove all data inside the tx_fifo
+            if (mutex_lock_interruptible(&inst->write_lock))
+            {
+                return -EINTR;
+            }
+            kfifo_reset(&inst->tx_fifo);
+            mutex_unlock(&inst->write_lock);
+            
+            inst->writeable = true;
+            wake_up_interruptible(&inst->poll_event);
+            
+            //ret = transfer_thread_init(inst, DMA_MEM_TO_DEV, stream_smi_write_dma_callback);
+            mb();
+            spin_unlock(&inst->state_lock);
+            
+            // return the success
+            return ret;
         }
         else
         {
@@ -734,7 +749,7 @@ int transfer_thread_init(struct bcm2835_smi_dev_instance *inst, enum dma_transfe
         struct dma_async_tx_descriptor *desc = NULL;
         struct bcm2835_smi_instance *smi_inst = inst->smi_inst;
         spin_lock(&smi_inst->transaction_lock);
-        desc = stream_smi_dma_init_cyclic(smi_inst, dir, callback,inst);
+        desc = stream_smi_dma_init_cyclic(smi_inst, dir, callback, inst);
     
         if(desc)
         {
@@ -886,15 +901,6 @@ static ssize_t smi_stream_write_file(struct file *f, const char __user *user_ptr
         return -EAGAIN;
     }
     
-    if (kfifo_is_full(&inst->tx_fifo))
-    {
-        if(wait_event_interruptible(inst->poll_event,  !kfifo_is_full(&inst->tx_fifo)))
-        {
-            mutex_unlock(&inst->write_lock);
-            return -EAGAIN;
-        }	
-    }
-    
     // check how many bytes are available in the tx fifo
     num_bytes_available = kfifo_avail(&inst->tx_fifo);
     num_to_push = num_bytes_available > count ? count : num_bytes_available;

examples/cpp_api/async_sample_process/main.cpp

@@ -152,12 +152,12 @@ void dataConsumerThread(appContext_st* app)
 // Rx Callback (async)
 void receivedSamples(CaribouLiteRadio* radio, const std::complex<float>* samples, CaribouLiteMeta* sync, size_t num_samples)
 {
-    for (int i = 0; i < 6; i ++)
+    /*for (int i = 0; i < 6; i ++)
     {
         std::cout << "[" << samples[i].real() << ", " << samples[i].imag() << "]";
     }
     std::cout << std::endl;
-
+    */
     // push the received samples in the fifo
     app.rx_fifo->put(samples, num_samples);
 }

firmware/.gitignore.bak

@@ -1,56 +0,0 @@
-# Prerequisites
-*.d
-
-# Object files
-*.o
-*.ko
-*.obj
-*.elf
-
-# Linker output
-*.ilk
-*.map
-*.exp
-
-# Precompiled Headers
-*.gch
-*.pch
-
-# Libraries
-*.lib
-*.a
-*.la
-*.lo
-
-# Shared objects (inc. Windows DLLs)
-*.dll
-*.so
-*.so.*
-*.dylib
-
-# Executables
-*.exe
-*.out
-*.app
-*.i*86
-*.x86_64
-*.hex
-
-# Debug files
-*.dSYM/
-*.su
-*.idb
-*.pdb
-
-# Kernel Module Compile Results
-*.mod*
-*.cmd
-.tmp_versions/
-modules.order
-Module.symvers
-Mkfile.old
-dkms.conf
-
-# build directories
-installations
-build

firmware/Makefile

@@ -4,9 +4,9 @@ pcf_file = ./io.pcf
 
 top.bin:
 	yosys -p 'synth_ice40 -top top -json $(filename).json -blif $(filename).blif' -p 'ice40_opt' -p 'fsm_opt' $(filename).v
+
 	#nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc
-	nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc --freq 80 --parallel-refine --opt-timing --seed 5 --timing-allow-fail
-	#nextpnr-ice40 --json blinky.json --pcf blinky.pcf --asc blinky.asc --gui
+	nextpnr-ice40 --lp1k --package qn84 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc --parallel-refine --opt-timing --seed 16 --timing-allow-fail
 	icepack $(filename).asc $(filename).bin
 
 build: top.bin

firmware/complex_fifo.v

@@ -15,9 +15,6 @@ module complex_fifo #(
 
 	output reg 						full_o,
 	output reg 						empty_o,
-
-	input wire						debug_pull,
-	input wire						debug_push,
 );
 
 	reg [ADDR_WIDTH-1:0]	wr_addr;
@@ -29,7 +26,15 @@ module complex_fifo #(
 	reg [ADDR_WIDTH-1:0]	rd_addr_gray_wr;
 	reg [ADDR_WIDTH-1:0]	rd_addr_gray_wr_r;
 
-	reg [2*DATA_WIDTH-1:0] 	debug_buffer;
+	// Initial conditions
+	initial begin
+		wr_addr <= 0;
+		wr_addr_gray <= 0;
+		full_o <= 0;
+		rd_addr <= 0;
+		rd_addr_gray <= 0;
+		empty_o <= 1'b1;
+	end
 
 	function [ADDR_WIDTH-1:0] gray_conv;
 		input [ADDR_WIDTH-1:0] in;
@@ -38,7 +43,7 @@ module complex_fifo #(
 		end
 	endfunction
 
-	always @(posedge wr_clk_i) begin
+	always @(posedge wr_clk_i/* or negedge wr_rst_b_i*/) begin
 		if (wr_rst_b_i == 1'b0) begin
 			wr_addr <= 0;
 			wr_addr_gray <= 0;
@@ -54,7 +59,7 @@ module complex_fifo #(
 		rd_addr_gray_wr_r <= rd_addr_gray_wr;
 	end
 
-	always @(posedge wr_clk_i) begin
+	always @(posedge wr_clk_i/* or negedge wr_rst_b_i*/) begin
 		if (wr_rst_b_i == 1'b0) begin
 			full_o <= 0;
 		end else if (wr_en_i) begin
@@ -64,11 +69,10 @@ module complex_fifo #(
 		end
 	end
 
-	always @(posedge rd_clk_i) begin
+	always @(posedge rd_clk_i/* or negedge rd_rst_b_i*/) begin
 		if (rd_rst_b_i == 1'b0) begin
 			rd_addr <= 0;
 			rd_addr_gray <= 0;
-			debug_buffer <= 32'hABCDEF01;
 		end else if (rd_en_i) begin
 			rd_addr <= rd_addr + 1'b1;
 			rd_addr_gray <= gray_conv(rd_addr + 1'b1);
@@ -81,7 +85,7 @@ module complex_fifo #(
 		wr_addr_gray_rd_r <= wr_addr_gray_rd;
 	end
 
-	always @(posedge rd_clk_i) begin
+	always @(posedge rd_clk_i/* or negedge rd_rst_b_i*/) begin
 		if (rd_rst_b_i == 1'b0) begin
 			empty_o <= 1'b1;
 		end else if (rd_en_i) begin
@@ -93,24 +97,15 @@ module complex_fifo #(
 
 	always @(posedge rd_clk_i) begin
 		if (rd_en_i) begin
-			if (debug_pull) begin
-				rd_data_o <= debug_buffer;
-			end else begin
-				rd_data_o[15:0] <= mem_q[rd_addr][15:0];
-				rd_data_o[31:16] <= mem_i[rd_addr][15:0];
-			end
+			rd_data_o[15:0] <= mem_q[rd_addr][15:0];
+			rd_data_o[31:16] <= mem_i[rd_addr][15:0];
 		end
 	end
 
 	always @(posedge wr_clk_i) begin
 		if (wr_en_i) begin
-			if (debug_push) begin
-				mem_q[wr_addr] <= debug_buffer[15:0];
-				mem_i[wr_addr] <= debug_buffer[31:16];
-			end else begin
-				mem_q[wr_addr] <= wr_data_i[15:0];
-				mem_i[wr_addr] <= wr_data_i[31:16];
-			end
+			mem_q[wr_addr] <= wr_data_i[15:0];
+			mem_i[wr_addr] <= wr_data_i[31:16];
 		end
 	end
 

firmware/io.pcf

@@ -37,14 +37,14 @@ set_io i_glob_clock             A29
 set_io i_rst_b                  A43
 
 # PMOD
-set_io io_pmod[0]               B24
-set_io io_pmod[1]               A31
-set_io io_pmod[2]               B23
-set_io io_pmod[3]               B21
-set_io io_pmod[4]               A25
-set_io io_pmod[5]               A26
-set_io io_pmod[6]               A27
-set_io io_pmod[7]               B20
+set_io io_pmod_out[0]           B24
+set_io io_pmod_out[1]           A31
+set_io io_pmod_out[2]           B23
+set_io io_pmod_out[3]           B21
+set_io io_pmod_in[0]            A25
+set_io io_pmod_in[1]            A26
+set_io io_pmod_in[2]            A27
+set_io io_pmod_in[3]            B20
 
 # MIXER
 set_io o_mixer_fm               A32

firmware/smi_ctrl.v

@@ -27,14 +27,13 @@ module smi_ctrl
     input [7:0]         i_smi_data_in,
     output              o_smi_read_req,
     output              o_smi_write_req,
-    input               i_smi_test,
     output              o_channel,
     output              o_dir,
 
     // TX CONDITIONAL
     output reg          o_cond_tx,
-    // Errors
-    output reg          o_address_error);
+    
+    output wire [1:0]   o_state);
 
     // ---------------------------------
 
@@ -60,7 +59,6 @@ module smi_ctrl
     always @(posedge i_sys_clk or negedge i_rst_b)
     begin
         if (i_rst_b == 1'b0) begin
-            o_address_error <= 1'b0;
             r_dir <= 1'b0;
             r_channel <= 1'b0;
         end else begin
@@ -78,7 +76,7 @@ module smi_ctrl
                             o_data_out[0] <= i_rx_fifo_empty;
                             o_data_out[1] <= i_tx_fifo_full;
                             o_data_out[2] <= r_channel;
-                            o_data_out[3] <= i_smi_test;
+                            o_data_out[3] <= 1'b0;
                             o_data_out[4] <= r_dir;
                             o_data_out[7:4] <= 3'b000;
                         end
@@ -118,7 +116,7 @@ module smi_ctrl
 
     wire soe_and_reset;
     assign soe_and_reset = i_rst_b & i_smi_soe_se;
-    assign o_smi_read_req = (!i_rx_fifo_empty) || i_smi_test;
+    assign o_smi_read_req = (!i_rx_fifo_empty);
     assign o_rx_fifo_pull = !r_fifo_pull_1 && r_fifo_pull && !i_rx_fifo_empty;
 
     always @(negedge soe_and_reset)
@@ -129,25 +127,15 @@ module smi_ctrl
             r_fifo_pulled_data <= 32'h00000000;
         end else begin
             // trigger the fifo pulling on the second byte
-            w_fifo_pull_trigger <= (int_cnt_rx == 5'd8) && !i_smi_test;
+            w_fifo_pull_trigger <= (int_cnt_rx == 5'd8);
 
-            if ( i_smi_test ) begin
-                if (r_smi_test_count == 0) begin
-                    r_smi_test_count <= 8'h56;
-                end else begin
-                    o_smi_data_out <= r_smi_test_count;
-                    r_smi_test_count <= {((r_smi_test_count[2] ^ r_smi_test_count[3]) & 1'b1), r_smi_test_count[7:1]};
-                end
-            end else begin
-                int_cnt_rx <= int_cnt_rx + 8;
-                o_smi_data_out <= r_fifo_pulled_data[int_cnt_rx+7:int_cnt_rx];
-                
-                // update the internal register as soon as we reach the fourth byte
-                if (int_cnt_rx == 5'd24) begin
-                    r_fifo_pulled_data <= i_rx_fifo_pulled_data;
-                end
+            int_cnt_rx <= int_cnt_rx + 8;
+            o_smi_data_out <= r_fifo_pulled_data[int_cnt_rx+7:int_cnt_rx];
+            
+            // update the internal register as soon as we reach the fourth byte
+            if (int_cnt_rx == 5'd24) begin
+                r_fifo_pulled_data <= i_rx_fifo_pulled_data;
             end
-
         end
     end
 
@@ -185,6 +173,7 @@ module smi_ctrl
     assign o_tx_fifo_push = !r_fifo_push_1 && r_fifo_push && !i_tx_fifo_full;
     assign swe_and_reset = i_rst_b & i_smi_swe_srw;
     assign o_tx_fifo_clock = i_sys_clk;
+    assign o_state = tx_reg_state;
 
     always @(negedge swe_and_reset)
     begin

firmware/top.v

@@ -40,7 +40,9 @@ module top (
     // DIGITAL I/F
     input [3:0] i_config,
     input i_button,
-    inout [7:0] io_pmod,
+    //inout [7:0] io_pmod,
+    output [3:0] io_pmod_out,
+    input [3:0] io_pmod_in,
     output o_led0,
     output o_led1,
 
@@ -121,10 +123,10 @@ module top (
   wire w_tx_sync_input_09;
   wire w_tx_sync_input_24;
 
-  assign w_rx_sync_input_09 = (w_rx_sync_type_09) ? io_pmod[7] : w_rx_sync_09;
-  assign w_rx_sync_input_24 = (w_rx_sync_type_24) ? io_pmod[6] : w_rx_sync_24;
-  assign w_tx_sync_input_09 = (w_tx_sync_type_09) ? io_pmod[5] : w_tx_sync_09;
-  assign w_tx_sync_input_24 = (w_tx_sync_type_24) ? io_pmod[4] : w_tx_sync_24;
+  assign w_rx_sync_input_09 = (w_rx_sync_type_09) ? io_pmod_in[3] : w_rx_sync_09;
+  assign w_rx_sync_input_24 = (w_rx_sync_type_24) ? io_pmod_in[2] : w_rx_sync_24;
+  assign w_tx_sync_input_09 = (w_tx_sync_type_09) ? io_pmod_in[1] : w_tx_sync_09;
+  assign w_tx_sync_input_24 = (w_tx_sync_type_24) ? io_pmod_in[0] : w_tx_sync_24;
 
   //=========================================================================
   // INSTANCES
@@ -179,7 +181,6 @@ module top (
 
   wire w_debug_fifo_push;
   wire w_debug_fifo_pull;
-  wire w_debug_smi_test;
   wire w_debug_lb_tx;
   wire [3:0] tx_sample_gap;
 
@@ -199,7 +200,7 @@ module top (
       .i_config(i_config),
       .o_led0  (o_led0),
       .o_led1  (o_led1),
-      .o_pmod  (/*io_pmod[3:0]*/),
+      .o_pmod  (io_pmod_out[3:0]),
 
       // Analog interfaces
       .o_mixer_fm(/*o_mixer_fm*/),
@@ -213,11 +214,6 @@ module top (
       .o_mixer_en(/*o_mixer_en*/)
   );
 
-  assign io_pmod[0] = ~lvds_clock_buf;
-  assign io_pmod[1] = w_lvds_tx_d0;
-  assign io_pmod[2] = w_lvds_tx_d1;
-  assign io_pmod[3] = i_smi_swe_srw;
-
   //=========================================================================
   // CONBINATORIAL ASSIGNMENTS
   //=========================================================================
@@ -401,21 +397,21 @@ module top (
   wire w_rx_fifo_empty;
 
   complex_fifo  #(
-      .ADDR_WIDTH(10),  // 1024 samples
+      .ADDR_WIDTH(10),   // 1024 samples
       .DATA_WIDTH(16),  // 2x16 for I and Q 
   ) rx_fifo (
       .wr_rst_b_i(i_rst_b),
       .wr_clk_i(w_rx_fifo_write_clk),
       .wr_en_i(w_rx_fifo_push),
       .wr_data_i(w_rx_fifo_data),
+
       .rd_rst_b_i(i_rst_b),
       .rd_clk_i(w_clock_sys),
       .rd_en_i(w_rx_fifo_pull),
       .rd_data_o(w_rx_fifo_pulled_data),
+
       .full_o(w_rx_fifo_full),
       .empty_o(w_rx_fifo_empty),
-      .debug_pull(1'b0/*w_debug_fifo_pull*/),
-      .debug_push(1'b0/*w_debug_fifo_push*/)
   );
   
   //=========================================================================
@@ -426,7 +422,7 @@ module top (
   
   lvds_tx lvds_tx_inst (
       .i_rst_b(i_rst_b),
-      .i_ddr_clk(~lvds_clock_buf),
+      .i_ddr_clk(lvds_clock_buf),
       .o_ddr_data({w_lvds_tx_d0, w_lvds_tx_d1}),
       .i_fifo_empty(w_tx_fifo_empty),
       .o_fifo_read_clk(w_tx_fifo_read_clk),
@@ -440,11 +436,25 @@ module top (
       .o_sync_state_bit(),
   );
 
+  //assign io_pmod[0] = ~lvds_clock_buf;
+  //assign io_pmod[1] = w_lvds_tx_d0;
+  //assign io_pmod[2] = w_lvds_tx_d1;
+  //assign io_pmod[0] = w_smi_write_req;
+  //assign io_pmod[1] = i_smi_swe_srw;
+  //assign io_pmod[2] = w_tx_fifo_push;
+  //assign io_pmod[3] = w_smi_tx_state[0];
+  //assign io_pmod[4] = w_smi_tx_state[1];
+  //assign io_pmod[5] = w_tx_fifo_full;
+  //assign io_pmod[6] = w_tx_fifo_empty;
+  //assign io_pmod[7] = w_tx_fifo_pull;
+
+  //assign io_pmod[7:0] = w_smi_data_input;
+  assign o_smi_write_req = i_smi_swe_srw;
+
   wire w_tx_fifo_full;
   wire w_tx_fifo_empty;
   wire w_tx_fifo_read_clk;
   wire w_tx_fifo_push;
-  wire w_tx_fifo_clock;
   wire [31:0] w_tx_fifo_data;
   wire w_tx_fifo_pull;
   wire [31:0] w_tx_fifo_pulled_data;
@@ -455,25 +465,21 @@ module top (
   ) tx_fifo (
       // smi clock is writing
       .wr_rst_b_i(i_rst_b),
-      .wr_clk_i(w_tx_fifo_clock),
+      .wr_clk_i(w_clock_sys),
       .wr_en_i(w_tx_fifo_push),
       .wr_data_i(w_tx_fifo_data),
+      .full_o(w_tx_fifo_full),
 	  
       // lvds clock is pulling (reading)
       .rd_rst_b_i(i_rst_b),
-      .rd_clk_i(w_tx_fifo_read_clk),
+      .rd_clk_i(~lvds_clock_buf),
       .rd_en_i(w_tx_fifo_pull),
       .rd_data_o(w_tx_fifo_pulled_data),
-      .full_o(w_tx_fifo_full),
       .empty_o(w_tx_fifo_empty),
-      .debug_pull(1'b0),
-      .debug_push(1'b0)
   );
 
   wire channel;
   wire w_smi_data_direction;
-  //assign channel = i_smi_a3;
-  //assign w_smi_data_direction = i_smi_a2;
 
   smi_ctrl smi_ctrl_ins (
       .i_rst_b(i_rst_b),
@@ -494,7 +500,7 @@ module top (
       .o_tx_fifo_push(w_tx_fifo_push),
       .o_tx_fifo_pushed_data(w_tx_fifo_data),
       .i_tx_fifo_full(w_tx_fifo_full),
-      .o_tx_fifo_clock(w_tx_fifo_clock),
+      .o_tx_fifo_clock(/*w_tx_fifo_clock*/),
 
       .i_smi_soe_se(i_smi_soe_se),
       .i_smi_swe_srw(i_smi_swe_srw),
@@ -504,15 +510,15 @@ module top (
       .o_smi_write_req(w_smi_write_req),
       .o_channel(channel),
       .o_dir (w_smi_data_direction),
-      .i_smi_test(1'b0/*w_debug_smi_test*/),
       .o_cond_tx(),
-      .o_address_error()
+      .o_state(w_smi_tx_state)
   );
 
   wire [7:0] w_smi_data_output;
   wire [7:0] w_smi_data_input;
   wire w_smi_read_req;
   wire w_smi_write_req;
+  wire [1:0] w_smi_tx_state;
 
   // the "Writing" flag indicates that the data[7:0] direction (inout)
   // from the FPGA's SMI module should be "output". This happens when the
@@ -594,7 +600,7 @@ module top (
   );
 
   assign o_smi_read_req  = (w_smi_data_direction) ? w_smi_read_req : w_smi_write_req;
-  assign o_smi_write_req = 1'bZ;
+  //assign o_smi_write_req = 1'bZ;
 
   //assign o_led0 = w_smi_data_direction;
   //assign o_led1 = channel;

firmware/try-seeds.sh

@@ -0,0 +1,22 @@
+#! /usr/bin/bash
+
+# Decimate
+FSTART="125"
+FSTOP="125"
+MOD="top"
+
+f=${FSTART}
+while [ $f -le ${FSTOP} ]
+  do
+  i=1
+  while [ $i -le 30 ]
+    do
+      echo "freq $f seed $i"
+      nextpnr-ice40 --lp1k --package qn84 --asc ${MOD}.asc --pcf io.pcf --json ${MOD}.json --seed $i --parallel-refine --opt-timing --timing-allow-fail 2>&1 | fgrep 'Info: Max frequency for clock'
+      
+      icetime -d lp1k -P qn84 -p io.pcf -t ${MOD}.asc 2>&1 | fgrep 'Total path delay'
+      #icepack ${MOD}.asc ${MOD}.bin
+      i=$((i+1))
+    done
+  f=$((f+5))
+  done

software/libcariboulite/src/at86rf215/at86rf215.c

@@ -181,7 +181,7 @@ int at86rf215_init(at86rf215_st* dev,
 
     ZF_LOGD("Adding chip definition to io_utils_spi");
     io_utils_hard_spi_st hard_dev_modem = { .spi_dev_id = dev->spi_dev, .spi_dev_channel = dev->spi_channel, };
-	dev->io_spi_handle = io_utils_spi_add_chip(dev->io_spi, dev->cs_pin, 1000000, 0, 0,
+	dev->io_spi_handle = io_utils_spi_add_chip(dev->io_spi, dev->cs_pin, 4000000, 0, 0,
                         						io_utils_spi_chip_type_modem,
                                                 &hard_dev_modem);
 

software/libcariboulite/src/caribou_smi/caribou_smi.c

@@ -689,11 +689,18 @@ static void caribou_smi_generate_data(caribou_smi_st* dev, uint8_t* data, size_t
 {
     caribou_smi_sample_complex_int16* cmplx_vec = sample_offset;  
     uint32_t *samples = (uint32_t*)(data);
-	
+    
+    // Sample Structure
+    // [                 BYTE 0      ] [           BYTE 1     ] [           BYTE 2        ] [          BYTE 3      ]
+    // [SOF TXC CTX I12 I11 I10 I9 I8] [0 I7 I6 I5 I4 I3 I2 I1] [0 I0 Q12 Q11 Q10 Q9 Q8 Q7] [0 Q6 Q5 Q4 Q3 Q2 Q1 Q0]
+	//   1  0/1 0/1
+    
     for (unsigned int i = 0; i < (data_length / CARIBOU_SMI_BYTES_PER_SAMPLE); i++)
     {                    
-        int32_t ii = cmplx_vec[i].i;
-        int32_t qq = cmplx_vec[i].q;
+        int32_t ii = 0xFFFF; //cmplx_vec[i].i;
+        int32_t qq = 0; //cmplx_vec[i].q;
+        ii &= 0x1FFF;
+        qq &= 0x1FFF;
 		
         uint32_t s = SMI_TX_SAMPLE_SOF | SMI_TX_SAMPLE_MODEM_TX_CTRL | SMI_TX_SAMPLE_COND_TX_CTRL; s <<= 5;
         s |= (ii >> 8) & 0x1F; s <<= 8;
@@ -705,6 +712,7 @@ static void caribou_smi_generate_data(caribou_smi_st* dev, uint8_t* data, size_t
 		//if (i < 2) printf("0x%08X\n", s);
 		
         samples[i] = __builtin_bswap32(s);
+        //samples[i] = s;
     }
 }