kopia lustrzana https://github.com/cariboulabs/cariboulite
Update README.md
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@ -3,7 +3,7 @@ CaribouLite contains an FPGA device (ICE40 family) with 1280 LE. It has two desi
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1. Step #1: Controlling and managing the RF front-end path, and other digital device control.
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2. Step #2: Streaming SMI I/Q data from the RPI to the modem, and from the modem LVDS back to the SMI interface.
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![System diagram](https://github.com/babelbees/Caribou/blob/main/Software/CaribouLite/Firmware/doc/system_view.png)
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![System diagram](docs/fpga/system_view.png)
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The above block diagram shows the FPGA's peripheral connections and their naming.
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@ -15,14 +15,14 @@ The above block diagram shows the FPGA's peripheral connections and their naming
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* Orange: 3.3V voltage region and signals
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# FPGA Internal Blocks
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![Internal Block Diagram](https://github.com/babelbees/Caribou/blob/main/Software/CaribouLite/Firmware/doc/FPGA_diagram_internal.png)
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![Internal Block Diagram](docs/fpga/FPGA_diagram_internal.png)
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In the above diagram, the FPGA internal blocks of logic are shown. These blocks are segmented into Pink (Step #1) and Violet (Step #2).
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Each subblock has a communal interface structure, module ID (within the system) and module version.
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The subblocks are described below.
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# Generic Block Structure
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This chapter describes the structure of a generic block within the FPGA internal blocks (SYS, IO, etc.). The minimal interfaces are shown below.
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![Generic Block Structure](https://github.com/babelbees/Caribou/blob/main/Software/CaribouLite/Firmware/doc/generic_module_block.png)
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![Generic Block Structure](docs/fpga/generic_module_block.png)
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* All blocks shall respond to a default `'00000'` opcode with their module-version.
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* The blocks have a 5-bit `IOC` interface carrying the internal opcode.
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