diff --git a/firmware/spi_slave.v b/firmware/spi_slave.v
index 4aeb7dc..7caea3e 100644
--- a/firmware/spi_slave.v
+++ b/firmware/spi_slave.v
@@ -25,7 +25,7 @@ module spi_slave
 
   // Purpose: Recover SPI Byte in SPI Clock Domain
   // Samples line on correct edge of SPI Clock
-  /*always @(posedge i_spi_sck or posedge i_spi_cs_b)
+  always @(posedge i_spi_sck/* or posedge i_spi_cs_b*/)
   begin
     if (i_spi_cs_b) begin
       r_rx_bit_count <= 0;
@@ -42,8 +42,8 @@ module spi_slave
       end
     end
   end
-  */
-  always @(posedge i_sys_clk)
+  
+  /*always @(posedge i_sys_clk)
   begin
     if (i_spi_cs_b) begin
       r_rx_bit_count <= 0;
@@ -59,7 +59,7 @@ module spi_slave
         r_rx_done <= 1'b0;
       end
     end
-  end
+  end*/
 
   // Purpose: Cross from SPI Clock Domain to main FPGA clock domain
   // Assert o_rx_data_valid for 1 clock cycle when o_rx_byte has valid data.
diff --git a/firmware/top.asc b/firmware/top.asc
index a73714a..3eb1160 100644
--- a/firmware/top.asc
+++ b/firmware/top.asc
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+.sym 1 i_sck$SB_IO_IN_$glb_clk
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+.sym 3 r_counter_$glb_clk
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 .sym 5 w_soft_reset_$glb_sr
-.sym 6 lvds_rx_09_inst.r_data_SB_DFFESR_Q_E_$glb_ce
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+.sym 297 w_rx_24_fifo_data[19]
+.sym 298 w_rx_24_fifo_data[25]
+.sym 300 rx_09_fifo.wr_addr[6]
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+.sym 408 w_rx_24_fifo_data[16]
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+.sym 552 w_rx_24_fifo_data[17]
+.sym 573 w_rx_09_fifo_pulled_data[10]
+.sym 585 w_smi_data_output[3]
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-.sym 910 lvds_clock
-.sym 915 smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E
+.sym 852 lvds_clock
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+.sym 861 lvds_rx_24_inst.r_data[8]
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+.sym 983 r_tx_data_SB_DFFE_Q_E
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+.sym 1036 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O
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 .sym 2368 w_soft_reset_$glb_sr
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-.sym 4644 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O_$glb_ce
+.sym 4558 w_rx_09_fifo_data[28]
+.sym 4567 lvds_rx_09_inst.r_data[23]
+.sym 4569 lvds_rx_09_inst.r_data[25]
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+.sym 4644 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce
 .sym 4645 lvds_clock_$glb_clk
-.sym 4647 w_rx_09_fifo_pulled_data[20]
-.sym 4649 w_rx_09_fifo_pulled_data[21]
-.sym 4651 w_rx_09_fifo_pulled_data[22]
-.sym 4653 w_rx_09_fifo_pulled_data[23]
-.sym 4662 rx_09_fifo.full_o_SB_LUT4_I2_I3[0]
-.sym 4667 w_smi_data_output[4]
-.sym 4668 rx_09_fifo.wr_addr[2]
-.sym 4670 rx_09_fifo.wr_addr[8]
-.sym 4671 rx_24_fifo.empty_o_SB_LUT4_I2_I3[0]
-.sym 4673 rx_24_fifo.rd_addr[3]
-.sym 4674 rx_09_fifo.wr_addr[3]
-.sym 4675 rx_09_fifo.wr_addr[5]
-.sym 4677 rx_24_fifo.rd_addr[5]
-.sym 4678 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1]
-.sym 4680 rx_09_fifo.wr_addr[5]
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+.sym 4649 w_rx_09_fifo_pulled_data[5]
+.sym 4651 w_rx_09_fifo_pulled_data[6]
+.sym 4653 w_rx_09_fifo_pulled_data[7]
+.sym 4657 rx_24_fifo.rd_addr_SB_DFFESR_Q_E
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+.sym 4665 lvds_rx_09_inst.r_data[25]
+.sym 4668 smi_ctrl_ins.int_cnt_09[4]
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+.sym 4671 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1]
+.sym 4672 rx_24_fifo.rd_addr[4]
+.sym 4673 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1]
+.sym 4674 w_smi_data_output[6]
+.sym 4675 w_rx_09_fifo_data[13]
+.sym 4676 w_rx_24_fifo_data[22]
+.sym 4677 rx_09_fifo.mem_i.0.0.0_WCLKE
+.sym 4682 rx_09_fifo.mem_i.0.0.0_WCLKE
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+.sym 4694 lvds_rx_09_inst.r_data[29]
+.sym 4696 w_rx_09_fifo_pulled_data[22]
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+.sym 4705 w_rx_09_fifo_pulled_data[19]
+.sym 4708 w_rx_09_fifo_pulled_data[21]
+.sym 4709 lvds_rx_09_inst.r_data[28]
+.sym 4710 smi_ctrl_ins.int_cnt_09[4]
+.sym 4713 lvds_rx_09_inst.r_data[11]
+.sym 4714 w_rx_09_fifo_pulled_data[5]
+.sym 4716 w_rx_09_fifo_pulled_data[6]
+.sym 4718 smi_ctrl_ins.int_cnt_09[4]
+.sym 4724 lvds_rx_09_inst.r_data[28]
+.sym 4727 w_rx_09_fifo_pulled_data[3]
+.sym 4728 smi_ctrl_ins.int_cnt_09[3]
+.sym 4729 w_rx_09_fifo_pulled_data[19]
+.sym 4730 smi_ctrl_ins.int_cnt_09[4]
+.sym 4736 lvds_rx_09_inst.r_data[10]
+.sym 4742 lvds_rx_09_inst.r_data[29]
+.sym 4745 smi_ctrl_ins.int_cnt_09[3]
+.sym 4746 w_rx_09_fifo_pulled_data[22]
+.sym 4747 smi_ctrl_ins.int_cnt_09[4]
+.sym 4748 w_rx_09_fifo_pulled_data[6]
+.sym 4753 lvds_rx_09_inst.r_data[13]
+.sym 4757 lvds_rx_09_inst.r_data[11]
+.sym 4763 smi_ctrl_ins.int_cnt_09[4]
+.sym 4764 smi_ctrl_ins.int_cnt_09[3]
+.sym 4765 w_rx_09_fifo_pulled_data[5]
+.sym 4766 w_rx_09_fifo_pulled_data[21]
+.sym 4767 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce
 .sym 4768 lvds_clock_$glb_clk
-.sym 4770 w_rx_09_fifo_pulled_data[8]
-.sym 4772 w_rx_09_fifo_pulled_data[9]
-.sym 4774 w_rx_09_fifo_pulled_data[10]
-.sym 4776 w_rx_09_fifo_pulled_data[11]
-.sym 4787 i_smi_a2_SB_LUT4_I1_O_SB_LUT4_O_I3[2]
-.sym 4789 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1]
-.sym 4794 rx_09_fifo.rd_addr[1]
-.sym 4799 w_rx_09_fifo_data[23]
-.sym 4801 rx_09_fifo.mem_i.0.0.0_RCLKE
-.sym 4802 rx_24_fifo.rd_addr[1]
-.sym 4804 rx_09_fifo.rd_addr[1]
+.sym 4770 w_rx_24_fifo_pulled_data[8]
+.sym 4772 w_rx_24_fifo_pulled_data[9]
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+.sym 4776 w_rx_24_fifo_pulled_data[11]
+.sym 4782 rx_09_fifo.rd_addr[8]
+.sym 4784 lvds_rx_09_inst.r_data[13]
+.sym 4786 rx_09_fifo.rd_addr[2]
+.sym 4789 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0]
+.sym 4790 lvds_rx_09_inst.r_data[29]
+.sym 4792 rx_09_fifo.rd_addr[7]
+.sym 4793 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0]
+.sym 4794 w_smi_data_output[5]
+.sym 4796 rx_24_fifo.rd_addr[6]
+.sym 4798 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I2[2]
+.sym 4799 rx_24_fifo.rd_addr[8]
+.sym 4802 rx_09_fifo.empty_o_SB_LUT4_I0_O[0]
+.sym 4804 rx_24_fifo.mem_i.0.0.0_WCLKE
 .sym 4805 i_smi_a3$SB_IO_IN
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-.sym 4814 lvds_rx_09_inst.r_data[16]
-.sym 4819 lvds_rx_09_inst.r_data[20]
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-.sym 4891 lvds_clock_$glb_clk
-.sym 4893 w_rx_09_fifo_pulled_data[12]
-.sym 4895 w_rx_09_fifo_pulled_data[13]
-.sym 4897 w_rx_09_fifo_pulled_data[14]
-.sym 4899 w_rx_09_fifo_pulled_data[15]
-.sym 4905 rx_09_fifo.wr_addr[4]
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-.sym 4913 smi_ctrl_ins.int_cnt_24[3]
-.sym 4917 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
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-.sym 4928 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[2]
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+.sym 4826 i_smi_a2_SB_LUT4_I1_1_O[2]
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+.sym 4838 i_smi_a2_SB_LUT4_I1_O
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+.sym 4841 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0]
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+.sym 4850 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2]
+.sym 4851 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0]
+.sym 4852 i_smi_a2_SB_LUT4_I1_1_O[3]
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+.sym 4863 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[1]
+.sym 4864 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0[2]
+.sym 4865 i_smi_a2_SB_LUT4_I1_1_O[3]
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+.sym 4869 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[1]
+.sym 4870 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0]
+.sym 4871 i_smi_a2_SB_LUT4_I1_1_O[3]
+.sym 4874 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2]
+.sym 4875 i_smi_a2_SB_LUT4_I1_1_O[3]
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+.sym 4880 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2]
+.sym 4881 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0]
+.sym 4882 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[1]
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+.sym 4888 i_smi_a2_SB_LUT4_I1_1_O[1]
+.sym 4889 i_smi_a2_SB_LUT4_I1_1_O[0]
+.sym 4890 i_smi_a2_SB_LUT4_I1_O
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+.sym 4893 w_rx_24_fifo_pulled_data[12]
+.sym 4895 w_rx_24_fifo_pulled_data[13]
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+.sym 4899 w_rx_24_fifo_pulled_data[15]
+.sym 4901 w_rx_09_fifo_pulled_data[26]
+.sym 4905 smi_ctrl_ins.soe_and_reset
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+.sym 4907 io_smi_data[0]$SB_IO_OUT
+.sym 4909 w_rx_09_fifo_data[7]
+.sym 4912 w_rx_09_fifo_pulled_data[10]
+.sym 4913 w_rx_24_fifo_data[19]
+.sym 4915 i_smi_a2_SB_LUT4_I1_1_O[3]
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+.sym 4918 w_rx_24_fifo_data[27]
+.sym 4920 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[7]
+.sym 4921 rx_24_fifo.wr_addr[8]
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+.sym 4923 rx_24_fifo.rd_addr[7]
+.sym 4924 w_rx_24_fifo_data[25]
+.sym 4925 $PACKER_VCC_NET
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+.sym 4928 rx_24_fifo.wr_addr[8]
+.sym 4934 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 4936 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 4937 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[0]
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+.sym 4940 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[3]
+.sym 4942 w_rx_24_fifo_pulled_data[8]
+.sym 4944 w_rx_24_fifo_pulled_data[9]
+.sym 4945 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 4946 w_rx_24_fifo_pulled_data[5]
+.sym 4947 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 4948 w_rx_24_fifo_pulled_data[11]
+.sym 4950 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
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+.sym 4954 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[1]
+.sym 4955 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 4956 w_rx_24_fifo_pulled_data[3]
+.sym 4958 w_rx_24_fifo_pulled_data[0]
+.sym 4959 lvds_rx_24_inst.r_data[29]
+.sym 4960 w_rx_24_fifo_pulled_data[13]
+.sym 4962 w_rx_24_fifo_pulled_data[2]
+.sym 4963 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 4973 w_rx_24_fifo_pulled_data[0]
+.sym 4974 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 4975 w_rx_24_fifo_pulled_data[8]
+.sym 4976 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 4979 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 4980 w_rx_24_fifo_pulled_data[9]
+.sym 4981 w_rx_24_fifo_pulled_data[1]
+.sym 4982 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 4985 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 4986 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 4987 w_rx_24_fifo_pulled_data[11]
+.sym 4988 w_rx_24_fifo_pulled_data[3]
+.sym 4991 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 4992 w_rx_24_fifo_pulled_data[5]
+.sym 4993 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 4994 w_rx_24_fifo_pulled_data[13]
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@@ -5835,100 +6138,94 @@
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@@ -5937,5414 +6234,5078 @@
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-.sym 9148 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[5]
-.sym 9149 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[6]
-.sym 9150 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[7]
-.sym 9155 smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E
-.sym 9157 i_smi_a2_SB_LUT4_I1_O_SB_LUT4_O_I3[2]
-.sym 9175 rx_09_fifo.wr_addr[4]
-.sym 9177 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O
-.sym 9186 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O
-.sym 9190 w_soft_reset
-.sym 9194 w_rx_09_fifo_push
-.sym 9214 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[6]
-.sym 9218 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[6]
-.sym 9223 w_rx_09_fifo_push
-.sym 9226 w_soft_reset
-.sym 9261 w_rx_09_fifo_push
-.sym 9262 w_soft_reset
-.sym 9263 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O
+.sym 9020 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[2]
+.sym 9021 w_rx_24_fifo_empty
+.sym 9022 i_smi_a2_SB_LUT4_I1_1_O[3]
+.sym 9023 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[3]
+.sym 9025 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I0_O[1]
+.sym 9026 smi_ctrl_ins.r_fifo_24_pull_1
+.sym 9027 smi_ctrl_ins.r_fifo_09_pull
+.sym 9039 w_rx_24_fifo_pulled_data[23]
+.sym 9041 w_lvds_rx_09_d1
+.sym 9045 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 9046 rx_24_fifo.rd_addr[2]
+.sym 9048 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 9050 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 9051 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
+.sym 9052 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[3]
+.sym 9053 rx_24_fifo.rd_addr[7]
+.sym 9054 w_rx_09_fifo_push
+.sym 9061 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2]
+.sym 9062 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 9063 i_smi_a2_SB_LUT4_I1_O
+.sym 9064 rx_24_fifo.wr_addr[5]
+.sym 9065 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1]
+.sym 9066 w_rx_24_fifo_pulled_data[15]
+.sym 9067 w_rx_24_fifo_pulled_data[7]
+.sym 9068 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I0_O[2]
+.sym 9069 rx_24_fifo.wr_addr[6]
+.sym 9070 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2]
+.sym 9071 i_smi_a3$SB_IO_IN
+.sym 9072 w_soft_reset
+.sym 9074 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[7]
+.sym 9075 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0]
+.sym 9076 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1]
+.sym 9077 smi_ctrl_ins.soe_and_reset
+.sym 9078 rx_24_fifo.wr_addr[2]
+.sym 9079 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[5]
+.sym 9080 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0]
+.sym 9081 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[9]
+.sym 9082 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I0_O[1]
+.sym 9085 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[2]
+.sym 9086 i_smi_a1$SB_IO_IN
+.sym 9087 i_smi_a2_SB_LUT4_I1_1_O[3]
+.sym 9088 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[2]
+.sym 9089 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[6]
+.sym 9090 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 9091 i_smi_a2$SB_IO_IN
+.sym 9092 rx_24_fifo.wr_addr[7]
+.sym 9094 w_rx_24_fifo_pulled_data[7]
+.sym 9095 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 9096 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 9097 w_rx_24_fifo_pulled_data[15]
+.sym 9101 w_soft_reset
+.sym 9102 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[2]
+.sym 9106 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[9]
+.sym 9107 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I0_O[2]
+.sym 9109 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I0_O[1]
+.sym 9112 rx_24_fifo.wr_addr[2]
+.sym 9113 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[2]
+.sym 9114 rx_24_fifo.wr_addr[5]
+.sym 9115 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[5]
+.sym 9118 w_soft_reset
+.sym 9119 i_smi_a2$SB_IO_IN
+.sym 9120 i_smi_a1$SB_IO_IN
+.sym 9121 i_smi_a3$SB_IO_IN
+.sym 9124 i_smi_a2_SB_LUT4_I1_1_O[3]
+.sym 9125 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[2]
+.sym 9126 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[0]
+.sym 9127 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0[1]
+.sym 9130 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[2]
+.sym 9131 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[0]
+.sym 9132 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0[1]
+.sym 9133 i_smi_a2_SB_LUT4_I1_1_O[3]
+.sym 9136 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[6]
+.sym 9137 rx_24_fifo.wr_addr[7]
+.sym 9138 rx_24_fifo.wr_addr[6]
+.sym 9139 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[7]
+.sym 9140 i_smi_a2_SB_LUT4_I1_O
+.sym 9141 smi_ctrl_ins.soe_and_reset
+.sym 9143 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1]
+.sym 9144 smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E
+.sym 9145 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
+.sym 9146 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 9147 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
+.sym 9148 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 9149 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
+.sym 9150 smi_ctrl_ins.int_cnt_24[3]
+.sym 9159 i_smi_a2_SB_LUT4_I1_O
+.sym 9169 rx_24_fifo.wr_addr[3]
+.sym 9171 rx_24_fifo.wr_addr[2]
+.sym 9172 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[3]
+.sym 9174 lvds_rx_09_inst.r_push
+.sym 9177 rx_24_fifo.wr_addr[4]
+.sym 9184 w_rx_24_fifo_pulled_data[16]
+.sym 9190 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
+.sym 9191 rx_24_fifo.rd_addr[8]
+.sym 9192 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 9196 w_rx_24_fifo_pulled_data[12]
+.sym 9198 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_LUT4_O_I1[1]
+.sym 9199 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[8]
+.sym 9200 w_rx_24_fifo_pulled_data[4]
+.sym 9201 w_rx_24_fifo_pulled_data[24]
+.sym 9202 rx_24_fifo.wr_addr_SB_DFFESR_Q_E
+.sym 9207 smi_ctrl_ins.int_cnt_24[3]
+.sym 9211 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
+.sym 9213 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 9215 rx_24_fifo.wr_addr[8]
+.sym 9217 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
+.sym 9223 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 9224 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 9225 w_rx_24_fifo_pulled_data[12]
+.sym 9226 w_rx_24_fifo_pulled_data[4]
+.sym 9236 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
+.sym 9253 w_rx_24_fifo_pulled_data[16]
+.sym 9254 w_rx_24_fifo_pulled_data[24]
+.sym 9255 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 9256 smi_ctrl_ins.int_cnt_24[3]
+.sym 9259 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_LUT4_O_I1[1]
+.sym 9260 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[8]
+.sym 9261 rx_24_fifo.rd_addr[8]
+.sym 9262 rx_24_fifo.wr_addr[8]
+.sym 9263 rx_24_fifo.wr_addr_SB_DFFESR_Q_E
 .sym 9264 lvds_clock_$glb_clk
 .sym 9265 w_soft_reset_$glb_sr
-.sym 9266 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[8]
-.sym 9267 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1]
-.sym 9268 rx_09_fifo.wr_addr[4]
-.sym 9269 rx_09_fifo.wr_addr[2]
-.sym 9270 rx_09_fifo.wr_addr[5]
-.sym 9271 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_I1[0]
-.sym 9272 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[3]
-.sym 9273 rx_09_fifo.wr_addr[3]
-.sym 9278 rx_09_fifo.wr_addr[7]
-.sym 9288 $PACKER_VCC_NET
-.sym 9290 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[2]
-.sym 9294 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2[6]
-.sym 9296 rx_09_fifo.rd_addr[1]
-.sym 9299 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[8]
-.sym 9301 w_rx_09_fifo_full
-.sym 9307 rx_09_fifo.wr_addr[6]
-.sym 9319 rx_09_fifo.wr_addr[8]
-.sym 9325 rx_09_fifo.wr_addr[4]
-.sym 9326 rx_09_fifo.wr_addr[7]
-.sym 9330 rx_09_fifo.wr_addr[3]
-.sym 9332 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1]
-.sym 9334 rx_09_fifo.wr_addr[2]
-.sym 9335 rx_09_fifo.wr_addr[5]
-.sym 9339 $nextpnr_ICESTORM_LC_4$O
-.sym 9342 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1]
-.sym 9345 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[2]
-.sym 9347 rx_09_fifo.wr_addr[2]
-.sym 9349 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1]
-.sym 9351 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3]
-.sym 9353 rx_09_fifo.wr_addr[3]
-.sym 9355 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[2]
-.sym 9357 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[4]
-.sym 9359 rx_09_fifo.wr_addr[4]
-.sym 9361 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[3]
-.sym 9363 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[5]
-.sym 9365 rx_09_fifo.wr_addr[5]
-.sym 9367 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[4]
-.sym 9369 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[6]
-.sym 9371 rx_09_fifo.wr_addr[6]
-.sym 9373 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[5]
-.sym 9375 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[7]
-.sym 9377 rx_09_fifo.wr_addr[7]
-.sym 9379 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[6]
-.sym 9381 $nextpnr_ICESTORM_LC_5$I3
-.sym 9384 rx_09_fifo.wr_addr[8]
-.sym 9385 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[7]
-.sym 9390 rx_09_fifo.rd_addr[1]
-.sym 9391 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[2]
-.sym 9392 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[3]
-.sym 9393 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[4]
-.sym 9394 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[5]
-.sym 9395 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[6]
-.sym 9396 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[7]
-.sym 9404 w_soft_reset
-.sym 9407 rx_09_fifo.wr_addr[8]
-.sym 9413 rx_09_fifo.rd_addr[8]
-.sym 9416 rx_09_fifo.rd_addr[7]
-.sym 9420 w_rx_09_fifo_push
-.sym 9424 rx_09_fifo.rd_addr[3]
-.sym 9425 $nextpnr_ICESTORM_LC_5$I3
-.sym 9431 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1]
-.sym 9432 rx_09_fifo.rd_addr[2]
-.sym 9433 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2[3]
-.sym 9434 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
-.sym 9435 rx_09_fifo.rd_addr[5]
-.sym 9436 rx_09_fifo.rd_addr[6]
-.sym 9437 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2[7]
-.sym 9439 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1]
-.sym 9440 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2[2]
-.sym 9441 rx_09_fifo.rd_addr[3]
-.sym 9442 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2[4]
-.sym 9443 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2[5]
-.sym 9444 w_rx_09_fifo_push
-.sym 9445 rx_09_fifo.rd_addr[7]
-.sym 9446 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[8]
-.sym 9447 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
-.sym 9448 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0[1]
-.sym 9449 rx_09_fifo.full_o_SB_LUT4_I2_I3[0]
-.sym 9450 rx_09_fifo.rd_addr[8]
-.sym 9451 rx_09_fifo.full_o_SB_LUT4_I2_O[2]
-.sym 9452 rx_09_fifo.full_o_SB_LUT4_I2_O[0]
-.sym 9454 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2[6]
-.sym 9455 rx_09_fifo.full_o_SB_LUT4_I2_O[1]
-.sym 9456 rx_09_fifo.rd_addr[1]
-.sym 9458 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0[3]
-.sym 9459 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1]
-.sym 9460 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0[2]
-.sym 9461 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0[0]
-.sym 9466 $nextpnr_ICESTORM_LC_5$I3
-.sym 9469 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0[2]
-.sym 9470 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0[0]
-.sym 9471 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0[3]
-.sym 9472 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0[1]
-.sym 9475 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1]
-.sym 9476 rx_09_fifo.full_o_SB_LUT4_I2_I3[0]
-.sym 9477 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1]
-.sym 9478 rx_09_fifo.rd_addr[1]
-.sym 9481 w_rx_09_fifo_push
-.sym 9482 rx_09_fifo.full_o_SB_LUT4_I2_O[0]
-.sym 9483 rx_09_fifo.full_o_SB_LUT4_I2_O[2]
-.sym 9484 rx_09_fifo.full_o_SB_LUT4_I2_O[1]
-.sym 9487 rx_09_fifo.rd_addr[6]
-.sym 9488 rx_09_fifo.rd_addr[5]
-.sym 9489 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2[5]
-.sym 9490 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2[4]
-.sym 9493 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]
-.sym 9494 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
-.sym 9495 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2[3]
-.sym 9496 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[8]
-.sym 9499 rx_09_fifo.rd_addr[8]
-.sym 9500 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2[7]
-.sym 9501 rx_09_fifo.rd_addr[7]
-.sym 9502 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2[6]
-.sym 9505 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2[1]
-.sym 9506 rx_09_fifo.rd_addr[2]
-.sym 9507 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2[2]
-.sym 9508 rx_09_fifo.rd_addr[3]
+.sym 9267 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[1]
+.sym 9268 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[2]
+.sym 9269 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[3]
+.sym 9270 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[4]
+.sym 9271 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[5]
+.sym 9272 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[6]
+.sym 9273 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[7]
+.sym 9278 rx_24_fifo.wr_addr[6]
+.sym 9283 smi_ctrl_ins.int_cnt_24[3]
+.sym 9286 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
+.sym 9287 smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E
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+.sym 9292 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 9293 rx_24_fifo.wr_addr[5]
+.sym 9294 w_rx_24_fifo_push
+.sym 9295 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1]
+.sym 9299 w_soft_reset
+.sym 9300 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1]
+.sym 9301 rx_24_fifo.wr_addr[8]
+.sym 9307 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1]
+.sym 9311 w_rx_24_fifo_pulled_data[22]
+.sym 9313 rx_24_fifo.rd_addr[1]
+.sym 9314 smi_ctrl_ins.int_cnt_24[3]
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+.sym 9317 w_rx_24_fifo_pulled_data[21]
+.sym 9320 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 9321 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 9322 smi_ctrl_ins.int_cnt_24[3]
+.sym 9324 w_rx_24_fifo_pulled_data[30]
+.sym 9325 w_rx_24_fifo_pulled_data[17]
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+.sym 9327 w_rx_24_fifo_pulled_data[26]
+.sym 9328 w_rx_24_fifo_pulled_data[29]
+.sym 9329 w_rx_24_fifo_pulled_data[27]
+.sym 9332 w_rx_24_fifo_pulled_data[28]
+.sym 9333 w_rx_24_fifo_pulled_data[25]
+.sym 9334 lvds_rx_09_inst.r_push
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+.sym 9340 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 9341 w_rx_24_fifo_pulled_data[20]
+.sym 9342 w_rx_24_fifo_pulled_data[28]
+.sym 9343 smi_ctrl_ins.int_cnt_24[3]
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+.sym 9347 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 9348 w_rx_24_fifo_pulled_data[21]
+.sym 9349 smi_ctrl_ins.int_cnt_24[3]
+.sym 9352 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 9353 smi_ctrl_ins.int_cnt_24[3]
+.sym 9354 w_rx_24_fifo_pulled_data[26]
+.sym 9355 w_rx_24_fifo_pulled_data[18]
+.sym 9358 smi_ctrl_ins.int_cnt_24[3]
+.sym 9359 w_rx_24_fifo_pulled_data[27]
+.sym 9360 w_rx_24_fifo_pulled_data[19]
+.sym 9361 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 9364 w_rx_24_fifo_pulled_data[22]
+.sym 9365 smi_ctrl_ins.int_cnt_24[3]
+.sym 9366 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 9367 w_rx_24_fifo_pulled_data[30]
+.sym 9373 lvds_rx_09_inst.r_push
+.sym 9376 rx_24_fifo.rd_addr[1]
+.sym 9377 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 9378 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1]
+.sym 9379 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1]
+.sym 9382 w_rx_24_fifo_pulled_data[25]
+.sym 9383 w_rx_24_fifo_pulled_data[17]
+.sym 9384 smi_ctrl_ins.int_cnt_24[3]
+.sym 9385 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 9387 lvds_clock_$glb_clk
+.sym 9388 w_soft_reset_$glb_sr
+.sym 9389 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[8]
+.sym 9390 w_rx_24_fifo_full
+.sym 9392 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3]
+.sym 9393 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 9394 rx_24_fifo.full_o_SB_LUT4_I3_O[3]
+.sym 9395 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
+.sym 9396 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[0]
+.sym 9418 i_smi_a1$SB_IO_IN
+.sym 9419 lvds_rx_09_inst.r_data[1]
+.sym 9424 w_rx_24_fifo_full
+.sym 9431 rx_24_fifo.full_o_SB_LUT4_I3_I2[1]
+.sym 9432 rx_24_fifo.full_o_SB_LUT4_I3_I2[2]
+.sym 9433 rx_24_fifo.full_o_SB_LUT4_I3_I2[3]
+.sym 9434 w_soft_reset
+.sym 9435 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
+.sym 9436 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
+.sym 9442 rx_24_fifo.full_o_SB_LUT4_I3_I2[4]
+.sym 9444 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 9445 rx_24_fifo.full_o_SB_LUT4_I3_I2[7]
+.sym 9447 rx_24_fifo.rd_addr[6]
+.sym 9449 rx_24_fifo.rd_addr[7]
+.sym 9454 w_rx_24_fifo_push
+.sym 9457 rx_24_fifo.wr_addr_SB_DFFESR_Q_E
+.sym 9459 rx_24_fifo.rd_addr[3]
+.sym 9461 rx_24_fifo.rd_addr[5]
+.sym 9464 rx_24_fifo.full_o_SB_LUT4_I3_I2[1]
+.sym 9471 rx_24_fifo.full_o_SB_LUT4_I3_I2[3]
+.sym 9475 rx_24_fifo.full_o_SB_LUT4_I3_I2[2]
+.sym 9481 w_rx_24_fifo_push
+.sym 9484 w_soft_reset
+.sym 9487 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
+.sym 9488 rx_24_fifo.full_o_SB_LUT4_I3_I2[3]
+.sym 9489 rx_24_fifo.rd_addr[3]
+.sym 9490 rx_24_fifo.rd_addr[6]
+.sym 9495 rx_24_fifo.full_o_SB_LUT4_I3_I2[4]
+.sym 9500 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 9505 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
+.sym 9506 rx_24_fifo.full_o_SB_LUT4_I3_I2[7]
+.sym 9507 rx_24_fifo.rd_addr[7]
+.sym 9508 rx_24_fifo.rd_addr[5]
+.sym 9509 rx_24_fifo.wr_addr_SB_DFFESR_Q_E
 .sym 9510 lvds_clock_$glb_clk
 .sym 9511 w_soft_reset_$glb_sr
-.sym 9512 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[8]
-.sym 9514 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[9]
-.sym 9515 rx_09_fifo.rd_addr_SB_DFFESR_Q_E
-.sym 9516 w_rx_09_fifo_full
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-.sym 9518 rx_09_fifo.full_o_SB_LUT4_I2_O[0]
-.sym 9519 rx_09_fifo.full_o_SB_LUT4_I2_I3[3]
-.sym 9535 $PACKER_VCC_NET
-.sym 9542 rx_09_fifo.rd_addr[7]
-.sym 9554 rx_09_fifo.rd_addr[1]
-.sym 9555 rx_09_fifo.rd_addr[2]
-.sym 9558 rx_09_fifo.rd_addr[5]
-.sym 9565 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
-.sym 9572 rx_09_fifo.rd_addr[3]
-.sym 9574 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1[1]
-.sym 9575 rx_09_fifo.rd_addr[6]
-.sym 9580 rx_09_fifo.rd_addr_SB_DFFESR_Q_E
-.sym 9584 rx_09_fifo.rd_addr[7]
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+.sym 9514 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[1]
+.sym 9516 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1]
+.sym 9517 rx_24_fifo.wr_addr[8]
+.sym 9518 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
+.sym 9519 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0]
+.sym 9538 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
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+.sym 9555 rx_24_fifo.wr_addr[2]
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+.sym 9561 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1]
+.sym 9562 rx_24_fifo.wr_addr[3]
+.sym 9563 rx_24_fifo.wr_addr[5]
+.sym 9564 rx_24_fifo.wr_addr[6]
+.sym 9566 rx_24_fifo.wr_addr[4]
+.sym 9577 rx_24_fifo.wr_addr[7]
 .sym 9585 $nextpnr_ICESTORM_LC_6$O
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-.sym 9591 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
-.sym 9594 rx_09_fifo.rd_addr[1]
-.sym 9597 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
-.sym 9600 rx_09_fifo.rd_addr[2]
-.sym 9601 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
-.sym 9603 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4]
-.sym 9606 rx_09_fifo.rd_addr[3]
-.sym 9607 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
-.sym 9609 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5]
-.sym 9611 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3[1]
-.sym 9613 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4]
-.sym 9615 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6]
-.sym 9618 rx_09_fifo.rd_addr[5]
-.sym 9619 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5]
-.sym 9621 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7]
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-.sym 9632 rx_09_fifo.rd_addr_SB_DFFESR_Q_E
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-.sym 9687 rx_09_fifo.rd_addr_SB_DFFESR_Q_E
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-.sym 9755 rx_09_fifo.rd_addr_SB_DFFESR_Q_E
-.sym 9756 w_clock_sys
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+.sym 9594 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1]
+.sym 9595 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
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+.sym 9603 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[4]
+.sym 9605 rx_24_fifo.wr_addr[3]
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+.sym 9609 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[5]
+.sym 9612 rx_24_fifo.wr_addr[4]
+.sym 9613 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[4]
+.sym 9615 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[6]
+.sym 9618 rx_24_fifo.wr_addr[5]
+.sym 9619 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[5]
+.sym 9621 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[7]
+.sym 9624 rx_24_fifo.wr_addr[6]
+.sym 9625 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[6]
+.sym 9627 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[8]
+.sym 9630 rx_24_fifo.wr_addr[7]
+.sym 9631 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[7]
+.sym 9659 lvds_rx_09_inst.r_push
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+.sym 9730 w_lvds_rx_09_d1
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 .sym 9757 w_soft_reset_$glb_sr
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-.sym 10164 o_shdn_rx_lna$SB_IO_OUT
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-.sym 10190 o_shdn_rx_lna$SB_IO_OUT
-.sym 10197 i_smi_a1$SB_IO_IN
+.sym 10187 o_shdn_rx_lna$SB_IO_OUT
 .sym 10201 io_smi_data[2]$SB_IO_OUT
 .sym 10204 io_smi_data[1]$SB_IO_OUT
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-.sym 10215 io_smi_data[1]$SB_IO_OUT
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-.sym 10259 io_smi_data[5]$SB_IO_OUT
-.sym 10280 i_smi_a3$SB_IO_IN
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-.sym 10420 io_smi_data[0]$SB_IO_OUT
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-.sym 10517 i_smi_a3$SB_IO_IN
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-.sym 10554 w_soft_reset
-.sym 10556 i_smi_a1_SB_LUT4_I1_O
-.sym 10557 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[2]
-.sym 10560 i_smi_a2_SB_LUT4_I1_O[3]
-.sym 10562 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2]
-.sym 10563 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[1]
-.sym 10565 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0]
-.sym 10566 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[1]
-.sym 10568 i_smi_a2_SB_LUT4_I1_O[3]
-.sym 10572 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0]
-.sym 10573 i_smi_a3$SB_IO_IN
-.sym 10574 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1]
-.sym 10575 w_smi_data_output[2]
-.sym 10578 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0]
-.sym 10580 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2]
-.sym 10581 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2]
-.sym 10600 w_smi_data_output[2]
-.sym 10602 i_smi_a3$SB_IO_IN
-.sym 10605 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[1]
-.sym 10606 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2]
-.sym 10607 i_smi_a2_SB_LUT4_I1_O[3]
-.sym 10608 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0]
-.sym 10612 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[2]
-.sym 10613 w_soft_reset
-.sym 10617 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0]
-.sym 10618 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[1]
-.sym 10619 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[2]
-.sym 10620 i_smi_a2_SB_LUT4_I1_O[3]
-.sym 10629 i_smi_a2_SB_LUT4_I1_O[3]
-.sym 10630 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[1]
-.sym 10631 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2]
-.sym 10632 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0]
-.sym 10633 i_smi_a1_SB_LUT4_I1_O
-.sym 10634 smi_ctrl_ins.soe_and_reset_$glb_clk
-.sym 10637 w_rx_24_fifo_data[31]
-.sym 10638 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[2]
-.sym 10639 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[2]
-.sym 10640 w_rx_24_fifo_data[29]
-.sym 10641 w_rx_24_fifo_data[25]
-.sym 10642 w_rx_24_fifo_data[30]
-.sym 10643 w_rx_24_fifo_data[27]
-.sym 10650 i_smi_a1_SB_LUT4_I1_O
-.sym 10651 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[2]
-.sym 10656 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[0]
-.sym 10661 w_rx_24_fifo_pulled_data[14]
-.sym 10662 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[1]
-.sym 10665 rx_24_fifo.empty_o_SB_LUT4_I2_I3[0]
-.sym 10667 rx_24_fifo.rd_addr[3]
-.sym 10670 w_rx_24_fifo_pulled_data[6]
-.sym 10671 rx_24_fifo.wr_addr[7]
-.sym 10679 lvds_rx_24_inst.r_data[23]
-.sym 10680 lvds_rx_24_inst.r_data[26]
-.sym 10682 lvds_rx_24_inst.r_data[19]
-.sym 10683 lvds_rx_24_inst.r_data[25]
-.sym 10684 lvds_rx_24_inst.r_data[21]
-.sym 10685 w_rx_24_fifo_pulled_data[12]
-.sym 10686 w_rx_24_fifo_pulled_data[4]
-.sym 10688 w_rx_24_fifo_pulled_data[9]
-.sym 10693 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
-.sym 10698 lvds_rx_24_inst.r_data[27]
-.sym 10699 i_smi_a2_SB_LUT4_I1_O_SB_LUT4_O_I3[2]
-.sym 10701 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
-.sym 10703 w_rx_24_fifo_pulled_data[1]
-.sym 10707 i_smi_a2_SB_LUT4_I1_O_SB_LUT4_O_I3[2]
-.sym 10710 w_rx_24_fifo_pulled_data[9]
-.sym 10711 w_rx_24_fifo_pulled_data[1]
-.sym 10712 i_smi_a2_SB_LUT4_I1_O_SB_LUT4_O_I3[2]
-.sym 10713 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
-.sym 10716 w_rx_24_fifo_pulled_data[12]
-.sym 10717 w_rx_24_fifo_pulled_data[4]
-.sym 10718 i_smi_a2_SB_LUT4_I1_O_SB_LUT4_O_I3[2]
-.sym 10719 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
-.sym 10723 lvds_rx_24_inst.r_data[21]
-.sym 10728 lvds_rx_24_inst.r_data[26]
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-.sym 10741 lvds_rx_24_inst.r_data[25]
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-.sym 10754 lvds_rx_24_inst.r_data[19]
-.sym 10756 lvds_rx_24_inst.r_data_SB_DFFESR_Q_E_$glb_ce
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+.sym 10223 io_smi_data[2]$SB_IO_OUT
+.sym 10228 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I0_O[2]
+.sym 10229 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I0[3]
+.sym 10230 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I0[4]
+.sym 10231 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I0[5]
+.sym 10232 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I0[6]
+.sym 10233 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I0[7]
+.sym 10236 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 10239 io_smi_data[2]$SB_IO_OUT
+.sym 10246 io_smi_data[1]$SB_IO_OUT
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+.sym 10275 rx_09_fifo.full_o_SB_LUT4_I3_I2[7]
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+.sym 10281 rx_09_fifo.full_o_SB_LUT4_I3_I2[1]
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+.sym 10288 rx_09_fifo.rd_addr[6]
+.sym 10290 rx_09_fifo.rd_addr[7]
+.sym 10294 io_smi_data[7]$SB_IO_OUT
+.sym 10295 rx_09_fifo.wr_addr_SB_DFFESR_Q_E
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+.sym 10303 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
+.sym 10307 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[5]
+.sym 10308 rx_09_fifo.rd_addr[6]
+.sym 10309 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[6]
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+.sym 10332 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 10343 io_smi_data[7]$SB_IO_OUT
+.sym 10347 rx_09_fifo.wr_addr_SB_DFFESR_Q_E
+.sym 10348 lvds_clock_$glb_clk
+.sym 10349 w_soft_reset_$glb_sr
+.sym 10354 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I0[8]
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+.sym 10356 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[0]
+.sym 10357 spi_if_ins.w_rx_data[6]
+.sym 10358 spi_if_ins.w_rx_data[3]
+.sym 10359 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[3]
+.sym 10360 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[2]
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+.sym 10366 rx_09_fifo.empty_o_SB_LUT4_I0_O[1]
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+.sym 10376 rx_09_fifo.wr_addr[7]
+.sym 10380 io_smi_data[0]$SB_IO_OUT
+.sym 10385 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
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+.sym 10404 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I2[2]
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+.sym 10414 rx_09_fifo.wr_addr[7]
+.sym 10415 rx_09_fifo.rd_addr_SB_DFFESR_Q_E
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+.sym 10417 rx_09_fifo.rd_addr[2]
+.sym 10418 rx_09_fifo.wr_addr[5]
+.sym 10425 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_I2_O
+.sym 10431 rx_09_fifo.empty_o_SB_LUT4_I0_O[1]
+.sym 10432 rx_09_fifo.wr_addr[6]
+.sym 10433 rx_09_fifo.wr_addr[5]
+.sym 10435 rx_09_fifo.wr_addr[4]
+.sym 10436 rx_09_fifo.wr_addr[2]
+.sym 10437 rx_09_fifo.wr_addr[8]
+.sym 10442 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[1]
+.sym 10443 rx_09_fifo.wr_addr[7]
+.sym 10463 $nextpnr_ICESTORM_LC_0$O
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+.sym 10469 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[2]
+.sym 10472 rx_09_fifo.wr_addr[2]
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+.sym 10475 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[3]
+.sym 10478 rx_09_fifo.empty_o_SB_LUT4_I0_O[1]
+.sym 10479 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[2]
+.sym 10481 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[4]
+.sym 10483 rx_09_fifo.wr_addr[4]
+.sym 10485 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[3]
+.sym 10487 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[5]
+.sym 10490 rx_09_fifo.wr_addr[5]
+.sym 10491 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[4]
+.sym 10493 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[6]
+.sym 10496 rx_09_fifo.wr_addr[6]
+.sym 10497 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[5]
+.sym 10499 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[7]
+.sym 10501 rx_09_fifo.wr_addr[7]
+.sym 10503 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[6]
+.sym 10505 $nextpnr_ICESTORM_LC_1$I3
+.sym 10507 rx_09_fifo.wr_addr[8]
+.sym 10509 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[7]
+.sym 10515 rx_09_fifo.rd_addr[2]
+.sym 10516 rx_09_fifo.empty_o_SB_LUT4_I0_O[0]
+.sym 10517 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I2[2]
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+.sym 10519 rx_09_fifo.rd_addr[6]
+.sym 10520 rx_09_fifo.rd_addr[7]
+.sym 10529 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[1]
+.sym 10537 rx_09_fifo.rd_addr[1]
+.sym 10539 rx_09_fifo.wr_addr[2]
+.sym 10540 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[3]
+.sym 10541 rx_09_fifo.wr_addr[8]
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+.sym 10547 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0]
+.sym 10548 io_smi_data[0]$SB_IO_OUT
+.sym 10549 $nextpnr_ICESTORM_LC_1$I3
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+.sym 10558 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
+.sym 10559 rx_09_fifo.full_o_SB_LUT4_I3_I2[2]
+.sym 10560 rx_09_fifo.full_o_SB_LUT4_I3_I2[8]
+.sym 10561 rx_09_fifo.full_o_SB_LUT4_I3_I2[5]
+.sym 10563 rx_09_fifo.full_o_SB_LUT4_I3_I2[6]
+.sym 10565 rx_09_fifo.wr_addr_SB_DFFESR_Q_E
+.sym 10567 rx_09_fifo.full_o_SB_LUT4_I3_I2[4]
+.sym 10568 rx_09_fifo.wr_addr[8]
+.sym 10569 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[7]
+.sym 10570 rx_09_fifo.rd_addr[8]
+.sym 10577 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[1]
+.sym 10584 rx_09_fifo.rd_addr[1]
+.sym 10590 $nextpnr_ICESTORM_LC_1$I3
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+.sym 10602 rx_09_fifo.full_o_SB_LUT4_I3_I2[5]
+.sym 10605 rx_09_fifo.rd_addr[1]
+.sym 10606 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I0[8]
+.sym 10607 rx_09_fifo.wr_addr[8]
+.sym 10608 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
+.sym 10613 rx_09_fifo.full_o_SB_LUT4_I3_I2[4]
+.sym 10619 rx_09_fifo.full_o_SB_LUT4_I3_I2[2]
+.sym 10623 rx_09_fifo.full_o_SB_LUT4_I3_I2[8]
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+.sym 10630 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[7]
+.sym 10631 rx_09_fifo.rd_addr[1]
+.sym 10632 rx_09_fifo.rd_addr[8]
+.sym 10633 rx_09_fifo.wr_addr_SB_DFFESR_Q_E
+.sym 10634 lvds_clock_$glb_clk
+.sym 10635 w_soft_reset_$glb_sr
+.sym 10636 rx_09_fifo.rd_addr[8]
+.sym 10637 rx_09_fifo.rd_addr_SB_DFFESR_Q_E
+.sym 10638 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3]
+.sym 10639 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1]
+.sym 10640 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
+.sym 10641 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[3]
+.sym 10642 rx_09_fifo.rd_addr[1]
+.sym 10643 rx_09_fifo.full_o_SB_LUT4_I3_O[0]
+.sym 10644 rx_09_fifo.wr_addr[4]
+.sym 10650 rx_09_fifo.wr_addr[2]
+.sym 10652 rx_09_fifo.wr_addr[6]
+.sym 10653 o_miso_$_TBUF__Y_E
+.sym 10654 rx_09_fifo.wr_addr[5]
+.sym 10655 w_rx_09_fifo_data[19]
+.sym 10657 smi_ctrl_ins.soe_and_reset
+.sym 10658 rx_09_fifo.empty_o_SB_LUT4_I0_O[1]
+.sym 10660 rx_09_fifo.rd_addr[2]
+.sym 10661 rx_09_fifo.wr_addr[5]
+.sym 10662 rx_09_fifo.empty_o_SB_LUT4_I0_O[0]
+.sym 10665 rx_09_fifo.empty_o_SB_LUT4_I0_O[1]
+.sym 10677 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[8]
+.sym 10678 rx_09_fifo.wr_addr[6]
+.sym 10680 rx_09_fifo.empty_o_SB_LUT4_I0_I1[2]
+.sym 10681 rx_09_fifo.wr_addr[4]
+.sym 10682 rx_09_fifo.wr_addr[7]
+.sym 10683 rx_09_fifo.rd_addr[6]
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+.sym 10685 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I2[2]
+.sym 10686 lvds_rx_09_inst.r_data[17]
+.sym 10687 rx_09_fifo.wr_addr[5]
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+.sym 10690 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I2[0]
+.sym 10691 rx_09_fifo.wr_addr[8]
+.sym 10692 rx_09_fifo.rd_addr[7]
+.sym 10693 rx_09_fifo.rd_addr[8]
+.sym 10694 rx_09_fifo.rd_addr[2]
+.sym 10695 rx_09_fifo.empty_o_SB_LUT4_I0_I1[1]
+.sym 10696 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1]
+.sym 10697 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
+.sym 10698 w_rx_09_fifo_empty
+.sym 10699 rx_09_fifo.wr_addr[2]
+.sym 10700 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[3]
+.sym 10702 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[4]
+.sym 10706 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 10708 rx_09_fifo.empty_o_SB_LUT4_I0_I1[3]
+.sym 10710 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[8]
+.sym 10711 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[3]
+.sym 10712 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
+.sym 10713 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I2[2]
+.sym 10716 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I2[2]
+.sym 10717 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I2[0]
+.sym 10718 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I2[3]
+.sym 10719 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[4]
+.sym 10722 rx_09_fifo.wr_addr[4]
+.sym 10723 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I2[2]
+.sym 10724 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I2[0]
+.sym 10725 rx_09_fifo.wr_addr[5]
+.sym 10728 rx_09_fifo.wr_addr[6]
+.sym 10729 rx_09_fifo.rd_addr[6]
+.sym 10730 rx_09_fifo.rd_addr[2]
+.sym 10731 rx_09_fifo.wr_addr[2]
+.sym 10734 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 10737 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1]
+.sym 10740 rx_09_fifo.empty_o_SB_LUT4_I0_I1[2]
+.sym 10741 rx_09_fifo.empty_o_SB_LUT4_I0_I1[1]
+.sym 10742 w_rx_09_fifo_empty
+.sym 10743 rx_09_fifo.empty_o_SB_LUT4_I0_I1[3]
+.sym 10748 lvds_rx_09_inst.r_data[17]
+.sym 10752 rx_09_fifo.wr_addr[7]
+.sym 10753 rx_09_fifo.rd_addr[8]
+.sym 10754 rx_09_fifo.wr_addr[8]
+.sym 10755 rx_09_fifo.rd_addr[7]
+.sym 10756 lvds_rx_09_inst.r_state_if_SB_LUT4_I3_O_$glb_ce
 .sym 10757 lvds_clock_$glb_clk
 .sym 10758 w_soft_reset_$glb_sr
-.sym 10759 rx_24_fifo.wr_addr[6]
-.sym 10760 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
-.sym 10761 rx_24_fifo.empty_o_SB_LUT4_I2_I3[1]
-.sym 10762 rx_24_fifo.wr_addr_SB_DFFESR_Q_E
-.sym 10764 rx_24_fifo.wr_addr[5]
-.sym 10772 w_rx_09_fifo_full
-.sym 10781 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
-.sym 10783 rx_09_fifo.wr_addr[2]
-.sym 10785 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0]
-.sym 10786 rx_24_fifo.full_o_SB_LUT4_I3_I2[1]
-.sym 10788 rx_24_fifo.full_o_SB_LUT4_I3_I2[2]
-.sym 10791 rx_09_fifo.wr_addr[8]
-.sym 10792 rx_24_fifo.rd_addr[1]
-.sym 10793 rx_09_fifo.full_o_SB_LUT4_I2_I3[0]
-.sym 10794 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
-.sym 10808 lvds_rx_24_inst.r_data[22]
-.sym 10809 lvds_rx_24_inst.r_data[20]
-.sym 10812 lvds_rx_24_inst.r_data[24]
-.sym 10814 lvds_rx_24_inst.r_data[17]
-.sym 10816 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
-.sym 10821 w_rx_24_fifo_pulled_data[14]
-.sym 10824 lvds_rx_24_inst.r_data[15]
-.sym 10827 lvds_rx_24_inst.r_data[18]
-.sym 10830 w_rx_24_fifo_pulled_data[6]
-.sym 10831 i_smi_a2_SB_LUT4_I1_O_SB_LUT4_O_I3[2]
-.sym 10833 lvds_rx_24_inst.r_data[20]
-.sym 10842 lvds_rx_24_inst.r_data[18]
-.sym 10845 i_smi_a2_SB_LUT4_I1_O_SB_LUT4_O_I3[2]
-.sym 10846 w_rx_24_fifo_pulled_data[14]
-.sym 10847 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
-.sym 10848 w_rx_24_fifo_pulled_data[6]
-.sym 10853 lvds_rx_24_inst.r_data[24]
-.sym 10858 lvds_rx_24_inst.r_data[22]
-.sym 10863 lvds_rx_24_inst.r_data[17]
-.sym 10870 lvds_rx_24_inst.r_data[15]
-.sym 10879 lvds_rx_24_inst.r_data_SB_DFFESR_Q_E_$glb_ce
+.sym 10759 io_smi_data[3]$SB_IO_OUT
+.sym 10760 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2]
+.sym 10761 smi_ctrl_ins.r_fifo_24_pull
+.sym 10762 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1]
+.sym 10763 smi_ctrl_ins.r_fifo_09_pull_1
+.sym 10764 w_rx_09_fifo_empty
+.sym 10765 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
+.sym 10766 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3]
+.sym 10771 rx_09_fifo.full_o_SB_LUT4_I3_I2[4]
+.sym 10772 rx_09_fifo.rd_addr[1]
+.sym 10775 rx_09_fifo.full_o_SB_LUT4_I3_I2[5]
+.sym 10777 rx_09_fifo.full_o_SB_LUT4_I3_I2[6]
+.sym 10780 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 10782 w_rx_09_fifo_pulled_data[15]
+.sym 10783 smi_ctrl_ins.int_cnt_09[3]
+.sym 10786 w_rx_09_fifo_empty
+.sym 10789 smi_ctrl_ins.int_cnt_09[4]
+.sym 10793 w_smi_read_req
+.sym 10794 w_rx_09_fifo_full
+.sym 10800 lvds_rx_09_inst.r_data[5]
+.sym 10801 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[2]
+.sym 10803 lvds_rx_09_inst.r_data[1]
+.sym 10805 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[1]
+.sym 10808 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2[2]
+.sym 10809 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2[1]
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+.sym 10812 lvds_rx_09_inst.r_data[9]
+.sym 10814 w_rx_09_fifo_push
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+.sym 10822 rx_09_fifo.empty_o_SB_LUT4_I0_O[0]
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+.sym 10831 lvds_rx_09_inst.r_data[7]
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+.sym 10864 rx_09_fifo.empty_o_SB_LUT4_I0_O[0]
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+.sym 10866 rx_09_fifo.rd_addr[2]
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+.sym 10879 lvds_rx_09_inst.r_state_if_SB_LUT4_I3_O_$glb_ce
 .sym 10880 lvds_clock_$glb_clk
 .sym 10881 w_soft_reset_$glb_sr
-.sym 10882 rx_24_fifo.wr_addr[3]
-.sym 10883 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
-.sym 10884 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
-.sym 10885 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
-.sym 10886 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2]
-.sym 10887 rx_24_fifo.wr_addr[7]
-.sym 10888 rx_24_fifo.wr_addr[4]
-.sym 10889 rx_24_fifo.wr_addr[8]
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-.sym 10902 lvds_rx_24_inst.r_data[26]
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-.sym 10906 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
-.sym 10907 rx_24_fifo.full_o_SB_LUT4_I3_I2[8]
-.sym 10908 w_rx_24_fifo_data[14]
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-.sym 10912 rx_24_fifo.rd_addr[6]
-.sym 10913 rx_24_fifo.wr_addr[8]
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-.sym 10917 i_smi_a2_SB_LUT4_I1_O_SB_LUT4_O_I3[2]
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+.sym 10884 smi_ctrl_ins.w_fifo_09_pull_trigger
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+.sym 10886 rx_09_fifo.mem_i.0.0.0_WCLKE
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+.sym 10889 smi_ctrl_ins.int_cnt_09[4]
+.sym 10892 w_rx_09_fifo_full
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+.sym 10903 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0]
+.sym 10904 smi_ctrl_ins.int_cnt_09[3]
+.sym 10905 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
+.sym 10906 smi_ctrl_ins.r_fifo_24_pull
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+.sym 10909 w_rx_09_fifo_pulled_data[31]
+.sym 10910 spi_if_ins.state_if_SB_DFFE_Q_D[0]
+.sym 10911 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
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+.sym 10947 w_smi_data_output[2]
+.sym 10948 w_soft_reset
+.sym 10951 i_smi_a3$SB_IO_IN
+.sym 10962 w_smi_data_output[2]
+.sym 10964 i_smi_a3$SB_IO_IN
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+.sym 11001 w_soft_reset
 .sym 11003 lvds_clock_$glb_clk
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-.sym 11007 rx_24_fifo.full_o_SB_LUT4_I3_I2[2]
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-.sym 11010 rx_24_fifo.full_o_SB_LUT4_I3_I2[5]
-.sym 11011 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
-.sym 11012 rx_24_fifo.full_o_SB_LUT4_I3_I2[7]
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-.sym 11030 rx_09_fifo.wr_addr[4]
-.sym 11032 w_rx_24_fifo_data[24]
-.sym 11033 rx_09_fifo.wr_addr[2]
-.sym 11035 $PACKER_VCC_NET
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-.sym 11037 w_cs[0]
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+.sym 11031 $PACKER_VCC_NET
+.sym 11032 smi_ctrl_ins.r_fifo_09_pull
+.sym 11035 rx_24_fifo.wr_addr[7]
+.sym 11037 i_smi_a3$SB_IO_IN
+.sym 11038 i_smi_a2_SB_LUT4_I1_1_O[3]
+.sym 11039 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 11040 w_fetch
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+.sym 11048 i_smi_a2_SB_LUT4_I1_1_O[3]
+.sym 11050 w_soft_reset
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+.sym 11060 w_rx_09_fifo_pulled_data[15]
+.sym 11063 rx_24_fifo.rd_addr[3]
+.sym 11064 smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E
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+.sym 11073 smi_ctrl_ins.int_cnt_09[4]
+.sym 11074 rx_24_fifo.rd_addr[6]
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 .sym 11127 w_soft_reset_$glb_sr
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-.sym 11269 w_rx_24_fifo_data[23]
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-.sym 11278 rx_09_fifo.wr_addr[3]
-.sym 11280 lvds_rx_09_inst.o_debug_state[0]
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-.sym 11295 rx_09_fifo.wr_addr[2]
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-.sym 11300 rx_09_fifo.wr_addr[6]
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-.sym 11302 rx_09_fifo.wr_addr[4]
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-.sym 11320 rx_09_fifo.wr_addr[7]
-.sym 11324 $nextpnr_ICESTORM_LC_10$O
-.sym 11327 rx_09_fifo.full_o_SB_LUT4_I2_I3[0]
-.sym 11330 rx_09_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
-.sym 11332 rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0[1]
-.sym 11334 rx_09_fifo.full_o_SB_LUT4_I2_I3[0]
-.sym 11336 rx_09_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
-.sym 11338 rx_09_fifo.wr_addr[2]
-.sym 11340 rx_09_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
-.sym 11342 rx_09_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4]
-.sym 11344 rx_09_fifo.wr_addr[3]
-.sym 11346 rx_09_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
-.sym 11348 rx_09_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5]
-.sym 11350 rx_09_fifo.wr_addr[4]
-.sym 11352 rx_09_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4]
-.sym 11354 rx_09_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6]
-.sym 11356 rx_09_fifo.wr_addr[5]
-.sym 11358 rx_09_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5]
-.sym 11360 rx_09_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7]
-.sym 11362 rx_09_fifo.wr_addr[6]
-.sym 11364 rx_09_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6]
-.sym 11366 rx_09_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8]
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-.sym 11370 rx_09_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7]
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-.sym 11376 rx_09_fifo.full_o_SB_LUT4_I2_O[1]
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-.sym 11379 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
-.sym 11380 rx_09_fifo.wr_addr[8]
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-.sym 11383 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 11391 rx_09_fifo.rd_addr[3]
-.sym 11394 rx_09_fifo.rd_addr[8]
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-.sym 11403 rx_09_fifo.rd_addr[6]
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-.sym 11416 rx_09_fifo.rd_addr[1]
-.sym 11417 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O
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-.sym 11426 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[3]
-.sym 11427 rx_09_fifo.wr_addr[7]
-.sym 11428 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[5]
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-.sym 11431 rx_09_fifo.wr_addr[6]
-.sym 11437 rx_09_fifo.wr_addr[8]
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-.sym 11448 rx_09_fifo.wr_addr[8]
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-.sym 11472 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[5]
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-.sym 11479 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[3]
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-.sym 11481 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[1]
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-.sym 11485 rx_09_fifo.wr_addr[7]
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-.sym 11493 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[3]
-.sym 11494 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O
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-.sym 11496 w_soft_reset_$glb_sr
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-.sym 11532 $PACKER_VCC_NET
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-.sym 11612 $nextpnr_ICESTORM_LC_8$I3
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-.sym 11617 rx_09_fifo.rd_addr_SB_DFFESR_Q_E
-.sym 11618 w_clock_sys
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+.sym 11440 rx_24_fifo.wr_addr[3]
+.sym 11441 rx_24_fifo.wr_addr[8]
+.sym 11447 $nextpnr_ICESTORM_LC_7$O
+.sym 11450 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1]
+.sym 11453 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[2]
+.sym 11455 rx_24_fifo.wr_addr[2]
+.sym 11457 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1]
+.sym 11459 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3]
+.sym 11462 rx_24_fifo.wr_addr[3]
+.sym 11463 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[2]
+.sym 11465 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[4]
+.sym 11468 rx_24_fifo.wr_addr[4]
+.sym 11469 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3]
+.sym 11471 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[5]
+.sym 11473 rx_24_fifo.wr_addr[5]
+.sym 11475 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[4]
+.sym 11477 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[6]
+.sym 11480 rx_24_fifo.wr_addr[6]
+.sym 11481 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[5]
+.sym 11483 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[7]
+.sym 11486 rx_24_fifo.wr_addr[7]
+.sym 11487 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[6]
+.sym 11489 $nextpnr_ICESTORM_LC_8$I3
+.sym 11492 rx_24_fifo.wr_addr[8]
+.sym 11493 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[7]
+.sym 11497 smi_ctrl_ins.i_cs_SB_LUT4_I2_O[1]
+.sym 11499 w_load
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+.sym 11514 rx_24_fifo.rd_addr[7]
+.sym 11521 w_fetch
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+.sym 11524 w_tx_data_io[2]
+.sym 11526 rx_24_fifo.wr_addr[7]
+.sym 11529 i_smi_a3$SB_IO_IN
+.sym 11533 $nextpnr_ICESTORM_LC_8$I3
+.sym 11538 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[8]
+.sym 11540 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[1]
+.sym 11542 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 11543 rx_24_fifo.wr_addr[4]
+.sym 11544 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 11545 rx_24_fifo.wr_addr[5]
+.sym 11546 w_rx_24_fifo_push
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+.sym 11551 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[5]
+.sym 11552 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
+.sym 11553 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[3]
+.sym 11555 w_rx_24_fifo_full
+.sym 11558 rx_24_fifo.full_o_SB_LUT4_I3_I2[4]
+.sym 11559 rx_24_fifo.full_o_SB_LUT4_I3_O[3]
+.sym 11560 rx_24_fifo.rd_addr[1]
+.sym 11561 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[0]
+.sym 11562 rx_24_fifo.rd_addr[6]
+.sym 11563 rx_24_fifo.full_o_SB_LUT4_I3_I2[1]
+.sym 11564 rx_24_fifo.full_o_SB_LUT4_I3_I2[2]
+.sym 11566 rx_24_fifo.rd_addr[2]
+.sym 11567 rx_24_fifo.rd_addr[4]
+.sym 11569 rx_24_fifo.rd_addr[5]
+.sym 11574 $nextpnr_ICESTORM_LC_8$I3
+.sym 11577 rx_24_fifo.full_o_SB_LUT4_I3_O[3]
+.sym 11578 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 11579 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
+.sym 11580 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 11589 rx_24_fifo.wr_addr[4]
+.sym 11590 rx_24_fifo.rd_addr[4]
+.sym 11591 rx_24_fifo.wr_addr[5]
+.sym 11592 rx_24_fifo.rd_addr[5]
+.sym 11595 rx_24_fifo.full_o_SB_LUT4_I3_I2[4]
+.sym 11596 w_rx_24_fifo_push
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+.sym 11601 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[2]
+.sym 11602 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[1]
+.sym 11603 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[0]
+.sym 11604 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[3]
+.sym 11607 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[8]
+.sym 11608 rx_24_fifo.rd_addr[6]
+.sym 11609 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[5]
+.sym 11610 w_rx_24_fifo_push
+.sym 11613 rx_24_fifo.rd_addr[2]
+.sym 11614 rx_24_fifo.rd_addr[1]
+.sym 11615 rx_24_fifo.full_o_SB_LUT4_I3_I2[2]
+.sym 11616 rx_24_fifo.full_o_SB_LUT4_I3_I2[1]
+.sym 11618 lvds_clock_$glb_clk
 .sym 11619 w_soft_reset_$glb_sr
-.sym 11621 sys_ctrl_ins.reset_cmd
-.sym 11622 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[1]
-.sym 11627 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R
-.sym 11636 rx_09_fifo.rd_addr[8]
-.sym 11637 lvds_rx_09_inst.o_debug_state[1]
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-.sym 11646 w_soft_reset
-.sym 11656 $nextpnr_ICESTORM_LC_8$I3
-.sym 11666 w_soft_reset
-.sym 11668 rx_09_fifo.full_o_SB_LUT4_I2_I3[3]
-.sym 11669 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[8]
-.sym 11670 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[2]
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-.sym 11677 rx_09_fifo.rd_addr[8]
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-.sym 11688 rx_09_fifo.rd_addr_SB_DFFESR_Q_E
-.sym 11692 $PACKER_VCC_NET
-.sym 11693 $nextpnr_ICESTORM_LC_8$COUT
-.sym 11696 $PACKER_VCC_NET
-.sym 11697 $nextpnr_ICESTORM_LC_8$I3
-.sym 11699 $nextpnr_ICESTORM_LC_9$I3
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-.sym 11709 $nextpnr_ICESTORM_LC_9$I3
-.sym 11712 w_soft_reset
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-.sym 11739 rx_09_fifo.wr_addr_SB_DFFESR_Q_D[2]
-.sym 11740 rx_09_fifo.rd_addr_SB_DFFESR_Q_E
-.sym 11741 w_clock_sys
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+.sym 11648 io_ctrl_ins.led1_state_SB_DFFESR_Q_E
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+.sym 11653 rx_24_fifo.rd_addr[4]
+.sym 11655 rx_24_fifo.rd_addr[5]
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+.sym 11673 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1]
+.sym 11674 rx_24_fifo.wr_addr[8]
+.sym 11677 rx_24_fifo.full_o_SB_LUT4_I3_I2[8]
+.sym 11679 rx_24_fifo.rd_addr[1]
+.sym 11684 rx_24_fifo.rd_addr[7]
+.sym 11685 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1]
+.sym 11686 rx_24_fifo.rd_addr[2]
+.sym 11687 rx_24_fifo.wr_addr[2]
+.sym 11688 rx_24_fifo.wr_addr_SB_DFFESR_Q_E
+.sym 11689 rx_24_fifo.rd_addr[8]
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+.sym 11692 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0]
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+.sym 11701 rx_24_fifo.wr_addr[8]
+.sym 11702 rx_24_fifo.wr_addr[2]
+.sym 11703 rx_24_fifo.rd_addr[2]
+.sym 11706 rx_24_fifo.full_o_SB_LUT4_I3_I2[8]
+.sym 11707 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 11708 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1]
+.sym 11709 rx_24_fifo.rd_addr[8]
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+.sym 11719 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1]
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+.sym 11725 rx_24_fifo.full_o_SB_LUT4_I3_I2[8]
+.sym 11730 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0]
+.sym 11731 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1]
+.sym 11732 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2]
+.sym 11733 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3]
+.sym 11736 rx_24_fifo.rd_addr[7]
+.sym 11737 rx_24_fifo.wr_addr[7]
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+.sym 11739 rx_24_fifo.wr_addr[8]
+.sym 11740 rx_24_fifo.wr_addr_SB_DFFESR_Q_E
+.sym 11741 lvds_clock_$glb_clk
 .sym 11742 w_soft_reset_$glb_sr
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-.sym 11749 lvds_rx_09_inst.r_push
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+.sym 11749 io_ctrl_ins.led1_state_SB_DFFESR_Q_E_SB_LUT4_O_I2[0]
+.sym 11774 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
+.sym 11776 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 11868 o_led1$SB_IO_OUT
+.sym 11873 o_led0$SB_IO_OUT
+.sym 11883 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 11885 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
+.sym 11890 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R
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+.sym 12012 o_led1$SB_IO_OUT
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+.sym 12309 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_I2_O
 .sym 12310 io_smi_data[0]$SB_IO_OUT
 .sym 12313 io_smi_data[7]$SB_IO_OUT
-.sym 12322 io_smi_data[7]$SB_IO_OUT
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-.sym 12334 io_smi_data[0]$SB_IO_OUT
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-.sym 12358 w_rx_09_fifo_empty
-.sym 12388 i_smi_a3$SB_IO_IN
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-.sym 12401 rx_24_fifo.rd_addr[1]
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-.sym 12410 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[1]
-.sym 12413 rx_24_fifo.rd_addr[1]
-.sym 12430 w_smi_data_output[7]
-.sym 12431 i_smi_a3$SB_IO_IN
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-.sym 12456 rx_24_fifo.rd_addr_SB_DFFESR_Q_E
-.sym 12457 w_clock_sys
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-.sym 12467 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[4]
-.sym 12468 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[5]
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-.sym 12473 rx_09_fifo.full_o_SB_LUT4_I2_I3[0]
-.sym 12475 rx_24_fifo.rd_addr[1]
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-.sym 12533 io_smi_data[3]$SB_IO_OUT
-.sym 12540 rx_24_fifo.rd_addr[1]
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-.sym 12544 rx_24_fifo.rd_addr[4]
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-.sym 12566 rx_24_fifo.empty_o_SB_LUT4_I2_I3[0]
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-.sym 12572 $nextpnr_ICESTORM_LC_12$O
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-.sym 12586 rx_24_fifo.empty_o_SB_LUT4_I2_I3[0]
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-.sym 12590 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4]
-.sym 12592 rx_24_fifo.rd_addr[3]
-.sym 12594 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
-.sym 12596 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5]
-.sym 12599 rx_24_fifo.rd_addr[4]
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-.sym 12604 rx_24_fifo.rd_addr[5]
-.sym 12606 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5]
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-.sym 12610 rx_24_fifo.rd_addr[6]
-.sym 12612 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6]
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-.sym 12616 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0]
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-.sym 12619 rx_24_fifo.rd_addr_SB_DFFESR_Q_E
-.sym 12620 w_clock_sys
-.sym 12621 w_soft_reset_$glb_sr
-.sym 12622 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[8]
-.sym 12623 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[9]
-.sym 12624 w_smi_read_req
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-.sym 12626 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0]
-.sym 12627 smi_ctrl_ins.r_fifo_09_pull_1
-.sym 12628 w_rx_24_fifo_empty
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-.sym 12640 rx_24_fifo.empty_o_SB_LUT4_I2_I3[0]
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-.sym 12644 rx_24_fifo.rd_addr[4]
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-.sym 12647 rx_24_fifo.empty_o_SB_LUT4_I2_I3[0]
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-.sym 12649 rx_24_fifo.rd_addr[3]
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-.sym 12651 rx_24_fifo.rd_addr[4]
-.sym 12653 rx_24_fifo.rd_addr[5]
-.sym 12654 rx_24_fifo.rd_addr[8]
-.sym 12655 rx_24_fifo.rd_addr[6]
-.sym 12656 rx_24_fifo.wr_addr[5]
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-.sym 12658 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8]
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-.sym 12665 rx_24_fifo.rd_addr_SB_DFFESR_Q_E
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-.sym 12685 i_smi_a3$SB_IO_IN
-.sym 12687 rx_24_fifo.rd_addr[8]
-.sym 12688 rx_24_fifo.wr_addr[6]
-.sym 12692 w_soft_reset
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-.sym 12697 rx_24_fifo.rd_addr[8]
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-.sym 12720 i_smi_a3$SB_IO_IN
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-.sym 12739 rx_24_fifo.wr_addr[5]
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-.sym 12741 rx_24_fifo.wr_addr[6]
-.sym 12742 rx_24_fifo.rd_addr_SB_DFFESR_Q_E
-.sym 12743 w_clock_sys
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+.sym 12326 io_smi_data[7]$SB_IO_OUT
+.sym 12339 w_rx_09_fifo_data[16]
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+.sym 12367 i_sck$SB_IO_IN
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+.sym 12405 rx_09_fifo.rd_addr[6]
+.sym 12407 rx_09_fifo.empty_o_SB_LUT4_I0_O[0]
+.sym 12409 $nextpnr_ICESTORM_LC_10$O
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+.sym 12427 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[4]
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+.sym 12436 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I2[2]
+.sym 12437 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[4]
+.sym 12439 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[6]
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+.sym 12445 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[7]
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+.sym 12451 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[8]
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+.sym 12463 io_smi_data[5]$SB_IO_OUT
+.sym 12467 spi_if_ins.spi.r_rx_byte[6]
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+.sym 12515 i_smi_a3$SB_IO_IN
+.sym 12517 w_soft_reset
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+.sym 12535 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[8]
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-.sym 12885 w_rx_24_fifo_pulled_data[9]
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-.sym 12890 w_rx_24_fifo_pulled_data[4]
-.sym 12892 w_tx_data_smi[1]
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-.sym 12894 rx_24_fifo.mem_i.0.0.0_WCLKE
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-.sym 12903 i_smi_a1$SB_IO_IN
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-.sym 12989 lvds_clock_$glb_clk
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+.sym 12751 rx_09_fifo.full_o_SB_LUT4_I3_I2[6]
+.sym 12752 rx_09_fifo.full_o_SB_LUT4_I3_I2[7]
+.sym 12757 smi_ctrl_ins.int_cnt_09[4]
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+.sym 12760 w_smi_read_req
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+.sym 12774 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 12776 w_soft_reset
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+.sym 12778 rx_09_fifo.rd_addr[6]
+.sym 12780 rx_09_fifo.rd_addr[7]
+.sym 12781 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8]
+.sym 12786 rx_09_fifo.rd_addr[8]
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+.sym 12792 rx_09_fifo.rd_addr[6]
+.sym 12795 w_soft_reset
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+.sym 12797 rx_09_fifo.rd_addr_SB_DFFESR_Q_E
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+.sym 12804 rx_09_fifo.full_o_SB_LUT4_I3_I2[2]
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+.sym 12826 w_soft_reset
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+.sym 12867 w_soft_reset_$glb_sr
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+.sym 12870 spi_if_ins.state_if[1]
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+.sym 13057 smi_ctrl_ins.soe_and_reset
+.sym 13059 smi_ctrl_ins.int_cnt_09[4]
+.sym 13062 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 13071 w_soft_reset
+.sym 13077 smi_ctrl_ins.int_cnt_09[4]
+.sym 13079 w_rx_09_fifo_empty
+.sym 13080 smi_ctrl_ins.int_cnt_09[3]
+.sym 13083 w_rx_24_fifo_empty
+.sym 13086 w_rx_09_fifo_empty
+.sym 13089 w_rx_09_fifo_push
+.sym 13092 w_soft_reset
+.sym 13095 w_rx_24_fifo_empty
+.sym 13097 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 13098 smi_ctrl_ins.int_cnt_24[3]
+.sym 13101 w_rx_09_fifo_push
+.sym 13102 rx_09_fifo.full_o_SB_LUT4_I3_I2[8]
+.sym 13103 w_rx_09_fifo_full
+.sym 13104 rx_09_fifo.rd_addr[8]
+.sym 13110 smi_ctrl_ins.int_cnt_09[4]
+.sym 13111 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E
+.sym 13112 smi_ctrl_ins.soe_and_reset
+.sym 13114 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
+.sym 13115 spi_if_ins.state_if_SB_DFFESR_Q_D[0]
+.sym 13117 spi_if_ins.state_if_SB_DFFE_Q_D[1]
+.sym 13118 spi_if_ins.state_if[0]
+.sym 13119 spi_if_ins.state_if_SB_DFFE_Q_E
+.sym 13122 w_rx_09_fifo_pulled_data[28]
+.sym 13127 w_rx_09_fifo_pulled_data[12]
+.sym 13134 rx_09_fifo.wr_addr[5]
+.sym 13135 smi_ctrl_ins.int_cnt_24[3]
+.sym 13137 spi_if_ins.w_rx_data[5]
+.sym 13138 spi_if_ins.o_cs_SB_LUT4_I3_O[3]
+.sym 13140 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
+.sym 13142 spi_if_ins.w_rx_data[6]
+.sym 13143 rx_09_fifo.mem_i.0.0.0_WCLKE
+.sym 13148 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 13157 spi_if_ins.state_if[2]
+.sym 13159 spi_if_ins.state_if_SB_DFFESR_Q_R
+.sym 13162 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 13166 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
+.sym 13175 spi_if_ins.state_if[1]
+.sym 13179 spi_if_ins.state_if_SB_DFFE_Q_D[0]
+.sym 13182 spi_if_ins.state_if_SB_DFFE_Q_D[1]
+.sym 13183 spi_if_ins.state_if[0]
+.sym 13189 spi_if_ins.state_if[0]
+.sym 13190 spi_if_ins.state_if[1]
+.sym 13194 spi_if_ins.state_if_SB_DFFE_Q_D[0]
+.sym 13197 spi_if_ins.state_if[2]
+.sym 13206 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 13208 spi_if_ins.state_if_SB_DFFE_Q_D[0]
+.sym 13209 spi_if_ins.state_if_SB_DFFE_Q_D[1]
+.sym 13213 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 13234 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
+.sym 13235 r_counter_$glb_clk
+.sym 13236 spi_if_ins.state_if_SB_DFFESR_Q_R
+.sym 13240 spi_if_ins.r_tx_byte[6]
+.sym 13241 spi_if_ins.r_tx_byte[0]
+.sym 13249 w_rx_09_fifo_data[3]
+.sym 13251 spi_if_ins.state_if[2]
+.sym 13260 w_rx_09_fifo_data[1]
+.sym 13262 w_cs[1]
+.sym 13265 spi_if_ins.o_ioc_SB_DFFE_Q_E
+.sym 13278 i_glob_clock$SB_IO_IN
+.sym 13281 w_tx_data_sys[0]
+.sym 13282 spi_if_ins.state_if[0]
+.sym 13284 spi_if_ins.state_if[2]
+.sym 13286 spi_if_ins.state_if_SB_DFFE_Q_D[0]
+.sym 13287 spi_if_ins.state_if[1]
+.sym 13290 spi_if_ins.o_cs_SB_LUT4_I3_O[1]
+.sym 13292 spi_if_ins.state_if[2]
+.sym 13298 spi_if_ins.o_cs_SB_LUT4_I3_O[3]
+.sym 13305 r_tx_data_SB_DFFE_Q_E
+.sym 13308 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 13309 smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O[0]
+.sym 13311 smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O[0]
+.sym 13312 spi_if_ins.o_cs_SB_LUT4_I3_O[1]
+.sym 13313 spi_if_ins.o_cs_SB_LUT4_I3_O[3]
+.sym 13314 w_tx_data_sys[0]
+.sym 13323 spi_if_ins.state_if[1]
+.sym 13324 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 13325 spi_if_ins.state_if[0]
+.sym 13326 spi_if_ins.state_if[2]
+.sym 13348 spi_if_ins.state_if_SB_DFFE_Q_D[0]
+.sym 13349 spi_if_ins.state_if[2]
+.sym 13350 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 13357 r_tx_data_SB_DFFE_Q_E
+.sym 13358 i_glob_clock$SB_IO_IN
+.sym 13360 r_tx_data[1]
+.sym 13361 r_tx_data[2]
+.sym 13363 r_tx_data_SB_DFFE_Q_E
+.sym 13364 r_tx_data[3]
+.sym 13365 r_tx_data[5]
+.sym 13366 r_tx_data[6]
+.sym 13367 smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O[0]
+.sym 13368 i_glob_clock$SB_IO_IN
+.sym 13375 w_tx_data_sys[0]
+.sym 13383 w_rx_09_fifo_pulled_data[31]
+.sym 13388 spi_if_ins.state_if_SB_DFFESR_Q_R
+.sym 13395 w_soft_reset
+.sym 13401 w_tx_data_smi[0]
+.sym 13405 spi_if_ins.w_rx_data[5]
+.sym 13411 w_cs[3]
+.sym 13412 w_cs[2]
+.sym 13415 w_tx_data_io[0]
+.sym 13418 spi_if_ins.w_rx_data[6]
+.sym 13420 w_cs[0]
+.sym 13422 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 13423 w_cs[1]
+.sym 13426 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 13428 spi_if_ins.o_ioc_SB_DFFE_Q_E
+.sym 13430 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
+.sym 13434 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 13435 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 13436 w_tx_data_smi[0]
+.sym 13437 w_tx_data_io[0]
+.sym 13440 spi_if_ins.w_rx_data[6]
+.sym 13443 spi_if_ins.w_rx_data[5]
+.sym 13448 spi_if_ins.w_rx_data[5]
+.sym 13449 spi_if_ins.w_rx_data[6]
+.sym 13452 spi_if_ins.w_rx_data[6]
+.sym 13455 spi_if_ins.w_rx_data[5]
+.sym 13458 w_cs[2]
+.sym 13459 w_cs[0]
+.sym 13460 w_cs[1]
+.sym 13461 w_cs[3]
+.sym 13464 w_cs[3]
+.sym 13465 w_cs[1]
+.sym 13466 w_cs[0]
+.sym 13467 w_cs[2]
+.sym 13471 spi_if_ins.w_rx_data[6]
+.sym 13472 spi_if_ins.w_rx_data[5]
+.sym 13480 spi_if_ins.o_ioc_SB_DFFE_Q_E
+.sym 13481 r_counter_$glb_clk
+.sym 13482 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
+.sym 13483 w_ioc[0]
+.sym 13484 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 13485 w_ioc[2]
+.sym 13486 w_cs[0]
+.sym 13487 w_ioc[1]
+.sym 13489 w_ioc[3]
+.sym 13490 w_ioc[4]
+.sym 13498 $PACKER_VCC_NET
+.sym 13500 smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O[0]
+.sym 13503 $PACKER_VCC_NET
+.sym 13505 spi_if_ins.o_cs_SB_LUT4_I3_O[1]
+.sym 13510 w_fetch
+.sym 13514 w_fetch
+.sym 13516 w_cs[1]
+.sym 13526 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.sym 13527 w_rx_24_fifo_empty
+.sym 13528 w_rx_09_fifo_full
+.sym 13529 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 13531 w_rx_09_fifo_empty
+.sym 13541 w_rx_24_fifo_full
+.sym 13543 w_tx_data_smi[2]
+.sym 13544 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[2]
+.sym 13549 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 13555 w_tx_data_io[2]
+.sym 13560 w_rx_09_fifo_empty
+.sym 13566 w_rx_09_fifo_full
+.sym 13575 w_rx_24_fifo_empty
+.sym 13584 w_rx_24_fifo_full
+.sym 13593 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 13594 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 13595 w_tx_data_io[2]
+.sym 13596 w_tx_data_smi[2]
+.sym 13603 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.sym 13604 r_counter_$glb_clk
+.sym 13605 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[2]
+.sym 13606 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E
+.sym 13608 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 13609 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2]
+.sym 13610 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[2]
+.sym 13611 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3[0]
+.sym 13613 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[2]
+.sym 13620 w_rx_data[1]
+.sym 13622 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.sym 13623 spi_if_ins.w_rx_data[2]
+.sym 13624 spi_if_ins.w_rx_data[4]
+.sym 13626 w_rx_data[0]
+.sym 13627 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 13628 rx_24_fifo.rd_addr[4]
+.sym 13632 i_smi_a1$SB_IO_IN
+.sym 13639 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E
+.sym 13647 spi_if_ins.state_if_SB_DFFE_Q_D[0]
+.sym 13649 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
+.sym 13651 w_ioc[1]
+.sym 13658 w_cs[0]
+.sym 13660 spi_if_ins.state_if_SB_DFFESR_Q_R
+.sym 13661 w_cs[2]
+.sym 13665 w_soft_reset
+.sym 13670 w_fetch
+.sym 13673 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 13680 w_ioc[1]
+.sym 13681 w_fetch
+.sym 13682 w_soft_reset
+.sym 13683 w_cs[2]
+.sym 13692 spi_if_ins.state_if_SB_DFFE_Q_D[0]
+.sym 13710 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 13711 w_cs[0]
+.sym 13712 w_fetch
+.sym 13726 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
+.sym 13727 r_counter_$glb_clk
+.sym 13728 spi_if_ins.state_if_SB_DFFESR_Q_R
+.sym 13729 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[2]
+.sym 13730 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
+.sym 13731 io_ctrl_ins.o_pmod[1]
+.sym 13732 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
+.sym 13733 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
+.sym 13734 io_ctrl_ins.led1_state_SB_LUT4_I3_O[3]
+.sym 13735 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R
+.sym 13736 io_ctrl_ins.o_pmod[2]
+.sym 13745 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 13754 w_load
+.sym 13755 w_cs[1]
+.sym 13757 w_soft_reset
+.sym 13759 w_rx_data[1]
+.sym 13760 w_ioc[0]
+.sym 13762 w_cs[1]
+.sym 13764 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
+.sym 13772 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 13778 smi_ctrl_ins.i_cs_SB_LUT4_I2_O[1]
+.sym 13791 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 13797 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
+.sym 13823 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 13835 smi_ctrl_ins.i_cs_SB_LUT4_I2_O[1]
+.sym 13836 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 13849 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
+.sym 13850 r_counter_$glb_clk
+.sym 13852 spi_if_ins.o_load_cmd_SB_LUT4_I3_1_O[0]
+.sym 13853 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I2[2]
+.sym 13854 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E
+.sym 13855 io_ctrl_ins.rf_pin_state[2]
+.sym 13856 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 13858 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I2[3]
+.sym 13864 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E
+.sym 13865 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R
+.sym 13881 w_soft_reset
+.sym 13894 w_fetch
+.sym 13897 w_load
+.sym 13899 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 13901 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
+.sym 13904 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
+.sym 13910 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I2[2]
+.sym 13913 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R
+.sym 13915 io_ctrl_ins.led1_state_SB_DFFESR_Q_E_SB_LUT4_O_I2[0]
+.sym 13917 w_soft_reset
+.sym 13918 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I2[0]
+.sym 13922 w_cs[1]
+.sym 13923 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I2[3]
+.sym 13928 io_ctrl_ins.led1_state_SB_DFFESR_Q_E_SB_LUT4_O_I2[0]
+.sym 13929 w_soft_reset
+.sym 13932 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I2[3]
+.sym 13933 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 13934 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I2[2]
+.sym 13935 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I2[0]
+.sym 13962 w_load
+.sym 13963 w_fetch
+.sym 13964 w_cs[1]
+.sym 13965 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
+.sym 13972 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
+.sym 13973 r_counter_$glb_clk
+.sym 13974 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R
+.sym 13975 io_ctrl_ins.rf_mode_SB_DFFESR_Q_E
+.sym 13976 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I2[0]
+.sym 13977 o_shdn_tx_lna$SB_IO_OUT
+.sym 13978 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
+.sym 13981 o_shdn_rx_lna$SB_IO_OUT
+.sym 13982 io_ctrl_ins.mixer_en_state
+.sym 13987 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E
+.sym 13988 w_fetch
+.sym 14005 o_led0$SB_IO_OUT
+.sym 14027 io_ctrl_ins.led1_state_SB_DFFESR_Q_E
+.sym 14028 w_rx_data[1]
+.sym 14030 w_rx_data[0]
+.sym 14064 w_rx_data[1]
+.sym 14093 w_rx_data[0]
+.sym 14095 io_ctrl_ins.led1_state_SB_DFFESR_Q_E
+.sym 14096 r_counter_$glb_clk
+.sym 14097 w_soft_reset_$glb_sr
+.sym 14113 io_ctrl_ins.led1_state_SB_DFFESR_Q_E
+.sym 14116 o_led1$SB_IO_OUT
+.sym 14121 o_shdn_tx_lna$SB_IO_OUT
+.sym 14123 i_smi_a1$SB_IO_IN
+.sym 14226 lvds_rx_09_inst.r_state_if_SB_LUT4_I3_O
 .sym 14344 i_smi_a1$SB_IO_IN
-.sym 14356 lvds_rx_24_inst.o_debug_state[0]
 .sym 14388 w_soft_reset
-.sym 14401 w_soft_reset
-.sym 14418 smi_ctrl_ins.soe_and_reset
+.sym 14412 w_soft_reset
+.sym 14418 i_sck$SB_IO_IN
 .sym 14419 io_smi_data[3]$SB_IO_OUT
-.sym 14428 io_smi_data[3]$SB_IO_OUT
-.sym 14431 smi_ctrl_ins.soe_and_reset
-.sym 14445 $PACKER_VCC_NET
-.sym 14447 smi_ctrl_ins.soe_and_reset
-.sym 14454 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1]
-.sym 14459 r_tx_data_SB_DFFE_Q_E
-.sym 14466 w_tx_data_smi[3]
+.sym 14437 io_smi_data[3]$SB_IO_OUT
+.sym 14440 i_sck$SB_IO_IN
+.sym 14450 w_rx_09_fifo_data[18]
 .sym 14476 i_smi_a3$SB_IO_IN
-.sym 14486 smi_ctrl_ins.int_cnt_24[3]
-.sym 14487 w_soft_reset
-.sym 14488 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E
-.sym 14496 i_smi_a2_SB_LUT4_I1_O_SB_LUT4_O_I3[2]
-.sym 14508 w_rx_09_fifo_empty
-.sym 14512 smi_ctrl_ins.int_cnt_09[4]
-.sym 14513 smi_ctrl_ins.int_cnt_09[3]
-.sym 14514 w_rx_24_fifo_empty
-.sym 14537 w_rx_24_fifo_empty
-.sym 14538 smi_ctrl_ins.int_cnt_24[3]
-.sym 14539 i_smi_a2_SB_LUT4_I1_O_SB_LUT4_O_I3[2]
-.sym 14551 w_soft_reset
-.sym 14561 smi_ctrl_ins.int_cnt_09[4]
-.sym 14562 smi_ctrl_ins.int_cnt_09[3]
-.sym 14564 w_rx_09_fifo_empty
-.sym 14565 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E
-.sym 14566 smi_ctrl_ins.soe_and_reset_$glb_clk
-.sym 14572 smi_ctrl_ins.r_fifo_24_pull_1
-.sym 14573 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[0]
-.sym 14575 smi_ctrl_ins.r_fifo_09_pull
-.sym 14577 smi_ctrl_ins.r_fifo_24_pull
-.sym 14586 smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E
-.sym 14593 $PACKER_VCC_NET
-.sym 14597 i_smi_soe_se$SB_IO_IN
-.sym 14603 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[0]
-.sym 14606 $PACKER_VCC_NET
-.sym 14614 w_soft_reset
-.sym 14624 $PACKER_VCC_NET
-.sym 14625 smi_ctrl_ins.r_fifo_09_pull
-.sym 14651 rx_24_fifo.empty_o_SB_LUT4_I2_I3[0]
-.sym 14654 rx_24_fifo.rd_addr[5]
-.sym 14655 rx_24_fifo.rd_addr[6]
-.sym 14660 rx_24_fifo.rd_addr[3]
-.sym 14661 rx_24_fifo.rd_addr[4]
-.sym 14664 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O[0]
-.sym 14665 rx_24_fifo.rd_addr[1]
-.sym 14672 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[1]
-.sym 14681 $nextpnr_ICESTORM_LC_13$O
-.sym 14683 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[1]
-.sym 14687 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[2]
-.sym 14689 rx_24_fifo.rd_addr[1]
-.sym 14693 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[3]
-.sym 14696 rx_24_fifo.empty_o_SB_LUT4_I2_I3[0]
-.sym 14697 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[2]
-.sym 14699 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[4]
-.sym 14701 rx_24_fifo.rd_addr[3]
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+.sym 15272 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
+.sym 15273 spi_if_ins.state_if_SB_DFFESR_Q_D[0]
+.sym 15279 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
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+.sym 15304 spi_if_ins.state_if[2]
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+.sym 15315 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
+.sym 15316 spi_if_ins.state_if_SB_DFFESR_Q_D[0]
+.sym 15317 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
+.sym 15318 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 15323 spi_if_ins.state_if_SB_DFFESR_Q_D[0]
+.sym 15327 spi_if_ins.state_if[1]
+.sym 15328 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 15329 spi_if_ins.state_if[0]
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+.sym 15343 spi_if_ins.state_if_SB_DFFE_Q_E
+.sym 15344 r_counter_$glb_clk
+.sym 15345 spi_if_ins.state_if_SB_DFFESR_Q_R
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+.sym 15347 spi_if_ins.r_tx_byte[7]
+.sym 15348 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
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+.sym 15351 spi_if_ins.r_tx_byte[2]
+.sym 15352 spi_if_ins.o_data_in_SB_DFFE_Q_E
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+.sym 15359 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
+.sym 15360 spi_if_ins.state_if_SB_DFFE_Q_E
+.sym 15362 w_rx_09_fifo_data[0]
+.sym 15363 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
+.sym 15369 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
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+.sym 15374 w_rx_data[4]
+.sym 15375 spi_if_ins.o_data_in_SB_DFFE_Q_E
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+.sym 15393 r_tx_data[6]
+.sym 15395 r_tx_data[0]
+.sym 15405 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 15439 r_tx_data[6]
+.sym 15447 r_tx_data[0]
+.sym 15466 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 15467 r_counter_$glb_clk
+.sym 15469 w_rx_data[4]
+.sym 15470 w_rx_data[7]
+.sym 15472 w_rx_data[5]
+.sym 15475 w_rx_data[6]
+.sym 15489 spi_if_ins.r_tx_byte[6]
+.sym 15496 w_tx_data_io[1]
+.sym 15499 w_rx_data[1]
+.sym 15502 w_rx_data[4]
+.sym 15503 w_rx_data[3]
+.sym 15510 i_glob_clock$SB_IO_IN
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+.sym 15512 w_tx_data_io[1]
+.sym 15513 w_cs[2]
+.sym 15514 spi_if_ins.o_cs_SB_LUT4_I3_O[1]
+.sym 15516 w_cs[1]
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+.sym 15520 w_cs[3]
+.sym 15521 w_cs[0]
+.sym 15523 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 15525 smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O[0]
+.sym 15527 w_tx_data_smi[1]
+.sym 15532 w_tx_data_io[3]
+.sym 15534 w_tx_data_io[5]
+.sym 15537 r_tx_data_SB_DFFE_Q_E
+.sym 15538 w_tx_data_smi[3]
+.sym 15540 smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O[1]
+.sym 15543 w_tx_data_io[1]
+.sym 15544 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 15545 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 15546 w_tx_data_smi[1]
+.sym 15549 smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O[1]
+.sym 15550 smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O[0]
+.sym 15561 w_cs[2]
+.sym 15562 w_cs[1]
+.sym 15563 w_cs[3]
+.sym 15564 w_cs[0]
+.sym 15567 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 15568 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 15569 w_tx_data_io[3]
+.sym 15570 w_tx_data_smi[3]
+.sym 15573 w_tx_data_io[5]
+.sym 15575 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 15576 smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O[0]
+.sym 15580 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 15582 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[1]
+.sym 15585 w_cs[2]
+.sym 15586 w_cs[1]
+.sym 15587 w_cs[3]
+.sym 15588 w_cs[0]
 .sym 15589 r_tx_data_SB_DFFE_Q_E
-.sym 15590 w_clock_sys
-.sym 15592 w_ioc[0]
-.sym 15593 w_ioc[1]
-.sym 15594 w_ioc[2]
-.sym 15596 spi_if_ins.o_cs_SB_LUT4_I3_O[1]
-.sym 15597 w_ioc[4]
-.sym 15598 w_ioc[3]
-.sym 15600 spi_if_ins.state_if_SB_DFFE_Q_E
-.sym 15607 r_tx_data_SB_DFFE_Q_E
-.sym 15616 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
-.sym 15619 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I3[1]
-.sym 15622 w_soft_reset
-.sym 15624 spi_if_ins.w_rx_data[0]
-.sym 15625 w_ioc[0]
-.sym 15633 $PACKER_GND_NET
-.sym 15635 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E
-.sym 15638 w_cs[0]
-.sym 15653 w_fetch
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-.sym 15658 w_ioc[1]
-.sym 15662 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
-.sym 15672 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
-.sym 15675 w_ioc[1]
-.sym 15678 w_fetch
-.sym 15679 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
-.sym 15681 w_cs[0]
-.sym 15709 $PACKER_GND_NET
-.sym 15712 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E
-.sym 15713 w_clock_sys
-.sym 15714 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
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-.sym 15716 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 15717 io_ctrl_ins.o_data_out_SB_DFFESR_Q_5_E
-.sym 15719 io_ctrl_ins.o_data_out_SB_DFFESR_Q_5_R[2]
-.sym 15720 w_load
-.sym 15721 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
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-.sym 15731 r_tx_data_SB_DFFE_Q_E
-.sym 15733 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
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-.sym 15736 w_ioc[1]
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-.sym 15767 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
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-.sym 15777 w_load
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-.sym 15780 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I3[2]
-.sym 15781 sys_ctrl_ins.reset_cmd
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-.sym 15796 sys_ctrl_ins.reset_cmd
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-.sym 15809 w_load
+.sym 15590 i_glob_clock$SB_IO_IN
+.sym 15591 spi_if_ins.o_cs_SB_LUT4_I3_O[1]
+.sym 15593 w_rx_data[1]
+.sym 15595 w_rx_data[3]
+.sym 15596 w_rx_data[2]
+.sym 15599 w_rx_data[0]
+.sym 15604 i_glob_clock$SB_IO_IN
+.sym 15605 w_rx_data[6]
+.sym 15607 w_rx_data[5]
+.sym 15611 spi_if_ins.w_rx_data[6]
+.sym 15613 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[1]
+.sym 15614 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E
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+.sym 15618 w_tx_data_io[3]
+.sym 15620 w_tx_data_io[5]
+.sym 15622 spi_if_ins.w_rx_data[1]
+.sym 15624 w_ioc[0]
+.sym 15626 w_soft_reset
+.sym 15634 spi_if_ins.w_rx_data[4]
+.sym 15642 spi_if_ins.w_rx_data[3]
+.sym 15644 spi_if_ins.o_ioc_SB_DFFE_Q_E
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+.sym 15648 spi_if_ins.w_rx_data[1]
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+.sym 15650 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
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+.sym 15655 w_cs[1]
+.sym 15659 w_cs[3]
+.sym 15660 w_cs[2]
+.sym 15666 spi_if_ins.w_rx_data[0]
+.sym 15672 w_cs[0]
+.sym 15673 w_cs[1]
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+.sym 15681 spi_if_ins.w_rx_data[2]
+.sym 15686 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
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+.sym 15710 spi_if_ins.w_rx_data[4]
+.sym 15712 spi_if_ins.o_ioc_SB_DFFE_Q_E
+.sym 15713 r_counter_$glb_clk
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+.sym 15716 w_tx_data_io[1]
+.sym 15717 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[3]
+.sym 15718 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[2]
+.sym 15719 i_button_SB_LUT4_I3_O[1]
+.sym 15720 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 15722 w_tx_data_io[3]
+.sym 15727 w_ioc[0]
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+.sym 15732 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
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+.sym 15735 w_cs[0]
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+.sym 15743 w_rx_data[2]
+.sym 15744 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[2]
+.sym 15745 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[2]
+.sym 15746 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
+.sym 15748 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E
+.sym 15749 w_rx_data[0]
+.sym 15758 w_ioc[2]
+.sym 15759 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2]
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+.sym 15763 w_ioc[4]
+.sym 15764 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[2]
+.sym 15766 w_load
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+.sym 15769 w_cs[1]
+.sym 15771 w_fetch
+.sym 15782 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 15784 i_button_SB_LUT4_I3_O[1]
+.sym 15785 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3[0]
+.sym 15786 w_soft_reset
+.sym 15789 w_fetch
+.sym 15790 w_load
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+.sym 15792 i_button_SB_LUT4_I3_O[1]
+.sym 15801 w_ioc[3]
+.sym 15803 w_ioc[2]
+.sym 15804 w_ioc[4]
+.sym 15808 w_cs[1]
+.sym 15809 w_soft_reset
 .sym 15810 w_fetch
-.sym 15825 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 15826 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I3[2]
-.sym 15828 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I3[1]
-.sym 15835 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
-.sym 15836 w_clock_sys
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-.sym 15838 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I3[2]
-.sym 15840 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O
-.sym 15841 w_rx_data[1]
-.sym 15842 w_tx_data_io[7]
-.sym 15843 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1]
-.sym 15844 io_ctrl_ins.rx_h_state_SB_LUT4_I1_O[2]
-.sym 15845 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[2]
-.sym 15850 $PACKER_GND_NET
-.sym 15854 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E
-.sym 15856 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0]
-.sym 15859 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 15862 io_ctrl_ins.o_data_out_SB_DFFESR_Q_5_E
-.sym 15863 w_ioc[0]
-.sym 15864 io_ctrl_ins.mixer_en_state
-.sym 15865 w_ioc[1]
-.sym 15866 i_button$SB_IO_IN
-.sym 15879 w_rx_data[0]
-.sym 15881 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O
-.sym 15890 w_rx_data[2]
-.sym 15906 w_rx_data[1]
-.sym 15924 w_rx_data[0]
-.sym 15938 w_rx_data[1]
-.sym 15950 w_rx_data[2]
-.sym 15958 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O
-.sym 15959 w_clock_sys
-.sym 15961 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E
-.sym 15962 io_ctrl_ins.pmod_dir_state[1]
-.sym 15963 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E
-.sym 15964 io_ctrl_ins.led0_state_SB_LUT4_I3_O[0]
-.sym 15965 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 15966 io_ctrl_ins.pmod_dir_state[4]
-.sym 15967 io_ctrl_ins.pmod_dir_state[3]
-.sym 15968 i_button_SB_LUT4_I0_I1[0]
-.sym 15986 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 16004 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E
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-.sym 16014 w_ioc[1]
-.sym 16015 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1]
-.sym 16018 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
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-.sym 16060 w_rx_data[1]
-.sym 16066 w_ioc[1]
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-.sym 16080 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
+.sym 15814 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[2]
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+.sym 15820 w_ioc[2]
+.sym 15821 w_ioc[4]
+.sym 15822 w_ioc[3]
+.sym 15831 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 15832 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3[0]
+.sym 15833 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2]
+.sym 15838 io_ctrl_ins.o_pmod[3]
+.sym 15839 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[0]
+.sym 15840 io_ctrl_ins.o_pmod[0]
+.sym 15841 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E
+.sym 15842 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E
+.sym 15843 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S
+.sym 15844 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
+.sym 15845 io_ctrl_ins.led0_state_SB_LUT4_I3_O[2]
+.sym 15852 w_soft_reset
+.sym 15854 io_ctrl_ins.pmod_dir_state[3]
+.sym 15862 i_button$SB_IO_IN
+.sym 15863 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E
+.sym 15865 w_rx_data[2]
+.sym 15869 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3[0]
+.sym 15871 w_rx_data[4]
+.sym 15872 io_ctrl_ins.led0_state_SB_LUT4_I3_O[3]
+.sym 15879 w_cs[1]
+.sym 15881 io_ctrl_ins.o_pmod[1]
+.sym 15883 i_button_SB_LUT4_I3_O[1]
+.sym 15887 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[2]
+.sym 15888 w_ioc[1]
+.sym 15889 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 15892 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3[0]
+.sym 15893 w_fetch
+.sym 15894 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[2]
+.sym 15896 w_ioc[0]
+.sym 15897 w_load
+.sym 15898 w_soft_reset
+.sym 15903 w_rx_data[2]
+.sym 15905 io_ctrl_ins.debug_mode[1]
+.sym 15906 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
+.sym 15907 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
+.sym 15910 w_rx_data[1]
+.sym 15913 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 15914 w_ioc[1]
+.sym 15915 w_ioc[0]
+.sym 15918 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
+.sym 15919 i_button_SB_LUT4_I3_O[1]
+.sym 15926 w_rx_data[1]
+.sym 15930 w_ioc[0]
+.sym 15931 w_ioc[1]
+.sym 15933 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[2]
+.sym 15936 w_cs[1]
+.sym 15937 w_soft_reset
+.sym 15938 w_load
+.sym 15939 w_fetch
+.sym 15942 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[2]
+.sym 15943 i_button_SB_LUT4_I3_O[1]
+.sym 15944 io_ctrl_ins.debug_mode[1]
+.sym 15945 io_ctrl_ins.o_pmod[1]
+.sym 15949 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 15950 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3[0]
+.sym 15951 w_ioc[0]
+.sym 15956 w_rx_data[2]
+.sym 15958 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
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+.sym 15961 io_ctrl_ins.led1_state_SB_LUT4_I3_O[2]
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-.sym 18274 i_config[1]$SB_IO_IN
-.sym 18275 i_button_SB_LUT4_I0_I1[0]
-.sym 18276 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 18285 io_ctrl_ins.rf_pin_state[2]
-.sym 18286 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 18287 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 18288 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
-.sym 18297 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1]
-.sym 18298 io_ctrl_ins.debug_mode[0]
-.sym 18299 i_button_SB_LUT4_I0_I1[0]
-.sym 18300 o_led0$SB_IO_OUT
-.sym 18303 io_ctrl_ins.rf_pin_state[1]
-.sym 18304 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 18305 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
-.sym 18309 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[1]
-.sym 18310 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
-.sym 18311 i_button_SB_LUT4_I0_I1[0]
-.sym 18312 i_config[0]$SB_IO_IN
-.sym 18313 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
-.sym 18314 w_clock_sys
-.sym 18333 io_ctrl_ins.mixer_en_state
-.sym 18335 i_config[3]$SB_IO_IN
-.sym 18337 io_ctrl_ins.o_data_out_SB_DFFESR_Q_5_E
-.sym 18463 i_button_SB_LUT4_I0_I1[1]
+.sym 16470 lvds_rx_09_inst.o_debug_state[0]
+.sym 16497 lvds_rx_09_inst.r_state_if_SB_LUT4_I3_O
+.sym 16512 lvds_rx_09_inst.r_state_if_SB_LUT4_I3_O
+.sym 16555 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 16556 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 16559 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 16572 spi_if_ins.w_rx_data[0]
+.sym 16587 i_mosi$SB_IO_IN
+.sym 16603 lvds_rx_09_inst.r_data[16]
+.sym 16665 lvds_rx_09_inst.r_data[16]
+.sym 16674 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce
+.sym 16675 lvds_clock_$glb_clk
+.sym 16681 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
+.sym 16684 spi_if_ins.spi.r3_rx_done
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+.sym 16686 w_rx_09_fifo_data[18]
+.sym 16687 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 16688 spi_if_ins.spi.r2_rx_done
+.sym 16703 lvds_rx_09_inst.r_data[16]
+.sym 16710 i_ss$SB_IO_IN
+.sym 16724 smi_ctrl_ins.soe_and_reset
+.sym 16727 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E
+.sym 16734 io_smi_data[4]$SB_IO_OUT
+.sym 16735 w_soft_reset
+.sym 16736 i_ss$SB_IO_IN
+.sym 16741 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 16742 smi_ctrl_ins.soe_and_reset
+.sym 16758 i_mosi$SB_IO_IN
+.sym 16760 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 16769 spi_if_ins.spi.r_temp_rx_byte[3]
+.sym 16781 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 16783 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 16785 o_miso_$_TBUF__Y_E
+.sym 16797 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 16803 i_mosi$SB_IO_IN
+.sym 16810 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 16822 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 16836 spi_if_ins.spi.r_temp_rx_byte[3]
+.sym 16837 o_miso_$_TBUF__Y_E
+.sym 16838 i_sck$SB_IO_IN_$glb_clk
+.sym 16840 o_miso_$_TBUF__Y_E
+.sym 16841 smi_ctrl_ins.soe_and_reset
+.sym 16843 o_miso_$_TBUF__Y_E
+.sym 16844 spi_if_ins.spi.r_rx_done
+.sym 16845 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0]
+.sym 16851 spi_if_ins.o_data_in_SB_DFFE_Q_E
+.sym 16853 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 16856 i_ss$SB_IO_IN
+.sym 16866 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
+.sym 16867 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0[0]
+.sym 16868 rx_09_fifo.empty_o_SB_LUT4_I0_O[1]
+.sym 16873 rx_09_fifo.wr_addr[7]
+.sym 16874 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[1]
+.sym 16875 smi_ctrl_ins.soe_and_reset
+.sym 16883 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 16884 i_smi_a3$SB_IO_IN
+.sym 16885 i_ss$SB_IO_IN
+.sym 16886 spi_if_ins.spi.r_temp_rx_byte[6]
+.sym 16888 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 16891 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 16892 spi_if_ins.spi.r_temp_rx_byte[3]
+.sym 16893 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
+.sym 16894 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 16912 w_smi_data_output[4]
+.sym 16920 spi_if_ins.spi.r_temp_rx_byte[6]
+.sym 16927 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 16935 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 16941 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 16946 i_smi_a3$SB_IO_IN
+.sym 16947 w_smi_data_output[4]
+.sym 16950 spi_if_ins.spi.r_temp_rx_byte[3]
+.sym 16958 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D[1]
+.sym 16959 i_ss$SB_IO_IN
+.sym 16960 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 16961 i_sck$SB_IO_IN_$glb_clk
+.sym 16963 spi_if_ins.w_rx_data[5]
+.sym 16964 spi_if_ins.w_rx_data[4]
+.sym 16966 spi_if_ins.w_rx_data[1]
+.sym 16967 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0[0]
+.sym 16969 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0[0]
+.sym 16970 spi_if_ins.w_rx_data[2]
+.sym 16974 w_rx_data[6]
+.sym 16976 rx_09_fifo.wr_addr[8]
+.sym 16979 spi_if_ins.spi.r_rx_byte[7]
+.sym 16981 i_ss$SB_IO_IN
+.sym 16984 w_rx_09_fifo_data[16]
+.sym 16987 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 16996 spi_if_ins.w_rx_data[5]
+.sym 16998 spi_if_ins.w_rx_data[4]
+.sym 17016 lvds_rx_09_inst.r_data[19]
+.sym 17019 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 17049 spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 17067 lvds_rx_09_inst.r_data[19]
+.sym 17083 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_I2_O_$glb_ce
+.sym 17084 lvds_clock_$glb_clk
+.sym 17088 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 17089 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R
+.sym 17090 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0[0]
+.sym 17091 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
+.sym 17092 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 17097 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E
+.sym 17098 w_rx_09_fifo_pulled_data[14]
+.sym 17100 w_rx_09_fifo_data[21]
+.sym 17101 spi_if_ins.w_rx_data[1]
+.sym 17104 lvds_rx_09_inst.r_data[19]
+.sym 17110 int_miso
+.sym 17111 smi_ctrl_ins.int_cnt_09[3]
+.sym 17112 spi_if_ins.w_rx_data[1]
+.sym 17114 spi_if_ins.r_tx_data_valid
+.sym 17117 smi_ctrl_ins.int_cnt_09[4]
+.sym 17120 spi_if_ins.w_rx_data[2]
+.sym 17130 sys_ctrl_ins.reset_count[3]
+.sym 17138 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
+.sym 17139 sys_ctrl_ins.reset_count[0]
+.sym 17140 sys_ctrl_ins.reset_cmd
+.sym 17153 sys_ctrl_ins.reset_count[2]
+.sym 17154 sys_ctrl_ins.reset_count[3]
+.sym 17156 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 17158 sys_ctrl_ins.reset_count[1]
+.sym 17159 $nextpnr_ICESTORM_LC_17$O
+.sym 17161 sys_ctrl_ins.reset_count[0]
+.sym 17165 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
+.sym 17167 sys_ctrl_ins.reset_count[1]
+.sym 17171 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
+.sym 17172 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 17173 sys_ctrl_ins.reset_count[2]
+.sym 17175 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
+.sym 17179 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 17180 sys_ctrl_ins.reset_count[3]
+.sym 17181 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
+.sym 17185 sys_ctrl_ins.reset_count[0]
+.sym 17190 sys_ctrl_ins.reset_count[2]
+.sym 17191 sys_ctrl_ins.reset_count[1]
+.sym 17192 sys_ctrl_ins.reset_count[0]
+.sym 17193 sys_ctrl_ins.reset_count[3]
+.sym 17196 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 17198 sys_ctrl_ins.reset_cmd
+.sym 17203 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 17204 sys_ctrl_ins.reset_count[0]
+.sym 17205 sys_ctrl_ins.reset_count[1]
+.sym 17206 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
+.sym 17207 r_counter_$glb_clk
+.sym 17208 sys_ctrl_ins.reset_cmd
+.sym 17209 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1]
+.sym 17210 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
+.sym 17211 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 17212 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 17213 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
+.sym 17214 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
+.sym 17215 int_miso
+.sym 17216 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[3]
+.sym 17219 w_rx_data[0]
+.sym 17227 w_rx_09_fifo_data[2]
+.sym 17234 spi_if_ins.r_tx_byte[0]
+.sym 17235 spi_if_ins.r_tx_byte[7]
+.sym 17237 w_soft_reset
+.sym 17238 spi_if_ins.spi.r_tx_byte[5]
+.sym 17240 spi_if_ins.state_if[2]
+.sym 17244 smi_ctrl_ins.soe_and_reset
+.sym 17252 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 17253 spi_if_ins.spi.SCKr[1]
+.sym 17255 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
+.sym 17257 spi_if_ins.spi.r_rx_byte[0]
+.sym 17259 spi_if_ins.spi.SCKr[2]
+.sym 17261 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 17263 spi_if_ins.spi.r_rx_byte[7]
+.sym 17295 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 17296 spi_if_ins.spi.SCKr[1]
+.sym 17297 spi_if_ins.spi.SCKr[2]
+.sym 17298 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
+.sym 17310 spi_if_ins.spi.r_rx_byte[0]
+.sym 17316 spi_if_ins.spi.r_rx_byte[7]
+.sym 17329 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 17330 r_counter_$glb_clk
+.sym 17332 spi_if_ins.spi.r_tx_byte[2]
+.sym 17333 spi_if_ins.spi.r_tx_byte[3]
+.sym 17334 spi_if_ins.spi.r_tx_byte[7]
+.sym 17335 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0]
+.sym 17336 spi_if_ins.spi.r_tx_byte[0]
+.sym 17337 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1]
+.sym 17338 spi_if_ins.spi.r_tx_byte[4]
+.sym 17339 spi_if_ins.spi.r_tx_byte[1]
+.sym 17344 w_rx_09_fifo_pulled_data[30]
+.sym 17347 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 17348 w_rx_09_fifo_data[4]
+.sym 17349 spi_if_ins.spi.SCKr[1]
+.sym 17350 w_rx_09_fifo_data[6]
+.sym 17351 i_ss$SB_IO_IN
+.sym 17354 spi_if_ins.w_rx_data[0]
+.sym 17355 spi_if_ins.spi.SCKr[2]
+.sym 17356 smi_ctrl_ins.soe_and_reset
+.sym 17358 w_rx_data[7]
+.sym 17365 r_tx_data[7]
+.sym 17377 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 17381 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
+.sym 17382 spi_if_ins.state_if[2]
+.sym 17384 spi_if_ins.state_if_SB_DFFE_Q_E
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+.sym 17386 spi_if_ins.state_if[1]
+.sym 17387 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
+.sym 17390 spi_if_ins.state_if[2]
+.sym 17404 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 17412 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
+.sym 17437 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 17438 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
+.sym 17442 spi_if_ins.state_if[2]
+.sym 17444 spi_if_ins.state_if[1]
+.sym 17445 spi_if_ins.state_if[0]
+.sym 17448 spi_if_ins.state_if[2]
+.sym 17449 spi_if_ins.state_if[1]
+.sym 17450 spi_if_ins.state_if[0]
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+.sym 17452 spi_if_ins.state_if_SB_DFFE_Q_E
+.sym 17453 r_counter_$glb_clk
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+.sym 17455 spi_if_ins.spi.r_tx_byte[6]
+.sym 17457 spi_if_ins.spi.r_tx_byte[5]
+.sym 17477 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 17479 spi_if_ins.w_rx_data[4]
+.sym 17489 spi_if_ins.w_rx_data[5]
+.sym 17490 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 17496 spi_if_ins.state_if[1]
+.sym 17497 spi_if_ins.state_if[2]
+.sym 17498 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 17501 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 17511 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 17514 r_tx_data[4]
+.sym 17516 r_tx_data[3]
+.sym 17517 r_tx_data[5]
+.sym 17520 r_tx_data[1]
+.sym 17521 r_tx_data[2]
+.sym 17524 spi_if_ins.state_if[0]
+.sym 17525 r_tx_data[7]
+.sym 17530 r_tx_data[5]
+.sym 17536 r_tx_data[7]
+.sym 17544 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 17548 r_tx_data[4]
+.sym 17556 r_tx_data[1]
+.sym 17560 r_tx_data[2]
+.sym 17565 spi_if_ins.state_if[1]
+.sym 17566 spi_if_ins.state_if[2]
+.sym 17567 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 17568 spi_if_ins.state_if[0]
+.sym 17572 r_tx_data[3]
+.sym 17575 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 17576 r_counter_$glb_clk
+.sym 17580 r_tx_data[4]
+.sym 17582 r_tx_data[7]
+.sym 17591 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 17597 w_soft_reset
+.sym 17604 spi_if_ins.w_rx_data[1]
+.sym 17605 spi_if_ins.w_rx_data[2]
+.sym 17609 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O[2]
+.sym 17610 w_rx_data[4]
+.sym 17612 w_rx_data[7]
+.sym 17619 spi_if_ins.w_rx_data[6]
+.sym 17634 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
+.sym 17639 spi_if_ins.w_rx_data[4]
+.sym 17646 spi_if_ins.o_data_in_SB_DFFE_Q_E
+.sym 17649 spi_if_ins.w_rx_data[5]
+.sym 17652 spi_if_ins.w_rx_data[4]
+.sym 17661 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
+.sym 17672 spi_if_ins.w_rx_data[5]
+.sym 17690 spi_if_ins.w_rx_data[6]
+.sym 17698 spi_if_ins.o_data_in_SB_DFFE_Q_E
+.sym 17699 r_counter_$glb_clk
+.sym 17701 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[0]
+.sym 17706 i_button_SB_LUT4_I3_O[0]
+.sym 17713 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R
+.sym 17717 w_tx_data_io[7]
+.sym 17728 w_rx_data[5]
+.sym 17736 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[2]
+.sym 17743 spi_if_ins.w_rx_data[3]
+.sym 17744 spi_if_ins.o_data_in_SB_DFFE_Q_E
+.sym 17758 spi_if_ins.w_rx_data[0]
+.sym 17764 spi_if_ins.w_rx_data[1]
+.sym 17765 spi_if_ins.w_rx_data[2]
+.sym 17782 spi_if_ins.w_rx_data[1]
+.sym 17793 spi_if_ins.w_rx_data[3]
+.sym 17802 spi_if_ins.w_rx_data[2]
+.sym 17818 spi_if_ins.w_rx_data[0]
+.sym 17821 spi_if_ins.o_data_in_SB_DFFE_Q_E
+.sym 17822 r_counter_$glb_clk
+.sym 17825 io_ctrl_ins.led1_state_SB_LUT4_I3_O[0]
+.sym 17827 io_ctrl_ins.pmod_dir_state[5]
+.sym 17828 io_ctrl_ins.led0_state_SB_LUT4_I3_O[0]
+.sym 17829 io_ctrl_ins.pmod_dir_state[3]
+.sym 17830 io_ctrl_ins.pmod_dir_state[4]
+.sym 17831 io_ctrl_ins.pmod_dir_state[7]
+.sym 17838 spi_if_ins.o_data_in_SB_DFFE_Q_E
+.sym 17846 w_rx_data[2]
+.sym 17848 io_ctrl_ins.led1_state_SB_LUT4_I3_O[2]
+.sym 17849 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
+.sym 17850 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 17851 w_rx_data[3]
+.sym 17854 i_config[2]$SB_IO_IN
+.sym 17855 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[0]
+.sym 17856 w_tx_data_io[0]
+.sym 17857 i_config[1]$SB_IO_IN
+.sym 17858 w_rx_data[7]
+.sym 17865 io_ctrl_ins.o_pmod[3]
+.sym 17869 i_button_SB_LUT4_I3_O[1]
+.sym 17870 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3[0]
+.sym 17872 io_ctrl_ins.pmod_dir_state[3]
+.sym 17874 io_ctrl_ins.led1_state_SB_LUT4_I3_O[2]
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+.sym 17880 io_ctrl_ins.led0_state_SB_LUT4_I3_O[2]
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+.sym 17882 io_ctrl_ins.led1_state_SB_LUT4_I3_O[0]
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+.sym 17885 w_ioc[1]
+.sym 17886 io_ctrl_ins.led1_state_SB_LUT4_I3_O[3]
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+.sym 17893 io_ctrl_ins.led0_state_SB_LUT4_I3_O[0]
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+.sym 17899 io_ctrl_ins.led0_state_SB_LUT4_I3_O[3]
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+.sym 17904 io_ctrl_ins.led1_state_SB_LUT4_I3_O[0]
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+.sym 17947 io_ctrl_ins.rf_pin_state[5]
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+.sym 17951 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[3]
+.sym 17952 io_ctrl_ins.rf_pin_state[3]
+.sym 17953 io_ctrl_ins.rf_pin_state[7]
+.sym 17969 i_button_SB_LUT4_I3_O[1]
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+.sym 17976 i_button_SB_LUT4_I3_O[1]
+.sym 17977 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 17979 io_ctrl_ins.pmod_dir_state[4]
+.sym 17989 w_ioc[0]
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+.sym 17992 i_button_SB_LUT4_I3_O[1]
+.sym 17994 w_rx_data[0]
+.sym 17997 w_ioc[1]
+.sym 17998 o_led0$SB_IO_OUT
+.sym 17999 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
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+.sym 18002 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
+.sym 18006 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 18009 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3[0]
+.sym 18011 w_rx_data[3]
+.sym 18017 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3[0]
+.sym 18019 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[2]
+.sym 18022 w_rx_data[3]
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+.sym 18040 w_ioc[1]
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+.sym 18042 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[2]
+.sym 18046 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
+.sym 18047 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 18051 w_ioc[0]
+.sym 18052 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 18053 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[2]
+.sym 18057 w_ioc[1]
+.sym 18058 w_ioc[0]
+.sym 18059 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 18063 o_led0$SB_IO_OUT
+.sym 18064 i_button_SB_LUT4_I3_O[1]
+.sym 18065 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
+.sym 18066 io_ctrl_ins.o_pmod[0]
+.sym 18067 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
+.sym 18068 r_counter_$glb_clk
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+.sym 18073 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[2]
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+.sym 18094 o_rx_h_tx_l$SB_IO_OUT
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+.sym 18114 w_rx_data[0]
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+.sym 18131 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
+.sym 18133 o_led1$SB_IO_OUT
+.sym 18134 io_ctrl_ins.mixer_en_state
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+.sym 18141 o_shdn_rx_lna$SB_IO_OUT
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+.sym 18145 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
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+.sym 18175 i_button$SB_IO_IN
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+.sym 18248 w_rx_data[1]
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+.sym 18437 r_counter_$glb_clk
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-.sym 18564 i_button_SB_LUT4_I0_I1[1]
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 .sym 18636 io_smi_data[4]$SB_IO_OUT
 .sym 18641 i_smi_a3$SB_IO_IN
 .sym 18645 i_smi_a3$SB_IO_IN
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+.sym 19265 smi_ctrl_ins.int_cnt_09[4]
+.sym 19267 $nextpnr_ICESTORM_LC_16$O
+.sym 19270 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
+.sym 19273 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
+.sym 19275 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 19276 $PACKER_VCC_NET
+.sym 19280 $PACKER_VCC_NET
+.sym 19282 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 19283 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
+.sym 19288 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
+.sym 19292 w_rx_09_fifo_pulled_data[8]
+.sym 19293 w_rx_09_fifo_pulled_data[24]
+.sym 19294 smi_ctrl_ins.int_cnt_09[3]
+.sym 19295 smi_ctrl_ins.int_cnt_09[4]
+.sym 19301 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
+.sym 19304 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
+.sym 19306 $PACKER_VCC_NET
+.sym 19307 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 19314 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 19315 r_counter_$glb_clk
+.sym 19316 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R
+.sym 19317 w_rx_09_fifo_pulled_data[28]
+.sym 19319 w_rx_09_fifo_pulled_data[29]
+.sym 19321 w_rx_09_fifo_pulled_data[30]
+.sym 19323 w_rx_09_fifo_pulled_data[31]
+.sym 19332 rx_09_fifo.empty_o_SB_LUT4_I0_O[1]
+.sym 19333 rx_09_fifo.wr_addr[7]
+.sym 19334 rx_09_fifo.wr_addr[4]
+.sym 19335 rx_09_fifo.wr_addr[6]
+.sym 19336 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[1]
+.sym 19339 smi_ctrl_ins.int_cnt_09[3]
+.sym 19342 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 19346 w_rx_09_fifo_pulled_data[31]
+.sym 19348 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1]
+.sym 19358 i_ss$SB_IO_IN
+.sym 19359 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 19360 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 19362 spi_if_ins.spi.SCKr[2]
+.sym 19363 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
+.sym 19364 spi_if_ins.spi.r_tx_byte[4]
+.sym 19366 spi_if_ins.r_tx_data_valid
+.sym 19367 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 19368 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1]
+.sym 19369 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0]
+.sym 19370 spi_if_ins.spi.r_tx_byte[0]
+.sym 19371 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1]
+.sym 19372 spi_if_ins.spi.SCKr[1]
+.sym 19373 spi_if_ins.spi.r_tx_byte[1]
+.sym 19374 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1]
+.sym 19375 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
+.sym 19377 spi_if_ins.r_tx_byte[7]
+.sym 19378 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
+.sym 19381 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[3]
+.sym 19385 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 19386 spi_if_ins.spi.r_tx_byte[5]
+.sym 19387 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
+.sym 19391 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
+.sym 19392 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
+.sym 19393 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 19394 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1[3]
+.sym 19397 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
+.sym 19398 spi_if_ins.spi.r_tx_byte[4]
+.sym 19399 spi_if_ins.spi.r_tx_byte[0]
+.sym 19400 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 19403 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 19404 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1]
+.sym 19405 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
+.sym 19409 spi_if_ins.spi.SCKr[1]
+.sym 19410 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
+.sym 19412 spi_if_ins.spi.SCKr[2]
+.sym 19415 i_ss$SB_IO_IN
+.sym 19416 spi_if_ins.r_tx_data_valid
+.sym 19421 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
+.sym 19422 spi_if_ins.spi.r_tx_byte[1]
+.sym 19423 spi_if_ins.spi.r_tx_byte[5]
+.sym 19424 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 19427 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1]
+.sym 19429 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
+.sym 19430 spi_if_ins.r_tx_byte[7]
+.sym 19433 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[2]
+.sym 19434 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[0]
+.sym 19435 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 19436 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0[1]
+.sym 19437 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 19438 r_counter_$glb_clk
+.sym 19451 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[0]
+.sym 19458 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 19465 $PACKER_VCC_NET
+.sym 19468 $PACKER_VCC_NET
+.sym 19474 $PACKER_VCC_NET
+.sym 19475 w_rx_09_fifo_data[7]
+.sym 19481 spi_if_ins.spi.r_tx_byte[6]
+.sym 19483 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 19485 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
+.sym 19494 spi_if_ins.r_tx_byte[0]
+.sym 19498 spi_if_ins.spi.r_tx_byte[3]
+.sym 19499 spi_if_ins.spi.r_tx_byte[7]
+.sym 19500 spi_if_ins.r_tx_byte[4]
+.sym 19501 spi_if_ins.r_tx_byte[1]
+.sym 19502 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 19505 spi_if_ins.spi.r_tx_byte[2]
+.sym 19506 spi_if_ins.r_tx_byte[7]
+.sym 19510 spi_if_ins.r_tx_byte[2]
+.sym 19512 spi_if_ins.r_tx_byte[3]
+.sym 19516 spi_if_ins.r_tx_byte[2]
+.sym 19523 spi_if_ins.r_tx_byte[3]
+.sym 19526 spi_if_ins.r_tx_byte[7]
+.sym 19532 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 19533 spi_if_ins.spi.r_tx_byte[6]
+.sym 19534 spi_if_ins.spi.r_tx_byte[2]
+.sym 19538 spi_if_ins.r_tx_byte[0]
+.sym 19544 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 19546 spi_if_ins.spi.r_tx_byte[3]
+.sym 19547 spi_if_ins.spi.r_tx_byte[7]
+.sym 19553 spi_if_ins.r_tx_byte[4]
+.sym 19557 spi_if_ins.r_tx_byte[1]
+.sym 19560 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 19561 r_counter_$glb_clk
+.sym 19562 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
+.sym 19575 spi_if_ins.r_tx_data_valid
+.sym 19587 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 19589 spi_if_ins.w_rx_data[2]
+.sym 19591 w_tx_data_io[4]
+.sym 19597 spi_if_ins.w_rx_data[4]
+.sym 19604 spi_if_ins.r_tx_byte[5]
+.sym 19622 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 19624 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
+.sym 19634 spi_if_ins.r_tx_byte[6]
+.sym 19640 spi_if_ins.r_tx_byte[6]
+.sym 19649 spi_if_ins.r_tx_byte[5]
+.sym 19683 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 19684 r_counter_$glb_clk
+.sym 19685 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
+.sym 19698 w_soft_reset
+.sym 19727 i_glob_clock$SB_IO_IN
+.sym 19729 r_tx_data_SB_DFFE_Q_E
+.sym 19734 w_tx_data_io[7]
+.sym 19747 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 19749 smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O[0]
+.sym 19751 w_tx_data_io[4]
+.sym 19756 spi_if_ins.o_cs_SB_LUT4_I3_O[1]
+.sym 19773 w_tx_data_io[4]
+.sym 19774 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 19784 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 19785 w_tx_data_io[7]
+.sym 19786 smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O[0]
+.sym 19806 r_tx_data_SB_DFFE_Q_E
+.sym 19807 i_glob_clock$SB_IO_IN
+.sym 19808 spi_if_ins.o_cs_SB_LUT4_I3_O[1]
+.sym 19821 i_glob_clock$SB_IO_IN
+.sym 19835 i_button_SB_LUT4_I3_O[0]
+.sym 19840 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E
+.sym 19866 w_rx_data[4]
+.sym 19867 w_rx_data[7]
+.sym 19877 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
+.sym 19883 w_rx_data[4]
+.sym 19913 w_rx_data[7]
+.sym 19929 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
+.sym 19930 r_counter_$glb_clk
+.sym 19963 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E
+.sym 19974 w_rx_data[4]
+.sym 19976 w_rx_data[7]
+.sym 19988 w_rx_data[5]
+.sym 19992 w_rx_data[3]
+.sym 19998 w_rx_data[1]
+.sym 20000 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E
+.sym 20004 w_rx_data[0]
+.sym 20013 w_rx_data[1]
+.sym 20025 w_rx_data[5]
+.sym 20032 w_rx_data[0]
+.sym 20038 w_rx_data[3]
+.sym 20043 w_rx_data[4]
+.sym 20048 w_rx_data[7]
+.sym 20052 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E
+.sym 20053 r_counter_$glb_clk
+.sym 20082 w_tx_data_io[4]
+.sym 20083 i_config[0]$SB_IO_IN
+.sym 20087 io_ctrl_ins.rf_pin_state[5]
+.sym 20098 i_config[2]$SB_IO_IN
+.sym 20099 io_ctrl_ins.pmod_dir_state[5]
+.sym 20102 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
+.sym 20103 io_ctrl_ins.pmod_dir_state[7]
+.sym 20105 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[0]
+.sym 20106 w_rx_data[5]
+.sym 20110 w_rx_data[7]
+.sym 20111 w_rx_data[3]
+.sym 20122 o_tr_vc1$SB_IO_OUT
+.sym 20123 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E
+.sym 20124 o_rx_h_tx_l$SB_IO_OUT
+.sym 20125 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 20132 w_rx_data[5]
+.sym 20136 i_config[2]$SB_IO_IN
+.sym 20138 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
+.sym 20147 o_rx_h_tx_l$SB_IO_OUT
+.sym 20148 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[0]
+.sym 20149 io_ctrl_ins.pmod_dir_state[7]
+.sym 20150 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 20153 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 20154 io_ctrl_ins.pmod_dir_state[5]
+.sym 20155 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[0]
+.sym 20156 o_tr_vc1$SB_IO_OUT
+.sym 20160 w_rx_data[3]
+.sym 20168 w_rx_data[7]
+.sym 20175 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E
+.sym 20176 r_counter_$glb_clk
+.sym 20194 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[2]
+.sym 20196 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[2]
+.sym 20198 i_button_SB_LUT4_I3_O[3]
+.sym 20200 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[3]
+.sym 20211 o_tr_vc1_b$SB_IO_OUT
+.sym 20220 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[2]
+.sym 20221 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[2]
+.sym 20223 io_ctrl_ins.pmod_dir_state[4]
+.sym 20224 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3]
+.sym 20227 i_config[1]$SB_IO_IN
+.sym 20228 i_button_SB_LUT4_I3_O[1]
+.sym 20229 o_tr_vc1_b$SB_IO_OUT
+.sym 20230 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 20231 i_config[3]$SB_IO_IN
+.sym 20232 o_tr_vc2$SB_IO_OUT
+.sym 20243 i_config[0]$SB_IO_IN
+.sym 20244 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[0]
+.sym 20245 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2]
+.sym 20246 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[0]
+.sym 20248 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S
+.sym 20249 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
+.sym 20250 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[3]
+.sym 20258 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
+.sym 20259 o_tr_vc2$SB_IO_OUT
+.sym 20260 i_config[0]$SB_IO_IN
+.sym 20261 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[0]
+.sym 20264 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[0]
+.sym 20265 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
+.sym 20266 i_button_SB_LUT4_I3_O[1]
+.sym 20267 i_config[1]$SB_IO_IN
+.sym 20270 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
+.sym 20272 i_config[3]$SB_IO_IN
+.sym 20282 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[2]
+.sym 20283 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[3]
+.sym 20284 o_tr_vc1_b$SB_IO_OUT
+.sym 20285 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[0]
+.sym 20294 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2]
+.sym 20295 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 20296 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3]
+.sym 20297 io_ctrl_ins.pmod_dir_state[4]
+.sym 20298 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[2]
+.sym 20299 r_counter_$glb_clk
+.sym 20300 io_ctrl_ins.o_data_out_SB_DFFESS_Q_S
+.sym 20313 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[0]
+.sym 20324 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 20325 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 20342 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
+.sym 20344 io_ctrl_ins.rf_pin_state[3]
+.sym 20345 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 20346 io_ctrl_ins.rf_pin_state[7]
+.sym 20348 io_ctrl_ins.rf_mode[0]
+.sym 20349 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[3]
+.sym 20350 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 20352 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 20353 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
+.sym 20359 io_ctrl_ins.rf_pin_state[5]
+.sym 20360 io_ctrl_ins.rf_pin_state[4]
+.sym 20364 io_ctrl_ins.rf_pin_state[6]
+.sym 20375 io_ctrl_ins.rf_mode[0]
+.sym 20376 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 20377 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
+.sym 20378 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[3]
+.sym 20381 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 20382 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
+.sym 20383 io_ctrl_ins.rf_pin_state[5]
+.sym 20387 io_ctrl_ins.rf_pin_state[4]
+.sym 20388 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 20389 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
+.sym 20399 io_ctrl_ins.rf_pin_state[6]
+.sym 20400 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 20401 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
+.sym 20405 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[3]
+.sym 20406 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
+.sym 20407 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 20408 io_ctrl_ins.rf_pin_state[3]
+.sym 20411 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
+.sym 20412 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 20413 io_ctrl_ins.rf_pin_state[7]
+.sym 20421 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
+.sym 20422 r_counter_$glb_clk
+.sym 20438 o_tr_vc2$SB_IO_OUT
+.sym 20440 o_tr_vc1$SB_IO_OUT
+.sym 20444 o_led0$SB_IO_OUT
+.sym 20576 o_led1$SB_IO_OUT
 .sym 20579 i_config[0]$SB_IO_IN
 .sym 20672 i_config[0]$SB_IO_IN
+.sym 20742 w_soft_reset
 .sym 20748 io_smi_data[5]$SB_IO_OUT
-.sym 20759 io_smi_data[5]$SB_IO_OUT
-.sym 20772 o_miso_$_TBUF__Y_E
-.sym 20775 i_ss$SB_IO_IN
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+.sym 28369 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
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+.sym 28373 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 28374 lvds_rx_24_inst.r_data[29]
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+.sym 28381 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
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+.sym 28408 rx_24_fifo.rd_addr[5]
+.sym 28409 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[5]
+.sym 28412 rx_24_fifo.rd_addr[6]
+.sym 28413 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[6]
+.sym 28416 rx_24_fifo.rd_addr[7]
+.sym 28417 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[7]
+.sym 28419 $PACKER_VCC_NET
+.sym 28421 $nextpnr_ICESTORM_LC_13$I3
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+.sym 28429 $nextpnr_ICESTORM_LC_14$I3
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+.sym 28440 rx_24_fifo.rd_addr[1]
+.sym 28441 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1]
+.sym 28448 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[2]
+.sym 28449 w_soft_reset
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+.sym 28493 rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
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+.sym 28529 w_rx_24_fifo_data[4]
+.sym 28536 w_soft_reset
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-.sym 30377 rx_24_fifo.wr_addr[8]
-.sym 30378 i_smi_a2_SB_LUT4_I1_O[0]
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-.sym 30381 i_smi_a2_SB_LUT4_I1_O[3]
-.sym 30382 rx_24_fifo.rd_addr[3]
-.sym 30383 rx_24_fifo.wr_addr[3]
-.sym 30384 rx_24_fifo.rd_addr[4]
-.sym 30385 rx_24_fifo.wr_addr[4]
-.sym 30386 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[1]
-.sym 30387 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0[1]
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+.sym 28946 w_soft_reset
+.sym 28947 i_smi_a2$SB_IO_IN
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+.sym 28962 rx_24_fifo.full_o_SB_LUT4_I3_I2[6]
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+.sym 28969 smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
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+.sym 28987 w_rx_24_fifo_pulled_data[24]
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+.sym 28995 w_rx_24_fifo_pulled_data[28]
+.sym 28996 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
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+.sym 28999 w_rx_24_fifo_pulled_data[29]
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+.sym 29004 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
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+.sym 29006 w_rx_24_fifo_pulled_data[19]
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+.sym 29008 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 29009 smi_ctrl_ins.int_cnt_24[3]
+.sym 29010 w_rx_24_fifo_pulled_data[22]
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+.sym 29012 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 29013 smi_ctrl_ins.int_cnt_24[3]
+.sym 29014 lvds_rx_09_inst.r_push
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+.sym 29065 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
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+.sym 29072 rx_24_fifo.wr_addr[3]
+.sym 29073 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[3]
+.sym 29076 rx_24_fifo.wr_addr[4]
+.sym 29077 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[4]
+.sym 29080 rx_24_fifo.wr_addr[5]
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+.sym 29084 rx_24_fifo.wr_addr[6]
+.sym 29085 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[6]
+.sym 29088 rx_24_fifo.wr_addr[7]
+.sym 29089 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[7]
+.sym 29092 rx_24_fifo.wr_addr[8]
+.sym 29093 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[8]
+.sym 29102 w_lvds_rx_09_d1
+.sym 29218 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
+.sym 29222 rx_09_fifo.rd_addr[6]
+.sym 29223 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[5]
+.sym 29224 rx_09_fifo.rd_addr[7]
+.sym 29225 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[6]
+.sym 29230 rx_09_fifo.full_o_SB_LUT4_I3_I2[1]
+.sym 29234 rx_09_fifo.full_o_SB_LUT4_I3_I2[7]
+.sym 29241 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 29249 io_smi_data[7]$SB_IO_OUT
+.sym 29251 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[1]
+.sym 29256 rx_09_fifo.wr_addr[2]
+.sym 29257 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[1]
+.sym 29260 rx_09_fifo.empty_o_SB_LUT4_I0_O[1]
+.sym 29261 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[2]
+.sym 29264 rx_09_fifo.wr_addr[4]
+.sym 29265 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[3]
+.sym 29268 rx_09_fifo.wr_addr[5]
+.sym 29269 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[4]
+.sym 29272 rx_09_fifo.wr_addr[6]
+.sym 29273 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[5]
+.sym 29276 rx_09_fifo.wr_addr[7]
+.sym 29277 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[6]
+.sym 29280 rx_09_fifo.wr_addr[8]
+.sym 29281 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[7]
+.sym 29285 $nextpnr_ICESTORM_LC_1$I3
+.sym 29286 rx_09_fifo.full_o_SB_LUT4_I3_I2[6]
+.sym 29290 rx_09_fifo.full_o_SB_LUT4_I3_I2[5]
+.sym 29294 rx_09_fifo.rd_addr[1]
+.sym 29295 rx_09_fifo.wr_addr[8]
+.sym 29296 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I0[8]
+.sym 29297 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
+.sym 29298 rx_09_fifo.full_o_SB_LUT4_I3_I2[4]
+.sym 29302 rx_09_fifo.full_o_SB_LUT4_I3_I2[2]
+.sym 29306 rx_09_fifo.full_o_SB_LUT4_I3_I2[8]
+.sym 29310 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[1]
+.sym 29311 rx_09_fifo.rd_addr[8]
+.sym 29312 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[7]
+.sym 29313 rx_09_fifo.rd_addr[1]
+.sym 29314 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
+.sym 29315 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[8]
+.sym 29316 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I2[2]
+.sym 29317 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[3]
+.sym 29318 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I2[0]
+.sym 29319 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[4]
+.sym 29320 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I2[2]
+.sym 29321 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I2[3]
+.sym 29322 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I2[2]
+.sym 29323 rx_09_fifo.wr_addr[4]
+.sym 29324 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I2[0]
+.sym 29325 rx_09_fifo.wr_addr[5]
+.sym 29326 rx_09_fifo.rd_addr[2]
+.sym 29327 rx_09_fifo.wr_addr[2]
+.sym 29328 rx_09_fifo.rd_addr[6]
+.sym 29329 rx_09_fifo.wr_addr[6]
+.sym 29332 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 29333 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1]
+.sym 29334 w_rx_09_fifo_empty
+.sym 29335 rx_09_fifo.empty_o_SB_LUT4_I0_I1[1]
+.sym 29336 rx_09_fifo.empty_o_SB_LUT4_I0_I1[2]
+.sym 29337 rx_09_fifo.empty_o_SB_LUT4_I0_I1[3]
+.sym 29338 lvds_rx_09_inst.r_data[17]
+.sym 29342 rx_09_fifo.rd_addr[7]
+.sym 29343 rx_09_fifo.wr_addr[7]
+.sym 29344 rx_09_fifo.rd_addr[8]
+.sym 29345 rx_09_fifo.wr_addr[8]
+.sym 29346 lvds_rx_09_inst.r_data[3]
+.sym 29350 lvds_rx_09_inst.r_data[15]
+.sym 29354 lvds_rx_09_inst.r_data[1]
+.sym 29359 w_rx_09_fifo_push
+.sym 29360 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2[1]
+.sym 29361 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2[2]
+.sym 29362 lvds_rx_09_inst.r_data[7]
+.sym 29366 rx_09_fifo.rd_addr[2]
+.sym 29367 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[1]
+.sym 29368 rx_09_fifo.empty_o_SB_LUT4_I0_O[0]
+.sym 29369 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1[2]
+.sym 29370 lvds_rx_09_inst.r_data[9]
+.sym 29374 lvds_rx_09_inst.r_data[5]
+.sym 29384 i_smi_a3$SB_IO_IN
+.sym 29385 w_smi_data_output[2]
+.sym 29390 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[0]
+.sym 29391 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[1]
+.sym 29392 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[2]
+.sym 29393 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0[3]
+.sym 29408 w_soft_reset
+.sym 29409 w_rx_09_fifo_push
+.sym 29413 smi_ctrl_ins.int_cnt_09[3]
+.sym 29414 rx_24_fifo.rd_addr[3]
+.sym 29415 rx_24_fifo.wr_addr[3]
+.sym 29416 rx_24_fifo.rd_addr[6]
+.sym 29417 rx_24_fifo.wr_addr[6]
+.sym 29420 i_smi_a2_SB_LUT4_I1_1_O[3]
+.sym 29421 w_soft_reset
+.sym 29424 smi_ctrl_ins.int_cnt_09[4]
+.sym 29425 smi_ctrl_ins.int_cnt_09[3]
+.sym 29434 w_rx_09_fifo_pulled_data[15]
+.sym 29435 w_rx_09_fifo_pulled_data[31]
+.sym 29436 smi_ctrl_ins.int_cnt_09[4]
+.sym 29437 smi_ctrl_ins.int_cnt_09[3]
+.sym 29443 smi_ctrl_ins.r_fifo_24_pull_1
+.sym 29444 w_rx_24_fifo_empty
+.sym 29445 smi_ctrl_ins.r_fifo_24_pull
+.sym 29446 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0]
+.sym 29447 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
+.sym 29448 w_rx_24_fifo_empty
+.sym 29449 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3]
+.sym 29451 i_smi_a2$SB_IO_IN
+.sym 29452 i_smi_a3$SB_IO_IN
+.sym 29453 i_smi_a1$SB_IO_IN
+.sym 29454 rx_24_fifo.wr_addr[3]
+.sym 29455 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[3]
+.sym 29456 rx_24_fifo.wr_addr[4]
+.sym 29457 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1[4]
+.sym 29462 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[0]
+.sym 29463 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[1]
+.sym 29464 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[2]
+.sym 29465 smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O[3]
+.sym 29466 smi_ctrl_ins.r_fifo_24_pull
+.sym 29470 smi_ctrl_ins.w_fifo_09_pull_trigger
+.sym 29474 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 29475 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1]
+.sym 29476 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1]
+.sym 29477 rx_24_fifo.rd_addr[1]
+.sym 29478 i_smi_a1$SB_IO_IN
+.sym 29479 i_smi_a3$SB_IO_IN
+.sym 29480 i_smi_a2$SB_IO_IN
+.sym 29481 w_soft_reset
+.sym 29482 rx_24_fifo.rd_addr[2]
+.sym 29483 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[1]
+.sym 29484 rx_24_fifo.rd_addr[4]
+.sym 29485 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[3]
+.sym 29486 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
+.sym 29487 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[1]
+.sym 29488 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
+.sym 29489 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0[3]
+.sym 29490 rx_24_fifo.rd_addr[3]
+.sym 29491 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[2]
+.sym 29492 rx_24_fifo.rd_addr[5]
+.sym 29493 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[4]
+.sym 29496 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 29497 smi_ctrl_ins.int_cnt_24[3]
+.sym 29498 rx_24_fifo.rd_addr[7]
+.sym 29499 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[6]
+.sym 29500 rx_24_fifo.rd_addr[8]
+.sym 29501 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[7]
+.sym 29505 smi_ctrl_ins.int_cnt_24[3]
+.sym 29507 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1]
+.sym 29512 rx_24_fifo.wr_addr[2]
+.sym 29513 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1]
+.sym 29516 rx_24_fifo.wr_addr[3]
+.sym 29517 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[2]
+.sym 29520 rx_24_fifo.wr_addr[4]
+.sym 29521 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[3]
+.sym 29524 rx_24_fifo.wr_addr[5]
+.sym 29525 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[4]
+.sym 29528 rx_24_fifo.wr_addr[6]
+.sym 29529 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[5]
+.sym 29532 rx_24_fifo.wr_addr[7]
+.sym 29533 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[6]
+.sym 29536 rx_24_fifo.wr_addr[8]
+.sym 29537 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[7]
+.sym 29541 $nextpnr_ICESTORM_LC_8$I3
+.sym 29542 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
+.sym 29543 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 29544 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 29545 rx_24_fifo.full_o_SB_LUT4_I3_O[3]
+.sym 29550 rx_24_fifo.rd_addr[4]
+.sym 29551 rx_24_fifo.wr_addr[4]
+.sym 29552 rx_24_fifo.rd_addr[5]
+.sym 29553 rx_24_fifo.wr_addr[5]
+.sym 29554 w_rx_24_fifo_push
+.sym 29555 rx_24_fifo.rd_addr[4]
+.sym 29556 rx_24_fifo.full_o_SB_LUT4_I3_I2[4]
+.sym 29557 w_rx_24_fifo_full
+.sym 29558 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[0]
+.sym 29559 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[1]
+.sym 29560 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[2]
+.sym 29561 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0[3]
+.sym 29562 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[8]
+.sym 29563 rx_24_fifo.rd_addr[6]
+.sym 29564 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2[5]
+.sym 29565 w_rx_24_fifo_push
+.sym 29566 rx_24_fifo.rd_addr[1]
+.sym 29567 rx_24_fifo.full_o_SB_LUT4_I3_I2[1]
+.sym 29568 rx_24_fifo.rd_addr[2]
+.sym 29569 rx_24_fifo.full_o_SB_LUT4_I3_I2[2]
+.sym 29570 rx_24_fifo.full_o_SB_LUT4_I3_I2[7]
+.sym 29574 rx_24_fifo.rd_addr[8]
+.sym 29575 rx_24_fifo.wr_addr[8]
+.sym 29576 rx_24_fifo.rd_addr[2]
+.sym 29577 rx_24_fifo.wr_addr[2]
+.sym 29578 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 29579 rx_24_fifo.rd_addr[8]
+.sym 29580 rx_24_fifo.full_o_SB_LUT4_I3_I2[8]
+.sym 29581 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1]
+.sym 29586 rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 29587 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1[1]
+.sym 29588 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0[1]
+.sym 29589 rx_24_fifo.rd_addr[1]
+.sym 29590 rx_24_fifo.full_o_SB_LUT4_I3_I2[8]
+.sym 29594 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[0]
+.sym 29595 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[1]
+.sym 29596 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[2]
+.sym 29597 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0[3]
+.sym 29598 rx_24_fifo.wr_addr[8]
+.sym 29599 rx_24_fifo.rd_addr[8]
+.sym 29600 rx_24_fifo.rd_addr[7]
+.sym 29601 rx_24_fifo.wr_addr[7]
+.sym 29659 w_rx_09_fifo_full
+.sym 29660 lvds_rx_09_inst.o_debug_state[0]
+.sym 29661 lvds_rx_09_inst.o_debug_state[1]
+.sym 29731 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1]
+.sym 29736 rx_09_fifo.rd_addr[1]
+.sym 29740 rx_09_fifo.rd_addr[2]
+.sym 29741 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[2]
+.sym 29744 rx_09_fifo.empty_o_SB_LUT4_I0_O[0]
+.sym 29745 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3]
+.sym 29748 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I2[2]
+.sym 29749 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[4]
+.sym 29752 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I2[0]
+.sym 29753 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[5]
+.sym 29756 rx_09_fifo.rd_addr[6]
+.sym 29757 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[6]
+.sym 29760 rx_09_fifo.rd_addr[7]
+.sym 29761 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[7]
+.sym 29764 rx_09_fifo.rd_addr[8]
+.sym 29765 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[8]
+.sym 29769 $nextpnr_ICESTORM_LC_11$I3
+.sym 29770 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I0[7]
+.sym 29771 rx_09_fifo.wr_addr[7]
+.sym 29772 rx_09_fifo.wr_addr[6]
+.sym 29773 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I0[6]
+.sym 29774 spi_if_ins.spi.r_rx_byte[6]
+.sym 29778 spi_if_ins.spi.r_rx_byte[3]
+.sym 29782 rx_09_fifo.wr_addr[7]
+.sym 29783 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I0[7]
+.sym 29784 rx_09_fifo.wr_addr[5]
+.sym 29785 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I0[5]
+.sym 29786 rx_09_fifo.empty_o_SB_LUT4_I0_O[1]
+.sym 29787 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I0[3]
+.sym 29788 rx_09_fifo.wr_addr[4]
+.sym 29789 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I0[4]
+.sym 29790 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[9]
+.sym 29791 rx_09_fifo.wr_addr[2]
+.sym 29792 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I0_O[2]
+.sym 29793 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I0_O[3]
+.sym 29795 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1]
+.sym 29800 rx_09_fifo.rd_addr[1]
+.sym 29804 rx_09_fifo.rd_addr[2]
+.sym 29805 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
+.sym 29808 rx_09_fifo.empty_o_SB_LUT4_I0_O[0]
+.sym 29809 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
+.sym 29812 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I2[2]
+.sym 29813 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[4]
+.sym 29816 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I2[0]
+.sym 29817 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[5]
+.sym 29820 rx_09_fifo.rd_addr[6]
+.sym 29821 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[6]
+.sym 29824 rx_09_fifo.rd_addr[7]
+.sym 29825 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[7]
+.sym 29828 rx_09_fifo.rd_addr[8]
+.sym 29829 rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3[8]
+.sym 29832 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1]
+.sym 29833 w_soft_reset
+.sym 29834 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
+.sym 29835 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
+.sym 29836 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[1]
+.sym 29837 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3]
+.sym 29841 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1]
+.sym 29842 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I2[0]
+.sym 29843 rx_09_fifo.full_o_SB_LUT4_I3_I2[5]
+.sym 29844 rx_09_fifo.rd_addr[6]
+.sym 29845 rx_09_fifo.full_o_SB_LUT4_I3_I2[6]
+.sym 29846 rx_09_fifo.rd_addr[2]
+.sym 29847 rx_09_fifo.full_o_SB_LUT4_I3_I2[2]
+.sym 29848 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I2[2]
+.sym 29849 rx_09_fifo.full_o_SB_LUT4_I3_I2[4]
+.sym 29852 rx_09_fifo.rd_addr[1]
+.sym 29853 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1]
+.sym 29856 rx_09_fifo.rd_addr[7]
+.sym 29857 rx_09_fifo.full_o_SB_LUT4_I3_I2[7]
+.sym 29860 i_smi_a3$SB_IO_IN
+.sym 29861 w_smi_data_output[3]
+.sym 29862 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
+.sym 29863 rx_09_fifo.empty_o_SB_LUT4_I0_O[0]
+.sym 29864 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[2]
+.sym 29865 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[3]
+.sym 29866 smi_ctrl_ins.w_fifo_24_pull_trigger
+.sym 29871 smi_ctrl_ins.r_fifo_09_pull_1
+.sym 29872 w_rx_09_fifo_empty
+.sym 29873 smi_ctrl_ins.r_fifo_09_pull
+.sym 29874 smi_ctrl_ins.r_fifo_09_pull
+.sym 29878 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[0]
+.sym 29879 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
+.sym 29880 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
+.sym 29881 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[3]
+.sym 29883 rx_09_fifo.empty_o_SB_LUT4_I0_O[0]
+.sym 29884 rx_09_fifo.empty_o_SB_LUT4_I0_O[1]
+.sym 29885 rx_09_fifo.empty_o_SB_LUT4_I0_O[2]
+.sym 29886 rx_09_fifo.full_o_SB_LUT4_I3_O[0]
+.sym 29887 rx_09_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 29888 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
+.sym 29889 rx_09_fifo.full_o_SB_LUT4_I3_O[3]
+.sym 29897 w_soft_reset
+.sym 29899 smi_ctrl_ins.int_cnt_09[4]
+.sym 29900 smi_ctrl_ins.int_cnt_09[3]
+.sym 29901 w_rx_09_fifo_empty
+.sym 29904 w_rx_24_fifo_empty
+.sym 29905 w_rx_09_fifo_empty
+.sym 29908 w_soft_reset
+.sym 29909 w_rx_09_fifo_push
+.sym 29911 i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3[2]
+.sym 29912 smi_ctrl_ins.int_cnt_24[3]
+.sym 29913 w_rx_24_fifo_empty
+.sym 29914 w_rx_09_fifo_push
+.sym 29915 rx_09_fifo.rd_addr[8]
+.sym 29916 rx_09_fifo.full_o_SB_LUT4_I3_I2[8]
+.sym 29917 w_rx_09_fifo_full
+.sym 29921 smi_ctrl_ins.int_cnt_09[4]
+.sym 29924 spi_if_ins.state_if[0]
+.sym 29925 spi_if_ins.state_if[1]
+.sym 29928 spi_if_ins.state_if_SB_DFFE_Q_D[0]
+.sym 29929 spi_if_ins.state_if[2]
+.sym 29935 spi_if_ins.state_if_SB_DFFE_Q_D[0]
+.sym 29936 spi_if_ins.state_if_SB_DFFE_Q_D[1]
+.sym 29937 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 29941 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 29954 w_tx_data_sys[0]
+.sym 29955 spi_if_ins.o_cs_SB_LUT4_I3_O[1]
+.sym 29956 smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O[0]
+.sym 29957 spi_if_ins.o_cs_SB_LUT4_I3_O[3]
+.sym 29962 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 29963 spi_if_ins.state_if[2]
+.sym 29964 spi_if_ins.state_if[0]
+.sym 29965 spi_if_ins.state_if[1]
+.sym 29979 spi_if_ins.state_if_SB_DFFE_Q_D[0]
+.sym 29980 spi_if_ins.state_if[2]
+.sym 29981 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 29986 w_tx_data_smi[0]
+.sym 29987 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 29988 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 29989 w_tx_data_io[0]
+.sym 29992 spi_if_ins.w_rx_data[5]
+.sym 29993 spi_if_ins.w_rx_data[6]
+.sym 29996 spi_if_ins.w_rx_data[5]
+.sym 29997 spi_if_ins.w_rx_data[6]
+.sym 30000 spi_if_ins.w_rx_data[5]
+.sym 30001 spi_if_ins.w_rx_data[6]
+.sym 30002 w_cs[2]
+.sym 30003 w_cs[1]
+.sym 30004 w_cs[3]
+.sym 30005 w_cs[0]
+.sym 30006 w_cs[0]
+.sym 30007 w_cs[1]
+.sym 30008 w_cs[3]
+.sym 30009 w_cs[2]
+.sym 30012 spi_if_ins.w_rx_data[6]
+.sym 30013 spi_if_ins.w_rx_data[5]
+.sym 30018 w_rx_09_fifo_empty
+.sym 30022 w_rx_09_fifo_full
+.sym 30030 w_rx_24_fifo_empty
+.sym 30034 w_rx_24_fifo_full
+.sym 30042 w_tx_data_smi[2]
+.sym 30043 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 30044 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 30045 w_tx_data_io[2]
+.sym 30050 w_soft_reset
+.sym 30051 w_ioc[1]
+.sym 30052 w_cs[2]
+.sym 30053 w_fetch
+.sym 30058 spi_if_ins.state_if_SB_DFFE_Q_D[0]
+.sym 30071 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 30072 w_cs[0]
+.sym 30073 w_fetch
+.sym 30094 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 30104 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 30105 smi_ctrl_ins.i_cs_SB_LUT4_I2_O[1]
+.sym 30116 io_ctrl_ins.led1_state_SB_DFFESR_Q_E_SB_LUT4_O_I2[0]
+.sym 30117 w_soft_reset
+.sym 30118 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I2[0]
+.sym 30119 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 30120 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I2[2]
+.sym 30121 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I2[3]
+.sym 30138 w_fetch
+.sym 30139 w_cs[1]
+.sym 30140 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
+.sym 30141 w_load
+.sym 30154 w_rx_data[1]
+.sym 30174 w_rx_data[0]
+.sym 30258 lvds_rx_09_inst.r_data[14]
+.sym 30276 i_smi_a3$SB_IO_IN
+.sym 30277 w_smi_data_output[5]
+.sym 30290 spi_if_ins.spi.r_temp_rx_byte[5]
+.sym 30294 i_mosi$SB_IO_IN
+.sym 30298 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 30310 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 30314 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[0]
+.sym 30315 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1]
+.sym 30316 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[2]
+.sym 30317 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[3]
+.sym 30326 spi_if_ins.spi.r_temp_rx_byte[5]
+.sym 30339 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 30344 lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1[1]
+.sym 30345 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 30348 rx_09_fifo.wr_addr[2]
+.sym 30349 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[2]
+.sym 30352 rx_09_fifo.empty_o_SB_LUT4_I0_O[1]
+.sym 30353 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[3]
+.sym 30356 rx_09_fifo.wr_addr[4]
+.sym 30357 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[4]
+.sym 30360 rx_09_fifo.wr_addr[5]
+.sym 30361 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[5]
+.sym 30364 rx_09_fifo.wr_addr[6]
+.sym 30365 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[6]
+.sym 30368 rx_09_fifo.wr_addr[7]
+.sym 30369 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[7]
+.sym 30372 rx_09_fifo.wr_addr[8]
+.sym 30373 rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3[8]
+.sym 30378 spi_if_ins.state_if_SB_DFFE_Q_D[1]
+.sym 30386 w_rx_09_fifo_pulled_data[14]
+.sym 30387 w_rx_09_fifo_pulled_data[30]
+.sym 30388 smi_ctrl_ins.int_cnt_09[4]
+.sym 30389 smi_ctrl_ins.int_cnt_09[3]
+.sym 30392 w_soft_reset
+.sym 30393 smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O[1]
+.sym 30394 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2[0]
+.sym 30395 rx_09_fifo.empty_o_SB_LUT4_I0_O[0]
+.sym 30396 rx_09_fifo.rd_addr[1]
+.sym 30397 rx_09_fifo.full_o_SB_LUT4_I3_I2[1]
+.sym 30400 rx_09_fifo.rd_addr[1]
+.sym 30401 rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1]
+.sym 30406 spi_if_ins.spi.SCKr[1]
+.sym 30414 w_rx_09_fifo_pulled_data[12]
+.sym 30415 w_rx_09_fifo_pulled_data[28]
+.sym 30416 smi_ctrl_ins.int_cnt_09[4]
+.sym 30417 smi_ctrl_ins.int_cnt_09[3]
+.sym 30430 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 30435 spi_if_ins.state_if[2]
+.sym 30436 spi_if_ins.state_if[1]
+.sym 30437 spi_if_ins.state_if[0]
+.sym 30439 spi_if_ins.state_if[2]
+.sym 30440 spi_if_ins.state_if[0]
+.sym 30441 spi_if_ins.state_if[1]
+.sym 30446 spi_if_ins.state_if_SB_DFFESR_Q_D[0]
+.sym 30447 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
+.sym 30448 spi_if_ins.state_if_SB_DFFESR_Q_D[2]
+.sym 30449 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 30450 spi_if_ins.state_if_SB_DFFESR_Q_D[0]
+.sym 30454 spi_if_ins.state_if[2]
+.sym 30455 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
+.sym 30456 spi_if_ins.state_if[0]
+.sym 30457 spi_if_ins.state_if[1]
+.sym 30478 r_tx_data[6]
+.sym 30482 r_tx_data[0]
+.sym 30498 w_tx_data_smi[1]
+.sym 30499 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 30500 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 30501 w_tx_data_io[1]
+.sym 30504 smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O[0]
+.sym 30505 smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O[1]
+.sym 30510 w_cs[0]
+.sym 30511 w_cs[2]
+.sym 30512 w_cs[1]
+.sym 30513 w_cs[3]
+.sym 30514 w_tx_data_smi[3]
+.sym 30515 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 30516 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 30517 w_tx_data_io[3]
+.sym 30519 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 30520 w_tx_data_io[5]
+.sym 30521 smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O[0]
+.sym 30524 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[0]
+.sym 30525 r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2[1]
+.sym 30526 w_cs[0]
+.sym 30527 w_cs[2]
+.sym 30528 w_cs[1]
+.sym 30529 w_cs[3]
+.sym 30530 spi_if_ins.w_rx_data[0]
+.sym 30534 w_cs[0]
+.sym 30535 w_cs[2]
+.sym 30536 w_cs[3]
+.sym 30537 w_cs[1]
+.sym 30538 spi_if_ins.w_rx_data[2]
+.sym 30542 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
+.sym 30546 spi_if_ins.w_rx_data[1]
+.sym 30554 spi_if_ins.w_rx_data[3]
+.sym 30558 spi_if_ins.w_rx_data[4]
+.sym 30562 w_fetch
+.sym 30563 i_button_SB_LUT4_I3_O[1]
+.sym 30564 w_load
+.sym 30565 w_cs[0]
+.sym 30571 w_ioc[2]
+.sym 30572 w_ioc[4]
+.sym 30573 w_ioc[3]
+.sym 30575 w_soft_reset
+.sym 30576 w_cs[1]
+.sym 30577 w_fetch
+.sym 30581 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[2]
+.sym 30582 w_ioc[1]
+.sym 30583 w_ioc[4]
+.sym 30584 w_ioc[3]
+.sym 30585 w_ioc[2]
+.sym 30591 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3[0]
+.sym 30592 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 30593 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2]
+.sym 30595 w_ioc[1]
+.sym 30596 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 30597 w_ioc[0]
+.sym 30600 i_button_SB_LUT4_I3_O[1]
+.sym 30601 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
+.sym 30602 w_rx_data[1]
+.sym 30607 w_ioc[0]
+.sym 30608 w_ioc[1]
+.sym 30609 io_ctrl_ins.o_data_out_SB_DFFESS_Q_E[2]
+.sym 30610 w_soft_reset
+.sym 30611 w_fetch
+.sym 30612 w_cs[1]
+.sym 30613 w_load
+.sym 30614 i_button_SB_LUT4_I3_O[1]
+.sym 30615 io_ctrl_ins.o_pmod[1]
+.sym 30616 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[2]
+.sym 30617 io_ctrl_ins.debug_mode[1]
+.sym 30619 w_ioc[0]
+.sym 30620 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R[1]
+.sym 30621 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3[0]
+.sym 30622 w_rx_data[2]
+.sym 30626 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[2]
+.sym 30627 w_fetch
+.sym 30628 w_cs[1]
+.sym 30629 w_load
+.sym 30632 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[2]
+.sym 30633 io_ctrl_ins.rf_mode[0]
+.sym 30637 io_ctrl_ins.rf_pin_state_SB_DFFE_Q_E
+.sym 30638 w_rx_data[2]
 .sym 30642 w_rx_data[1]
-.sym 30647 w_ioc[1]
-.sym 30648 w_ioc[0]
-.sym 30649 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
-.sym 30655 w_ioc[1]
-.sym 30656 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1[1]
-.sym 30657 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1]
-.sym 30658 io_ctrl_ins.o_pmod[1]
-.sym 30659 o_shdn_rx_lna$SB_IO_OUT
-.sym 30660 w_ioc[0]
-.sym 30661 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 30662 io_ctrl_ins.o_pmod[0]
-.sym 30663 io_ctrl_ins.mixer_en_state
-.sym 30664 w_ioc[0]
-.sym 30665 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 30666 o_led1$SB_IO_OUT
-.sym 30667 i_button_SB_LUT4_I0_I1[0]
-.sym 30668 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[2]
-.sym 30669 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[3]
-.sym 30670 io_ctrl_ins.pmod_dir_state[3]
-.sym 30671 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 30672 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2]
-.sym 30673 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
-.sym 30674 io_ctrl_ins.led0_state_SB_LUT4_I3_O[0]
-.sym 30675 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 30676 io_ctrl_ins.led0_state_SB_LUT4_I3_O[2]
-.sym 30677 io_ctrl_ins.led0_state_SB_LUT4_I3_O[3]
-.sym 30678 io_ctrl_ins.pmod_dir_state[4]
-.sym 30679 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 30680 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2]
-.sym 30681 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3]
-.sym 30732 w_soft_reset
-.sym 30733 lvds_rx_24_inst.o_debug_state[0]
-.sym 30768 w_soft_reset
-.sym 30769 i_smi_soe_se$SB_IO_IN
-.sym 30786 smi_ctrl_ins.r_fifo_24_pull
-.sym 30791 smi_ctrl_ins.r_fifo_24_pull_1
-.sym 30792 w_rx_24_fifo_empty
-.sym 30793 smi_ctrl_ins.r_fifo_24_pull
-.sym 30798 smi_ctrl_ins.w_fifo_09_pull_trigger
-.sym 30806 smi_ctrl_ins.w_fifo_24_pull_trigger
-.sym 30819 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
-.sym 30824 rx_24_fifo.empty_o_SB_LUT4_I2_I3[1]
-.sym 30825 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[1]
-.sym 30828 rx_24_fifo.wr_addr[3]
-.sym 30829 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[2]
-.sym 30832 rx_24_fifo.wr_addr[4]
-.sym 30833 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[3]
-.sym 30836 rx_24_fifo.wr_addr[5]
-.sym 30837 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[4]
-.sym 30840 rx_24_fifo.wr_addr[6]
-.sym 30841 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[5]
-.sym 30844 rx_24_fifo.wr_addr[7]
-.sym 30845 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[6]
-.sym 30848 rx_24_fifo.wr_addr[8]
-.sym 30849 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[7]
-.sym 30853 $nextpnr_ICESTORM_LC_2$I3
-.sym 30854 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[0]
-.sym 30855 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[1]
-.sym 30856 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[2]
-.sym 30857 rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0[3]
-.sym 30858 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0[8]
-.sym 30859 rx_24_fifo.rd_addr[8]
-.sym 30860 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[7]
-.sym 30861 w_rx_24_fifo_push
-.sym 30862 rx_24_fifo.rd_addr[3]
-.sym 30863 lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2[2]
-.sym 30864 rx_24_fifo.empty_o_SB_LUT4_I2_I3[0]
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-.sym 31885 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
-.sym 31886 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
-.sym 31887 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[1]
-.sym 31888 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
-.sym 31889 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
-.sym 31890 spi_if_ins.spi.r_tx_byte[2]
-.sym 31891 spi_if_ins.spi.r_tx_byte[6]
-.sym 31892 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
-.sym 31893 spi_if_ins.spi.r_tx_bit_count[2]
-.sym 31894 spi_if_ins.r_tx_byte[7]
-.sym 31898 spi_if_ins.r_tx_byte[1]
-.sym 31902 spi_if_ins.r_tx_byte[3]
-.sym 31906 spi_if_ins.r_tx_byte[6]
-.sym 31914 spi_if_ins.r_tx_byte[5]
-.sym 31922 spi_if_ins.r_tx_byte[0]
-.sym 31930 spi_if_ins.r_tx_byte[2]
-.sym 31934 spi_if_ins.r_tx_byte[4]
-.sym 31938 spi_if_ins.spi.r_temp_rx_byte[4]
-.sym 31942 spi_if_ins.spi.r_temp_rx_byte[5]
-.sym 31946 i_mosi$SB_IO_IN
-.sym 31950 spi_if_ins.spi.r_temp_rx_byte[3]
-.sym 31954 spi_if_ins.spi.r_temp_rx_byte[0]
-.sym 31958 spi_if_ins.spi.r_temp_rx_byte[6]
-.sym 31962 spi_if_ins.spi.r_temp_rx_byte[2]
-.sym 31966 spi_if_ins.spi.r_temp_rx_byte[1]
-.sym 31974 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
-.sym 32002 spi_if_ins.spi.r_rx_byte[5]
-.sym 32006 spi_if_ins.spi.r_rx_byte[1]
-.sym 32010 spi_if_ins.spi.r_rx_byte[4]
-.sym 32014 spi_if_ins.spi.r_rx_byte[0]
-.sym 32022 spi_if_ins.spi.r_rx_byte[6]
-.sym 32026 spi_if_ins.spi.r_rx_byte[7]
-.sym 32030 spi_if_ins.spi.r_rx_byte[3]
-.sym 32042 spi_if_ins.spi.r_rx_byte[2]
-.sym 32074 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 32106 w_rx_data[7]
-.sym 32113 io_ctrl_ins.led1_state_SB_DFFESR_Q_E
-.sym 32126 w_rx_data[3]
-.sym 32134 w_rx_data[0]
-.sym 32138 w_rx_data[1]
-.sym 32146 io_ctrl_ins.o_pmod[7]
-.sym 32147 o_rx_h_tx_l$SB_IO_OUT
-.sym 32148 w_ioc[0]
-.sym 32149 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 32152 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1[0]
-.sym 32153 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
-.sym 32155 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
-.sym 32156 i_button_SB_LUT4_I0_I1[0]
-.sym 32157 w_soft_reset
-.sym 32170 w_rx_data[0]
-.sym 32178 w_rx_data[3]
-.sym 32183 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
-.sym 32184 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 32185 w_ioc[0]
-.sym 32190 w_rx_data[7]
-.sym 32203 io_ctrl_ins.rf_pin_state[7]
-.sym 32204 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 32205 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 32206 io_ctrl_ins.rf_pin_state[0]
-.sym 32207 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 32208 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
-.sym 32209 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 32210 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
-.sym 32211 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 32212 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
-.sym 32213 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 32214 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0]
-.sym 32215 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 32216 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
-.sym 32217 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 32218 io_ctrl_ins.o_pmod[3]
-.sym 32219 o_tr_vc2$SB_IO_OUT
-.sym 32220 w_ioc[0]
-.sym 32221 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 32222 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 32223 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O[0]
-.sym 32224 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 32225 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
-.sym 32290 spi_if_ins.spi.SCKr[0]
-.sym 32306 i_sck$SB_IO_IN
-.sym 32323 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 32328 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 32332 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 32333 spi_if_ins.spi.r_rx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
-.sym 32335 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 32336 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 32337 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 32339 i_ss$SB_IO_IN
-.sym 32340 spi_if_ins.spi.SCKr[2]
-.sym 32341 spi_if_ins.spi.SCKr[1]
-.sym 32343 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 32344 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 32345 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 32348 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 32349 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 32353 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 32362 spi_if_ins.spi.SCKr[1]
-.sym 32429 spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_E
-.sym 32433 r_counter
-.sym 32436 i_ss_SB_LUT4_I1_O[0]
-.sym 32437 i_ss_SB_LUT4_I1_O[1]
-.sym 32454 spi_if_ins.spi.r_temp_rx_byte[5]
-.sym 32458 spi_if_ins.spi.r_temp_rx_byte[2]
-.sym 32462 spi_if_ins.spi.r_temp_rx_byte[3]
-.sym 32466 spi_if_ins.spi.r_temp_rx_byte[1]
-.sym 32470 i_mosi$SB_IO_IN
-.sym 32474 spi_if_ins.spi.r_temp_rx_byte[4]
-.sym 32478 spi_if_ins.spi.r_temp_rx_byte[0]
-.sym 32533 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
-.sym 32558 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 32633 w_rx_data[5]
-.sym 32646 w_rx_data[4]
-.sym 32650 w_rx_data[5]
-.sym 32662 w_rx_data[6]
-.sym 32686 w_rx_data[6]
-.sym 32690 w_rx_data[5]
-.sym 32694 w_rx_data[4]
-.sym 32707 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 32708 io_ctrl_ins.rf_pin_state[4]
-.sym 32709 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 32715 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 32716 io_ctrl_ins.rf_pin_state[6]
-.sym 32717 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 32723 io_ctrl_ins.rf_pin_state[5]
-.sym 32724 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 32725 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 32726 io_ctrl_ins.o_pmod[5]
-.sym 32727 o_tr_vc1$SB_IO_OUT
-.sym 32728 w_ioc[0]
-.sym 32729 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 32730 io_ctrl_ins.o_pmod[4]
-.sym 32731 o_tr_vc1_b$SB_IO_OUT
-.sym 32732 w_ioc[0]
-.sym 32733 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 32734 io_ctrl_ins.o_pmod[6]
-.sym 32735 o_rx_h_tx_l_b$SB_IO_OUT
-.sym 32736 w_ioc[0]
-.sym 32737 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
+.sym 31705 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
+.sym 31707 io_ctrl_ins.rf_pin_state[7]
+.sym 31708 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
+.sym 31709 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 31942 i_sck$SB_IO_IN
+.sym 31950 spi_if_ins.spi.SCKr[0]
+.sym 31986 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
+.sym 32018 $PACKER_GND_NET
+.sym 32025 sys_ctrl_ins.reset_cmd
+.sym 32034 $PACKER_VCC_NET
+.sym 32049 w_cs[0]
+.sym 32098 w_rx_data[5]
+.sym 32126 w_rx_data[6]
+.sym 32134 io_ctrl_ins.o_pmod[6]
+.sym 32135 i_button_SB_LUT4_I3_O[1]
+.sym 32136 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[2]
+.sym 32137 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[3]
+.sym 32138 i_button_SB_LUT4_I3_O[0]
+.sym 32139 i_button_SB_LUT4_I3_O[1]
+.sym 32140 i_button_SB_LUT4_I3_O[2]
+.sym 32141 i_button_SB_LUT4_I3_O[3]
+.sym 32146 io_ctrl_ins.o_pmod[5]
+.sym 32147 i_button_SB_LUT4_I3_O[1]
+.sym 32148 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[2]
+.sym 32149 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[3]
+.sym 32162 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
+.sym 32163 io_ctrl_ins.pmod_dir_state[6]
+.sym 32164 io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[0]
+.sym 32165 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 32186 w_rx_data[6]
+.sym 32560 w_soft_reset
+.sym 32561 lvds_rx_24_inst.o_debug_state[0]
+.sym 32577 r_counter
+.sym 32629 $PACKER_GND_NET
diff --git a/firmware/top.bin b/firmware/top.bin
index 9432f0c..47fdcff 100644
Binary files a/firmware/top.bin and b/firmware/top.bin differ
diff --git a/firmware/top.json b/firmware/top.json
index 6e4baa9..6d3b863 100644
--- a/firmware/top.json
+++ b/firmware/top.json
@@ -64,7 +64,7 @@
         }
       },
       "cells": {
-        "$specify$268": {
+        "$specify$267": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -95,7 +95,7 @@
             "SRC": [ 6 ]
           }
         },
-        "$specify$269": {
+        "$specify$268": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -126,7 +126,7 @@
             "SRC": [ 2 ]
           }
         },
-        "$specify$270": {
+        "$specify$269": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -157,7 +157,7 @@
             "SRC": [ 2 ]
           }
         },
-        "$specify$271": {
+        "$specify$270": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -188,7 +188,7 @@
             "SRC": [ 3 ]
           }
         },
-        "$specify$272": {
+        "$specify$271": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -219,7 +219,7 @@
             "SRC": [ 3 ]
           }
         },
-        "$specify$273": {
+        "$specify$272": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -250,7 +250,7 @@
             "SRC": [ 3 ]
           }
         },
-        "$specify$274": {
+        "$specify$273": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -281,7 +281,7 @@
             "SRC": [ 4 ]
           }
         },
-        "$specify$275": {
+        "$specify$274": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -312,7 +312,7 @@
             "SRC": [ 4 ]
           }
         },
-        "$specify$276": {
+        "$specify$275": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -343,7 +343,7 @@
             "SRC": [ 4 ]
           }
         },
-        "$specify$277": {
+        "$specify$276": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -374,7 +374,7 @@
             "SRC": [ 5 ]
           }
         },
-        "$specify$278": {
+        "$specify$277": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -405,7 +405,7 @@
             "SRC": [ 5 ]
           }
         },
-        "$specify$279": {
+        "$specify$278": {
           "hide_name": 1,
           "type": "$specify3",
           "parameters": {
@@ -442,7 +442,7 @@
             "SRC": [ 7 ]
           }
         },
-        "$specify$280": {
+        "$specify$279": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -473,7 +473,7 @@
             "SRC": [ 9 ]
           }
         },
-        "$specify$281": {
+        "$specify$280": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -508,7 +508,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$282": {
+        "$specify$281": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -543,7 +543,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$283": {
+        "$specify$282": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -578,7 +578,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$284": {
+        "$specify$283": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -613,7 +613,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$285": {
+        "$specify$284": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -648,7 +648,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$286": {
+        "$specify$285": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -683,7 +683,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$287": {
+        "$specify$286": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -718,7 +718,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$288": {
+        "$specify$287": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -753,7 +753,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$289": {
+        "$specify$288": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -788,7 +788,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$290": {
+        "$specify$289": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -823,7 +823,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$291": {
+        "$specify$290": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -858,7 +858,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$292": {
+        "$specify$291": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -893,7 +893,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$293": {
+        "$specify$292": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -928,7 +928,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$294": {
+        "$specify$293": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -963,7 +963,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$295": {
+        "$specify$294": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -998,7 +998,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$296": {
+        "$specify$295": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -1033,7 +1033,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$297": {
+        "$specify$296": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -1068,7 +1068,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$298": {
+        "$specify$297": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -1103,7 +1103,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$299": {
+        "$specify$298": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -1138,7 +1138,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$300": {
+        "$specify$299": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -1173,7 +1173,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$301": {
+        "$specify$300": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -1208,7 +1208,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$302": {
+        "$specify$301": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -3555,6 +3555,7 @@
     "SB_GB": {
       "attributes": {
         "blackbox": "00000000000000000000000000000001",
+        "cells_not_processed": "00000000000000000000000000000001",
         "src": "/usr/local/bin/../share/yosys/ice40/cells_sim.v:162.1-172.10"
       },
       "ports": {
@@ -6389,7 +6390,7 @@
         }
       },
       "cells": {
-        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1593$387": {
+        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1593$386": {
           "hide_name": 1,
           "type": "$logic_and",
           "parameters": {
@@ -6413,7 +6414,7 @@
             "Y": [ 78 ]
           }
         },
-        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1595$388": {
+        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1595$387": {
           "hide_name": 1,
           "type": "$logic_and",
           "parameters": {
@@ -6437,7 +6438,7 @@
             "Y": [ 79 ]
           }
         },
-        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1601$389": {
+        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1601$388": {
           "hide_name": 1,
           "type": "$logic_and",
           "parameters": {
@@ -6461,7 +6462,7 @@
             "Y": [ 80 ]
           }
         },
-        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1605$390": {
+        "$logic_and$/usr/local/bin/../share/yosys/ice40/cells_sim.v:1605$389": {
           "hide_name": 1,
           "type": "$logic_and",
           "parameters": {
@@ -6485,7 +6486,7 @@
             "Y": [ 81 ]
           }
         },
-        "$specify$232": {
+        "$specify$231": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -6520,7 +6521,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$233": {
+        "$specify$232": {
           "hide_name": 1,
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@@ -10329,18 +10280,18 @@
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@@ -10377,9 +10328,9 @@
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@@ -10449,9 +10375,9 @@
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@@ -10473,11 +10399,11 @@
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@@ -10498,11 +10424,136 @@
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@@ -10521,10 +10572,10 @@
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@@ -10545,18 +10596,18 @@
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@@ -10570,11 +10621,11 @@
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@@ -10594,11 +10645,11 @@
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@@ -12173,9 +12349,9 @@
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@@ -12466,7 +12642,7 @@
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@@ -12492,7 +12668,7 @@
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@@ -18593,11 +18794,61 @@
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         "rx_09_fifo.mem_i.0.0.0": {
@@ -18642,14 +18893,14 @@
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@@ -18696,14 +18947,14 @@
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@@ -18750,14 +19001,14 @@
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@@ -18804,14 +19055,14 @@
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@@ -18823,7 +19074,7 @@
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@@ -18833,11 +19084,11 @@
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@@ -18847,7 +19098,7 @@
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@@ -21119,11 +21295,11 @@
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-            "I1": [ 608 ],
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-            "O": [ 644 ]
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         "rx_24_fifo.mem_i.0.0.0": {
@@ -21168,15 +21344,15 @@
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@@ -21222,15 +21398,15 @@
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@@ -21276,15 +21452,15 @@
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@@ -21330,15 +21506,15 @@
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@@ -21349,7 +21525,7 @@
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@@ -21359,11 +21535,11 @@
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@@ -21373,7 +21549,7 @@
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@@ -21383,11 +21559,11 @@
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@@ -21397,7 +21573,7 @@
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@@ -21407,11 +21583,11 @@
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@@ -21421,7 +21597,7 @@
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@@ -21431,11 +21607,11 @@
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@@ -21445,7 +21621,7 @@
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@@ -21455,11 +21631,11 @@
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@@ -21469,7 +21645,7 @@
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@@ -21479,11 +21655,11 @@
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@@ -21493,7 +21669,7 @@
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@@ -21503,11 +21679,11 @@
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@@ -21517,7 +21693,7 @@
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@@ -21527,11 +21703,11 @@
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@@ -21541,7 +21717,7 @@
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@@ -21551,11 +21727,11 @@
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@@ -21566,7 +21742,7 @@
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@@ -21578,7 +21754,7 @@
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-            "I2": [ 354 ],
+            "I2": [ 583 ],
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@@ -23704,10 +23905,10 @@
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@@ -23730,7 +23931,7 @@
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@@ -23754,60 +23955,10 @@
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@@ -23831,8 +23982,8 @@
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@@ -23855,16 +24006,16 @@
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@@ -23878,18 +24029,18 @@
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@@ -23903,11 +24054,11 @@
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@@ -23928,14 +24079,14 @@
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-        "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O": {
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@@ -23943,7 +24094,7 @@
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@@ -23955,12 +24106,12 @@
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-        "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_1": {
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@@ -23968,7 +24119,7 @@
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@@ -23980,12 +24131,12 @@
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-        "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_2": {
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@@ -23993,7 +24144,7 @@
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@@ -24005,37 +24156,12 @@
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-        "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_4": {
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@@ -24043,7 +24169,7 @@
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@@ -24055,12 +24181,12 @@
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-        "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_5": {
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@@ -24068,7 +24194,57 @@
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@@ -24081,11 +24257,11 @@
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-        "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_6": {
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@@ -24093,7 +24269,7 @@
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@@ -24105,9 +24281,9 @@
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+            "I2": [ 294 ],
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@@ -24117,7 +24293,7 @@
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@@ -24126,10 +24302,10 @@
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@@ -24139,7 +24315,7 @@
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+            "src": "top.v:311.13-342.5|smi_ctrl.v:139.5-152.8|/usr/local/bin/../share/yosys/ice40/ff_map.v:19.59-19.105"
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@@ -24148,10 +24324,10 @@
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@@ -24173,10 +24349,10 @@
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@@ -24197,11 +24373,61 @@
             "O": "output"
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+          "hide_name": 0,
+          "type": "SB_LUT4",
+          "parameters": {
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@@ -24536,7 +24712,7 @@
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@@ -24571,9 +24747,9 @@
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@@ -24617,10 +24793,10 @@
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@@ -24630,7 +24806,7 @@
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@@ -24639,10 +24815,10 @@
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@@ -24664,10 +24840,10 @@
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@@ -24691,8 +24867,8 @@
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@@ -24712,11 +24888,11 @@
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@@ -24739,9 +24915,9 @@
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@@ -24764,8 +24940,8 @@
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@@ -24789,9 +24965,9 @@
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@@ -24814,9 +24990,9 @@
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@@ -24837,11 +25013,11 @@
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@@ -24862,11 +25038,11 @@
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@@ -24888,10 +25064,10 @@
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@@ -24912,11 +25088,11 @@
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@@ -24937,11 +25113,11 @@
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@@ -24960,10 +25136,10 @@
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@@ -24982,10 +25158,10 @@
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@@ -25004,10 +25180,10 @@
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@@ -25026,10 +25202,10 @@
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@@ -25048,10 +25224,10 @@
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@@ -25070,10 +25246,10 @@
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@@ -25092,10 +25268,10 @@
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@@ -25114,10 +25290,10 @@
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@@ -25138,11 +25314,11 @@
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@@ -25162,11 +25338,11 @@
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@@ -25189,20 +25365,20 @@
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@@ -25212,11 +25388,11 @@
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@@ -25238,85 +25414,10 @@
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@@ -25335,10 +25436,10 @@
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@@ -25357,10 +25458,10 @@
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@@ -25379,10 +25480,10 @@
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@@ -25401,10 +25502,10 @@
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@@ -25423,10 +25524,35 @@
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+          "type": "SB_LUT4",
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         "spi_if_ins.o_load_cmd_SB_DFFESR_Q": {
@@ -25446,111 +25572,11 @@
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@@ -25571,93 +25597,18 @@
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-          "type": "SB_LUT4",
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@@ -25671,11 +25622,36 @@
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+          }
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+        "spi_if_ins.o_load_cmd_SB_LUT4_I3_1": {
+          "hide_name": 0,
+          "type": "SB_LUT4",
+          "parameters": {
+            "LUT_INIT": "0001000000000000"
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+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
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         "spi_if_ins.r_tx_byte_SB_DFFE_Q": {
@@ -25694,10 +25670,10 @@
             "Q": "output"
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@@ -25716,10 +25692,10 @@
             "Q": "output"
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@@ -25738,10 +25714,10 @@
             "Q": "output"
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@@ -25760,10 +25736,10 @@
             "Q": "output"
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@@ -25782,10 +25758,10 @@
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@@ -25804,10 +25780,10 @@
             "Q": "output"
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@@ -25826,10 +25802,10 @@
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@@ -25848,10 +25824,10 @@
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@@ -25871,11 +25847,11 @@
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@@ -25898,9 +25874,9 @@
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@@ -25922,21 +25898,21 @@
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@@ -25946,39 +25922,14 @@
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@@ -25999,158 +25950,8 @@
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@@ -26168,9 +25969,9 @@
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@@ -26188,9 +25989,9 @@
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@@ -26208,9 +26009,59 @@
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+          "type": "SB_LUT4",
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+        "spi_if_ins.spi.SCKr_SB_LUT4_I1": {
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+          "type": "SB_LUT4",
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@@ -26229,10 +26080,10 @@
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@@ -26251,10 +26102,10 @@
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@@ -26273,10 +26124,10 @@
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@@ -26295,10 +26146,10 @@
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@@ -26317,10 +26168,10 @@
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@@ -26339,10 +26190,10 @@
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@@ -26361,10 +26212,10 @@
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@@ -26383,10 +26234,10 @@
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@@ -26404,9 +26255,9 @@
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@@ -26425,10 +26276,10 @@
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@@ -26450,10 +26301,160 @@
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@@ -26471,9 +26472,9 @@
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@@ -26491,9 +26492,9 @@
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@@ -26516,84 +26517,78 @@
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-        "spi_if_ins.spi.r_rx_bit_count_SB_DFFESR_Q": {
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-        "spi_if_ins.spi.r_rx_bit_count_SB_DFFESR_Q_1": {
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           "hide_name": 0,
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-        "spi_if_ins.spi.r_rx_bit_count_SB_DFFESR_Q_2": {
+        "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2": {
           "hide_name": 0,
-          "type": "SB_DFFESR",
+          "type": "SB_DFFSR",
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-        "spi_if_ins.spi.r_rx_bit_count_SB_DFFESR_Q_2_D_SB_LUT4_O": {
+        "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D_SB_LUT4_O": {
           "hide_name": 0,
           "type": "SB_LUT4",
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@@ -26614,11 +26609,11 @@
             "I0": [ "0" ],
             "I1": [ "0" ],
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-        "spi_if_ins.spi.r_rx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O": {
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           "type": "SB_LUT4",
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@@ -26626,7 +26621,7 @@
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+            "src": "top.v:92.11-108.5|spi_slave.v:34.25-34.43|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
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@@ -26638,12 +26633,12 @@
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-            "I2": [ 78 ],
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-        "spi_if_ins.spi.r_rx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_1": {
+        "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_1": {
           "hide_name": 0,
           "type": "SB_LUT4",
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@@ -26651,7 +26646,7 @@
           },
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+            "src": "top.v:92.11-108.5|spi_slave.v:34.25-34.43|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
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@@ -26663,18 +26658,18 @@
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-            "I2": [ 79 ],
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-            "O": [ 882 ]
+            "I2": [ 878 ],
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-        "spi_if_ins.spi.r_rx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO": {
+        "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO": {
           "hide_name": 0,
           "type": "SB_CARRY",
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+            "src": "top.v:92.11-108.5|spi_slave.v:34.25-34.43|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4"
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@@ -26683,10 +26678,10 @@
             "I1": "input"
           },
           "connections": {
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-            "CO": [ 884 ],
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-            "I1": [ 79 ]
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         "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q": {
@@ -26696,7 +26691,7 @@
           },
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+            "src": "top.v:92.11-108.5|spi_slave.v:28.3-44.6|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
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@@ -26705,10 +26700,10 @@
             "Q": "output"
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         "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_1": {
@@ -26718,7 +26713,7 @@
           },
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+            "src": "top.v:92.11-108.5|spi_slave.v:28.3-44.6|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
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@@ -26727,10 +26722,10 @@
             "Q": "output"
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+            "C": [ 44 ],
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         "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_2": {
@@ -26740,7 +26735,7 @@
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+            "src": "top.v:92.11-108.5|spi_slave.v:28.3-44.6|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
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@@ -26749,10 +26744,10 @@
             "Q": "output"
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+            "C": [ 44 ],
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         "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_3": {
@@ -26762,7 +26757,7 @@
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+            "src": "top.v:92.11-108.5|spi_slave.v:28.3-44.6|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
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@@ -26771,10 +26766,10 @@
             "Q": "output"
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+            "C": [ 44 ],
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         "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_4": {
@@ -26784,7 +26779,7 @@
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-            "src": "top.v:92.11-108.5|spi_slave.v:46.3-62.6|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
+            "src": "top.v:92.11-108.5|spi_slave.v:28.3-44.6|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
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@@ -26793,10 +26788,10 @@
             "Q": "output"
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         "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_5": {
@@ -26806,7 +26801,7 @@
           },
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+            "src": "top.v:92.11-108.5|spi_slave.v:28.3-44.6|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
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@@ -26815,10 +26810,10 @@
             "Q": "output"
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           "connections": {
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+            "C": [ 44 ],
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         "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_6": {
@@ -26828,7 +26823,7 @@
           },
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+            "src": "top.v:92.11-108.5|spi_slave.v:28.3-44.6|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
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@@ -26837,10 +26832,10 @@
             "Q": "output"
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+            "C": [ 44 ],
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         "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_7": {
@@ -26850,7 +26845,7 @@
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-            "src": "top.v:92.11-108.5|spi_slave.v:46.3-62.6|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
+            "src": "top.v:92.11-108.5|spi_slave.v:28.3-44.6|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:5.57-5.103"
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@@ -26859,17 +26854,41 @@
             "Q": "output"
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+            "Q": [ 855 ]
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-        "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_E_SB_LUT4_O": {
+        "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q": {
+          "hide_name": 0,
+          "type": "SB_DFFESR",
+          "parameters": {
+          },
+          "attributes": {
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+            "src": "top.v:92.11-108.5|spi_slave.v:28.3-44.6|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
+          },
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+            "C": "input",
+            "D": "input",
+            "E": "input",
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+        },
+        "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3": {
           "hide_name": 0,
           "type": "SB_LUT4",
           "parameters": {
-            "LUT_INIT": "1111000000000000"
+            "LUT_INIT": "0000111100000000"
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@@ -26885,40 +26904,16 @@
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             "I1": [ "0" ],
-            "I2": [ 80 ],
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-            "O": [ 886 ]
+            "I2": [ 45 ],
+            "I3": [ 890 ],
+            "O": [ 883 ]
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-        "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q": {
-          "hide_name": 0,
-          "type": "SB_DFFESR",
-          "parameters": {
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-            "src": "top.v:92.11-108.5|spi_slave.v:46.3-62.6|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/ff_map.v:24.66-24.119"
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-        },
-        "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E_SB_LUT4_O": {
+        "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_O": {
           "hide_name": 0,
           "type": "SB_LUT4",
           "parameters": {
-            "LUT_INIT": "1100111100000000"
+            "LUT_INIT": "1100000000000000"
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@@ -26933,10 +26928,35 @@
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-            "I1": [ 45 ],
-            "I2": [ 866 ],
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-            "O": [ 893 ]
+            "I1": [ 880 ],
+            "I2": [ 876 ],
+            "I3": [ 878 ],
+            "O": [ 890 ]
+          }
+        },
+        "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E_SB_LUT4_O": {
+          "hide_name": 0,
+          "type": "SB_LUT4",
+          "parameters": {
+            "LUT_INIT": "1110101110101010"
+          },
+          "attributes": {
+            "module_not_derived": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+          },
+          "port_directions": {
+            "I0": "input",
+            "I1": "input",
+            "I2": "input",
+            "I3": "input",
+            "O": "output"
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+            "I1": [ 880 ],
+            "I2": [ 876 ],
+            "I3": [ 878 ],
+            "O": [ 891 ]
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         },
         "spi_if_ins.spi.r_temp_rx_byte_SB_DFFE_Q": {
@@ -26946,7 +26966,7 @@
           },
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@@ -27065,10 +27085,10 @@
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@@ -27087,10 +27107,10 @@
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@@ -27110,11 +27130,11 @@
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@@ -27136,10 +27156,10 @@
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@@ -27161,10 +27181,10 @@
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@@ -27207,9 +27227,9 @@
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@@ -27234,8 +27254,8 @@
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@@ -27255,11 +27275,11 @@
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@@ -27279,11 +27299,11 @@
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@@ -27303,11 +27323,11 @@
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@@ -27327,11 +27347,11 @@
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@@ -27351,11 +27371,11 @@
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@@ -27375,11 +27395,11 @@
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@@ -27399,11 +27419,11 @@
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@@ -27423,11 +27443,11 @@
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@@ -27447,11 +27467,11 @@
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@@ -27471,11 +27491,11 @@
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@@ -27497,35 +27517,10 @@
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@@ -27545,11 +27540,11 @@
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@@ -27569,36 +27564,11 @@
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@@ -27620,10 +27590,35 @@
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@@ -27647,8 +27642,8 @@
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@@ -27667,10 +27662,10 @@
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@@ -27691,11 +27686,36 @@
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+        "spi_if_ins.state_if_SB_DFFE_Q_D_SB_LUT4_O_1": {
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+          "type": "SB_LUT4",
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@@ -27716,29 +27736,11 @@
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-            "USER_SIGNAL_TO_GLOBAL_BUFFER": [ 410 ]
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         "sys_ctrl_ins.i_cs_SB_DFFE_Q": {
@@ -27757,10 +27759,10 @@
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+            "C": [ 70 ],
+            "D": [ 83 ],
+            "E": [ 81 ],
+            "Q": [ 809 ]
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         },
         "sys_ctrl_ins.o_data_out_SB_DFFE_Q": {
@@ -27779,10 +27781,10 @@
             "Q": "output"
           },
           "connections": {
-            "C": [ 82 ],
-            "D": [ 103 ],
-            "E": [ 904 ],
-            "Q": [ 905 ]
+            "C": [ 70 ],
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+            "Q": [ 902 ]
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         },
         "sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O": {
@@ -27804,60 +27806,10 @@
           },
           "connections": {
             "I0": [ "0" ],
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-            "I2": [ 811 ],
-            "I3": [ 825 ],
-            "O": [ 904 ]
-          }
-        },
-        "sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I1": {
-          "hide_name": 0,
-          "type": "SB_LUT4",
-          "parameters": {
-            "LUT_INIT": "0011111111111111"
-          },
-          "attributes": {
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-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-          },
-          "port_directions": {
-            "I0": "input",
-            "I1": "input",
-            "I2": "input",
-            "I3": "input",
-            "O": "output"
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-          "connections": {
-            "I0": [ "0" ],
-            "I1": [ 52 ],
-            "I2": [ 51 ],
-            "I3": [ 53 ],
-            "O": [ 103 ]
-          }
-        },
-        "sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I3": {
-          "hide_name": 0,
-          "type": "SB_LUT4",
-          "parameters": {
-            "LUT_INIT": "1100111111111111"
-          },
-          "attributes": {
-            "module_not_derived": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
-          },
-          "port_directions": {
-            "I0": "input",
-            "I1": "input",
-            "I2": "input",
-            "I3": "input",
-            "O": "output"
-          },
-          "connections": {
-            "I0": [ "0" ],
-            "I1": [ 53 ],
-            "I2": [ 51 ],
-            "I3": [ 52 ],
-            "O": [ 97 ]
+            "I1": [ 105 ],
+            "I2": [ 809 ],
+            "I3": [ 89 ],
+            "O": [ 901 ]
           }
         },
         "sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_O": {
@@ -27879,10 +27831,10 @@
           },
           "connections": {
             "I0": [ "0" ],
-            "I1": [ 832 ],
-            "I2": [ 830 ],
-            "I3": [ 831 ],
-            "O": [ 52 ]
+            "I1": [ 108 ],
+            "I2": [ 106 ],
+            "I3": [ 107 ],
+            "O": [ 105 ]
           }
         },
         "sys_ctrl_ins.o_data_out_SB_LUT4_I0": {
@@ -27903,11 +27855,11 @@
             "O": "output"
           },
           "connections": {
-            "I0": [ 905 ],
-            "I1": [ 414 ],
-            "I2": [ 428 ],
-            "I3": [ 738 ],
-            "O": [ 429 ]
+            "I0": [ 902 ],
+            "I1": [ 419 ],
+            "I2": [ 433 ],
+            "I3": [ 739 ],
+            "O": [ 435 ]
           }
         },
         "sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q": {
@@ -27927,11 +27879,11 @@
             "S": "input"
           },
           "connections": {
-            "C": [ 82 ],
+            "C": [ 70 ],
             "D": [ "0" ],
-            "E": [ 906 ],
-            "Q": [ 54 ],
-            "S": [ 907 ]
+            "E": [ 903 ],
+            "Q": [ 49 ],
+            "S": [ 904 ]
           }
         },
         "sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E_SB_LUT4_O": {
@@ -27955,8 +27907,8 @@
             "I0": [ "0" ],
             "I1": [ "0" ],
             "I2": [ "0" ],
-            "I3": [ 908 ],
-            "O": [ 906 ]
+            "I3": [ 905 ],
+            "O": [ 903 ]
           }
         },
         "sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S_SB_LUT4_O": {
@@ -27977,11 +27929,11 @@
             "O": "output"
           },
           "connections": {
-            "I0": [ 909 ],
-            "I1": [ 910 ],
-            "I2": [ 911 ],
-            "I3": [ 912 ],
-            "O": [ 907 ]
+            "I0": [ 906 ],
+            "I1": [ 907 ],
+            "I2": [ 908 ],
+            "I3": [ 909 ],
+            "O": [ 904 ]
           }
         },
         "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q": {
@@ -28001,11 +27953,11 @@
             "R": "input"
           },
           "connections": {
-            "C": [ 82 ],
+            "C": [ 70 ],
             "D": [ "1" ],
-            "E": [ 913 ],
-            "Q": [ 908 ],
-            "R": [ 914 ]
+            "E": [ 910 ],
+            "Q": [ 905 ],
+            "R": [ 911 ]
           }
         },
         "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E_SB_LUT4_O": {
@@ -28026,61 +27978,11 @@
             "O": "output"
           },
           "connections": {
-            "I0": [ 825 ],
-            "I1": [ 915 ],
-            "I2": [ 834 ],
-            "I3": [ 811 ],
-            "O": [ 913 ]
-          }
-        },
-        "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2": {
-          "hide_name": 0,
-          "type": "SB_LUT4",
-          "parameters": {
-            "LUT_INIT": "1111000000000000"
-          },
-          "attributes": {
-            "module_not_derived": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-          },
-          "port_directions": {
-            "I0": "input",
-            "I1": "input",
-            "I2": "input",
-            "I3": "input",
-            "O": "output"
-          },
-          "connections": {
-            "I0": [ "0" ],
-            "I1": [ "0" ],
-            "I2": [ 915 ],
-            "I3": [ 164 ],
-            "O": [ 165 ]
-          }
-        },
-        "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_O": {
-          "hide_name": 0,
-          "type": "SB_LUT4",
-          "parameters": {
-            "LUT_INIT": "0000111100000000"
-          },
-          "attributes": {
-            "module_not_derived": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
-          },
-          "port_directions": {
-            "I0": "input",
-            "I1": "input",
-            "I2": "input",
-            "I3": "input",
-            "O": "output"
-          },
-          "connections": {
-            "I0": [ "0" ],
-            "I1": [ "0" ],
-            "I2": [ 51 ],
-            "I3": [ 108 ],
-            "O": [ 915 ]
+            "I0": [ 89 ],
+            "I1": [ 86 ],
+            "I2": [ 90 ],
+            "I3": [ 809 ],
+            "O": [ 910 ]
           }
         },
         "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R_SB_LUT4_O": {
@@ -28104,8 +28006,8 @@
             "I0": [ "0" ],
             "I1": [ "0" ],
             "I2": [ "0" ],
-            "I3": [ 811 ],
-            "O": [ 914 ]
+            "I3": [ 809 ],
+            "O": [ 911 ]
           }
         },
         "sys_ctrl_ins.reset_cmd_SB_LUT4_I3": {
@@ -28128,9 +28030,9 @@
           "connections": {
             "I0": [ "0" ],
             "I1": [ "0" ],
-            "I2": [ 907 ],
-            "I3": [ 908 ],
-            "O": [ 916 ]
+            "I2": [ 904 ],
+            "I3": [ 905 ],
+            "O": [ 912 ]
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q": {
@@ -28150,11 +28052,11 @@
             "R": "input"
           },
           "connections": {
-            "C": [ 82 ],
-            "D": [ 917 ],
-            "E": [ 916 ],
-            "Q": [ 909 ],
-            "R": [ 908 ]
+            "C": [ 70 ],
+            "D": [ 913 ],
+            "E": [ 912 ],
+            "Q": [ 906 ],
+            "R": [ 905 ]
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_1": {
@@ -28174,11 +28076,11 @@
             "R": "input"
           },
           "connections": {
-            "C": [ 82 ],
-            "D": [ 918 ],
-            "E": [ 916 ],
-            "Q": [ 911 ],
-            "R": [ 908 ]
+            "C": [ 70 ],
+            "D": [ 914 ],
+            "E": [ 912 ],
+            "Q": [ 908 ],
+            "R": [ 905 ]
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_1_D_SB_LUT4_O": {
@@ -28199,11 +28101,11 @@
             "O": "output"
           },
           "connections": {
-            "I0": [ 907 ],
+            "I0": [ 904 ],
             "I1": [ "0" ],
-            "I2": [ 911 ],
-            "I3": [ 919 ],
-            "O": [ 918 ]
+            "I2": [ 908 ],
+            "I3": [ 915 ],
+            "O": [ 914 ]
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_2": {
@@ -28223,11 +28125,11 @@
             "R": "input"
           },
           "connections": {
-            "C": [ 82 ],
-            "D": [ 920 ],
-            "E": [ 916 ],
-            "Q": [ 910 ],
-            "R": [ 908 ]
+            "C": [ 70 ],
+            "D": [ 916 ],
+            "E": [ 912 ],
+            "Q": [ 907 ],
+            "R": [ 905 ]
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_2_D_SB_LUT4_O": {
@@ -28248,11 +28150,11 @@
             "O": "output"
           },
           "connections": {
-            "I0": [ 907 ],
+            "I0": [ 904 ],
             "I1": [ "0" ],
-            "I2": [ 910 ],
-            "I3": [ 912 ],
-            "O": [ 920 ]
+            "I2": [ 907 ],
+            "I3": [ 909 ],
+            "O": [ 916 ]
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_3": {
@@ -28272,11 +28174,11 @@
             "R": "input"
           },
           "connections": {
-            "C": [ 82 ],
-            "D": [ 921 ],
-            "E": [ 916 ],
-            "Q": [ 912 ],
-            "R": [ 908 ]
+            "C": [ 70 ],
+            "D": [ 917 ],
+            "E": [ 912 ],
+            "Q": [ 909 ],
+            "R": [ 905 ]
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_3_D_SB_LUT4_O": {
@@ -28300,8 +28202,8 @@
             "I0": [ "0" ],
             "I1": [ "0" ],
             "I2": [ "0" ],
-            "I3": [ 912 ],
-            "O": [ 921 ]
+            "I3": [ 909 ],
+            "O": [ 917 ]
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O": {
@@ -28322,11 +28224,11 @@
             "O": "output"
           },
           "connections": {
-            "I0": [ 907 ],
+            "I0": [ 904 ],
             "I1": [ "0" ],
-            "I2": [ 909 ],
-            "I3": [ 922 ],
-            "O": [ 917 ]
+            "I2": [ 906 ],
+            "I3": [ 918 ],
+            "O": [ 913 ]
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO": {
@@ -28344,10 +28246,10 @@
             "I1": "input"
           },
           "connections": {
-            "CI": [ 919 ],
-            "CO": [ 922 ],
+            "CI": [ 915 ],
+            "CO": [ 918 ],
             "I0": [ "0" ],
-            "I1": [ 911 ]
+            "I1": [ 908 ]
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO_1": {
@@ -28365,10 +28267,10 @@
             "I1": "input"
           },
           "connections": {
-            "CI": [ 912 ],
-            "CO": [ 919 ],
+            "CI": [ 909 ],
+            "CO": [ 915 ],
             "I0": [ "0" ],
-            "I1": [ 910 ]
+            "I1": [ 907 ]
           }
         },
         "w_smi_read_req_SB_LUT4_O": {
@@ -28391,9 +28293,9 @@
           "connections": {
             "I0": [ "0" ],
             "I1": [ "0" ],
-            "I2": [ 590 ],
-            "I3": [ 432 ],
-            "O": [ 408 ]
+            "I2": [ 567 ],
+            "I3": [ 438 ],
+            "O": [ 414 ]
           }
         }
       },
@@ -28405,9 +28307,9 @@
             "src": "top.v:40.13-40.21"
           }
         },
-        "i_button_SB_LUT4_I0_I1": {
+        "i_button_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 47, 15 ],
+          "bits": [ 124, 86, 48, 125 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -28469,12 +28371,6 @@
             "src": "top.v:46.13-46.21"
           }
         },
-        "i_smi_a1_SB_LUT4_I1_O": {
-          "hide_name": 0,
-          "bits": [ 56 ],
-          "attributes": {
-          }
-        },
         "i_smi_a2": {
           "hide_name": 0,
           "bits": [ 29 ],
@@ -28482,22 +28378,28 @@
             "src": "top.v:47.13-47.21"
           }
         },
-        "i_smi_a2_SB_LUT4_I1_O": {
+        "i_smi_a2_SB_LUT4_I1_1_O": {
           "hide_name": 0,
-          "bits": [ 70, 67, 62, 57 ],
+          "bits": [ 65, 62, 57, 52 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "i_smi_a2_SB_LUT4_I1_O_SB_LUT4_O_I3": {
+        "i_smi_a2_SB_LUT4_I1_1_O_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 58, 59, 60, 61 ],
+          "bits": [ 53, 54, 55, 56 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
+        "i_smi_a2_SB_LUT4_I1_O": {
+          "hide_name": 0,
+          "bits": [ 51 ],
+          "attributes": {
+          }
+        },
         "i_smi_a3": {
           "hide_name": 0,
           "bits": [ 30 ],
@@ -28526,24 +28428,16 @@
             "src": "top.v:59.13-59.17"
           }
         },
-        "i_ss_SB_LUT4_I1_O": {
-          "hide_name": 0,
-          "bits": [ 80, 76 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
         "int_miso": {
           "hide_name": 0,
-          "bits": [ 406 ],
+          "bits": [ 413 ],
           "attributes": {
             "src": "top.v:110.9-110.17"
           }
         },
         "io_ctrl_ins.debug_mode": {
           "hide_name": 0,
-          "bits": [ 87, 85 ],
+          "bits": [ 75, 73 ],
           "attributes": {
             "hdlname": "io_ctrl_ins debug_mode",
             "src": "top.v:128.12-156.5|io_ctrl.v:67.17-67.27"
@@ -28551,7 +28445,7 @@
         },
         "io_ctrl_ins.debug_mode_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 176, 89, 88, 91 ],
+          "bits": [ 97, 76, 79 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -28575,7 +28469,7 @@
         },
         "io_ctrl_ins.i_cs": {
           "hide_name": 0,
-          "bits": [ 94 ],
+          "bits": [ 82 ],
           "attributes": {
             "hdlname": "io_ctrl_ins i_cs",
             "src": "top.v:128.12-156.5|io_ctrl.v:9.29-9.33"
@@ -28583,7 +28477,7 @@
         },
         "io_ctrl_ins.i_data_in": {
           "hide_name": 0,
-          "bits": [ 86, 83, 163, 162, 161, 160, 158, 155 ],
+          "bits": [ 74, 71, 165, 164, 163, 161, 159, 156 ],
           "attributes": {
             "hdlname": "io_ctrl_ins i_data_in",
             "src": "top.v:128.12-156.5|io_ctrl.v:7.29-7.38"
@@ -28591,7 +28485,7 @@
         },
         "io_ctrl_ins.i_fetch_cmd": {
           "hide_name": 0,
-          "bits": [ 825 ],
+          "bits": [ 89 ],
           "attributes": {
             "hdlname": "io_ctrl_ins i_fetch_cmd",
             "src": "top.v:128.12-156.5|io_ctrl.v:10.29-10.40"
@@ -28599,7 +28493,7 @@
         },
         "io_ctrl_ins.i_ioc": {
           "hide_name": 0,
-          "bits": [ 51, 53, 832, 831, 830 ],
+          "bits": [ 101, 104, 108, 107, 106 ],
           "attributes": {
             "hdlname": "io_ctrl_ins i_ioc",
             "src": "top.v:128.12-156.5|io_ctrl.v:6.29-6.34"
@@ -28607,7 +28501,7 @@
         },
         "io_ctrl_ins.i_load_cmd": {
           "hide_name": 0,
-          "bits": [ 834 ],
+          "bits": [ 90 ],
           "attributes": {
             "hdlname": "io_ctrl_ins i_load_cmd",
             "src": "top.v:128.12-156.5|io_ctrl.v:11.29-11.39"
@@ -28615,7 +28509,7 @@
         },
         "io_ctrl_ins.i_reset": {
           "hide_name": 0,
-          "bits": [ 54 ],
+          "bits": [ 49 ],
           "attributes": {
             "hdlname": "io_ctrl_ins i_reset",
             "src": "top.v:128.12-156.5|io_ctrl.v:3.29-3.36"
@@ -28623,7 +28517,7 @@
         },
         "io_ctrl_ins.i_sys_clk": {
           "hide_name": 0,
-          "bits": [ 82 ],
+          "bits": [ 70 ],
           "attributes": {
             "hdlname": "io_ctrl_ins i_sys_clk",
             "src": "top.v:128.12-156.5|io_ctrl.v:4.29-4.38"
@@ -28639,7 +28533,7 @@
         },
         "io_ctrl_ins.led0_state_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 154, 103, 117, 98 ],
+          "bits": [ 154, 131, 87, 112 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -28655,13 +28549,21 @@
         },
         "io_ctrl_ins.led1_state_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 96 ],
+          "bits": [ 84 ],
           "attributes": {
           }
         },
-        "io_ctrl_ins.led1_state_SB_LUT4_I0_I2": {
+        "io_ctrl_ins.led1_state_SB_DFFESR_Q_E_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 27, 47, 100, 101 ],
+          "bits": [ 88, 49 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "io_ctrl_ins.led1_state_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 130, 131, 92, 95 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -28677,7 +28579,7 @@
         },
         "io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 105 ],
+          "bits": [ 96 ],
           "attributes": {
             "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8"
           }
@@ -28692,14 +28594,30 @@
         },
         "io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 109 ],
+          "bits": [ 98 ],
           "attributes": {
             "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8"
           }
         },
-        "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_O": {
+        "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3": {
           "hide_name": 0,
-          "bits": [ 151, 97, 112 ],
+          "bits": [ 102, 101 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I2_O": {
+          "hide_name": 0,
+          "bits": [ 91, 6, 94, 77 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "io_ctrl_ins.lna_tx_shutdown_state_SB_LUT4_I1_I3_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 168, 86, 47, 14 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -28707,7 +28625,7 @@
         },
         "io_ctrl_ins.mixer_en_state": {
           "hide_name": 0,
-          "bits": [ 114 ],
+          "bits": [ 110 ],
           "attributes": {
             "hdlname": "io_ctrl_ins mixer_en_state",
             "src": "top.v:128.12-156.5|io_ctrl.v:76.17-76.31"
@@ -28715,14 +28633,14 @@
         },
         "io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 113 ],
+          "bits": [ 109 ],
           "attributes": {
             "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8"
           }
         },
         "io_ctrl_ins.o_data_out": {
           "hide_name": 0,
-          "bits": [ 153, 119, 147, 122, 127, 133, 139, 142 ],
+          "bits": [ 153, 128, 144, 133, 138, 115, 118, 123 ],
           "attributes": {
             "hdlname": "io_ctrl_ins o_data_out",
             "src": "top.v:128.12-156.5|io_ctrl.v:8.29-8.39"
@@ -28730,7 +28648,7 @@
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 121 ],
+          "bits": [ 117 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
@@ -28738,7 +28656,7 @@
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D": {
           "hide_name": 0,
-          "bits": [ 126 ],
+          "bits": [ 122 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
@@ -28746,7 +28664,7 @@
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D": {
           "hide_name": 0,
-          "bits": [ 131 ],
+          "bits": [ 126 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
@@ -28754,7 +28672,7 @@
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_4_D": {
           "hide_name": 0,
-          "bits": [ 138 ],
+          "bits": [ 132 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
@@ -28762,37 +28680,23 @@
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_5_D": {
           "hide_name": 0,
-          "bits": [ 50 ],
+          "bits": [ 137 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
           }
         },
-        "io_ctrl_ins.o_data_out_SB_DFFESR_Q_5_E": {
-          "hide_name": 0,
-          "bits": [ 132 ],
-          "attributes": {
-          }
-        },
-        "io_ctrl_ins.o_data_out_SB_DFFESR_Q_5_R": {
-          "hide_name": 0,
-          "bits": [ 51, 143, 134, 144 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D": {
           "hide_name": 0,
-          "bits": [ 145 ],
+          "bits": [ 142 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
           }
         },
-        "io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I3": {
+        "io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 103, 149, 150 ],
+          "bits": [ 146, 131, 147, 103 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -28800,13 +28704,19 @@
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E": {
           "hide_name": 0,
-          "bits": [ 146 ],
+          "bits": [ 143 ],
+          "attributes": {
+          }
+        },
+        "io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R": {
+          "hide_name": 0,
+          "bits": [ 145 ],
           "attributes": {
           }
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 102 ],
+          "bits": [ 113 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
@@ -28814,14 +28724,16 @@
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 118 ],
+          "bits": [ 114 ],
           "attributes": {
           }
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_R": {
           "hide_name": 0,
-          "bits": [ 120 ],
+          "bits": [ 101, 105, 116 ],
           "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
         "io_ctrl_ins.o_data_out_SB_DFFESS_Q_D": {
@@ -28832,6 +28744,20 @@
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
           }
         },
+        "io_ctrl_ins.o_data_out_SB_DFFESS_Q_E": {
+          "hide_name": 0,
+          "bits": [ 101, 104, 127 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "io_ctrl_ins.o_data_out_SB_DFFESS_Q_S": {
+          "hide_name": 0,
+          "bits": [ 129 ],
+          "attributes": {
+          }
+        },
         "io_ctrl_ins.o_led0": {
           "hide_name": 0,
           "bits": [ 26 ],
@@ -28866,7 +28792,7 @@
         },
         "io_ctrl_ins.o_pmod": {
           "hide_name": 0,
-          "bits": [ 116, 107, 111, 170, 169, 168, 167, 166 ],
+          "bits": [ 85, 93, 100, 169, 168, 149, 119, 124 ],
           "attributes": {
             "hdlname": "io_ctrl_ins o_pmod",
             "src": "top.v:128.12-156.5|io_ctrl.v:18.29-18.35"
@@ -28930,7 +28856,7 @@
         },
         "io_ctrl_ins.pmod_dir_state": {
           "hide_name": 0,
-          "bits": [ 154, 104, 149, 123, 128, 135, 159, 157 ],
+          "bits": [ 154, 130, 146, 134, 139, 162, 160, 158 ],
           "attributes": {
             "hdlname": "io_ctrl_ins pmod_dir_state",
             "src": "top.v:128.12-156.5|io_ctrl.v:73.17-73.31"
@@ -28938,29 +28864,41 @@
         },
         "io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E": {
           "hide_name": 0,
-          "bits": [ 156 ],
+          "bits": [ 157 ],
           "attributes": {
           }
         },
         "io_ctrl_ins.pmod_state": {
           "hide_name": 0,
-          "bits": [ 116, 107, 111, 170, 169, 168, 167, 166 ],
+          "bits": [ 85, 93, 100, 169, 168, 149, 119, 124 ],
           "attributes": {
             "hdlname": "io_ctrl_ins pmod_state",
             "src": "top.v:128.12-156.5|io_ctrl.v:74.17-74.27"
           }
         },
+        "io_ctrl_ins.pmod_state_SB_DFFE_Q_E": {
+          "hide_name": 0,
+          "bits": [ 167 ],
+          "attributes": {
+          }
+        },
         "io_ctrl_ins.rf_mode": {
           "hide_name": 0,
-          "bits": [ 151, 88, 89 ],
+          "bits": [ 148, 76, 77 ],
           "attributes": {
             "hdlname": "io_ctrl_ins rf_mode",
             "src": "top.v:128.12-156.5|io_ctrl.v:68.17-68.24"
           }
         },
+        "io_ctrl_ins.rf_mode_SB_DFFESR_Q_E": {
+          "hide_name": 0,
+          "bits": [ 72 ],
+          "attributes": {
+          }
+        },
         "io_ctrl_ins.rf_pin_state": {
           "hide_name": 0,
-          "bits": [ 115, 106, 110, 176, 175, 174, 173, 172 ],
+          "bits": [ 111, 97, 99, 176, 175, 174, 173, 172 ],
           "attributes": {
             "hdlname": "io_ctrl_ins rf_pin_state",
             "src": "top.v:128.12-156.5|io_ctrl.v:75.17-75.29"
@@ -28987,9 +28925,9 @@
             "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8"
           }
         },
-        "io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O": {
+        "io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 16, 47, 140, 141 ],
+          "bits": [ 119, 86, 120, 121 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -29012,7 +28950,7 @@
         },
         "io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 91, 173, 178 ],
+          "bits": [ 79, 173, 178 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -29020,18 +28958,10 @@
         },
         "io_ctrl_ins.rx_h_state_SB_DFFE_Q_E": {
           "hide_name": 0,
-          "bits": [ 90 ],
+          "bits": [ 78 ],
           "attributes": {
           }
         },
-        "io_ctrl_ins.rx_h_state_SB_LUT4_I1_O": {
-          "hide_name": 0,
-          "bits": [ 17, 47, 48, 49 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
         "io_ctrl_ins.tr_vc_1_b_state": {
           "hide_name": 0,
           "bits": [ 6 ],
@@ -29049,7 +28979,7 @@
         },
         "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O": {
           "hide_name": 0,
-          "bits": [ 128, 103, 129, 130 ],
+          "bits": [ 139, 131, 140, 141 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -29072,15 +29002,15 @@
         },
         "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 91, 175, 181 ],
+          "bits": [ 174, 79, 181 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "io_ctrl_ins.tr_vc_1_state_SB_LUT4_I1_O": {
+        "io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 135, 103, 136, 137 ],
+          "bits": [ 149, 86, 150, 151 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -29101,9 +29031,9 @@
             "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8"
           }
         },
-        "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O": {
+        "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O": {
           "hide_name": 0,
-          "bits": [ 123, 103, 124, 125 ],
+          "bits": [ 134, 131, 135, 136 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -29127,14 +29057,14 @@
           "hide_name": 0,
           "bits": [ 193 ],
           "attributes": {
-            "src": "top.v:192.9-192.19"
+            "src": "top.v:189.9-189.19"
           }
         },
         "lvds_clock_buf": {
           "hide_name": 0,
           "bits": [ 193 ],
           "attributes": {
-            "src": "top.v:193.9-193.23"
+            "src": "top.v:190.9-190.23"
           }
         },
         "lvds_rx_09_inst.i_ddr_clk": {
@@ -29142,7 +29072,7 @@
           "bits": [ 193 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst i_ddr_clk",
-            "src": "top.v:262.12-272.5|lvds_rx.v:4.29-4.38"
+            "src": "top.v:259.12-269.5|lvds_rx.v:4.29-4.38"
           }
         },
         "lvds_rx_09_inst.i_ddr_data": {
@@ -29150,31 +29080,31 @@
           "bits": [ 191, 192 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst i_ddr_data",
-            "src": "top.v:262.12-272.5|lvds_rx.v:5.29-5.39"
+            "src": "top.v:259.12-269.5|lvds_rx.v:5.29-5.39"
           }
         },
         "lvds_rx_09_inst.i_fifo_full": {
           "hide_name": 0,
-          "bits": [ 282 ],
+          "bits": [ 316 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst i_fifo_full",
-            "src": "top.v:262.12-272.5|lvds_rx.v:7.29-7.40"
+            "src": "top.v:259.12-269.5|lvds_rx.v:7.29-7.40"
           }
         },
         "lvds_rx_09_inst.i_reset": {
           "hide_name": 0,
-          "bits": [ 54 ],
+          "bits": [ 49 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst i_reset",
-            "src": "top.v:262.12-272.5|lvds_rx.v:3.29-3.36"
+            "src": "top.v:259.12-269.5|lvds_rx.v:3.29-3.36"
           }
         },
         "lvds_rx_09_inst.o_debug_state": {
           "hide_name": 0,
-          "bits": [ 273, 270 ],
+          "bits": [ 307, 304 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst o_debug_state",
-            "src": "top.v:262.12-272.5|lvds_rx.v:11.29-11.42"
+            "src": "top.v:259.12-269.5|lvds_rx.v:11.29-11.42"
           }
         },
         "lvds_rx_09_inst.o_fifo_data": {
@@ -29182,7 +29112,7 @@
           "bits": [ 246, 245, 242, 240, 238, 236, 234, 232, 230, 228, 226, 224, 220, 218, 216, 214, 212, 210, 208, 206, 204, 202, 258, 256, 254, 252, 250, 248, 244, 222, 200, 198 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst o_fifo_data",
-            "src": "top.v:262.12-272.5|lvds_rx.v:10.29-10.40"
+            "src": "top.v:259.12-269.5|lvds_rx.v:10.29-10.40"
           }
         },
         "lvds_rx_09_inst.o_fifo_push": {
@@ -29190,20 +29120,40 @@
           "bits": [ 260 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst o_fifo_push",
-            "src": "top.v:262.12-272.5|lvds_rx.v:9.29-9.40"
+            "src": "top.v:259.12-269.5|lvds_rx.v:9.29-9.40"
           }
         },
-        "lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_1_O": {
+        "lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2": {
           "hide_name": 0,
-          "bits": [ 262 ],
+          "bits": [ 260, 261, 262 ],
           "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "lvds_rx_09_inst.o_fifo_push_SB_LUT4_I3_O": {
+        "lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_1_I1": {
           "hide_name": 0,
-          "bits": [ 261 ],
+          "bits": [ "0", 284, 282, 280, 278, 276, 274, 272, 269 ],
           "attributes": {
-            "src": "top.v:277.17-288.5|complex_fifo.v:23.1-37.4"
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:274.17-285.5|complex_fifo.v:30.24-30.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
+          }
+        },
+        "lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I1": {
+          "hide_name": 0,
+          "bits": [ 919, 286, 290, 271, 265, 289, 288, 287, 269 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:274.17-285.5|complex_fifo.v:30.24-30.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27",
+            "unused_bits": "0 "
+          }
+        },
+        "lvds_rx_09_inst.o_fifo_push_SB_LUT4_I1_I2_SB_LUT4_O_I2": {
+          "hide_name": 0,
+          "bits": [ 264, 265, 266, 267 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
         "lvds_rx_09_inst.o_fifo_write_clk": {
@@ -29211,7 +29161,7 @@
           "bits": [ 193 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst o_fifo_write_clk",
-            "src": "top.v:262.12-272.5|lvds_rx.v:8.29-8.45"
+            "src": "top.v:259.12-269.5|lvds_rx.v:8.29-8.45"
           }
         },
         "lvds_rx_09_inst.r_data": {
@@ -29219,27 +29169,21 @@
           "bits": [ 241, 239, 237, 235, 233, 231, 229, 227, 225, 223, 219, 217, 215, 213, 211, 209, 207, 205, 203, 201, 257, 255, 253, 251, 249, 247, 243, 221, 199, 196, "x", "x" ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst r_data",
-            "src": "top.v:262.12-272.5|lvds_rx.v:27.17-27.23"
-          }
-        },
-        "lvds_rx_09_inst.r_data_SB_DFFESR_Q_E": {
-          "hide_name": 0,
-          "bits": [ 263 ],
-          "attributes": {
+            "src": "top.v:259.12-269.5|lvds_rx.v:27.17-27.23"
           }
         },
         "lvds_rx_09_inst.r_phase_count": {
           "hide_name": 0,
-          "bits": [ 267, 265, 923 ],
+          "bits": [ 301, 299, 920 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst r_phase_count",
-            "src": "top.v:262.12-272.5|lvds_rx.v:26.17-26.30",
+            "src": "top.v:259.12-269.5|lvds_rx.v:26.17-26.30",
             "unused_bits": "2"
           }
         },
         "lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 264 ],
+          "bits": [ 298 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -29247,69 +29191,69 @@
         },
         "lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 268 ],
+          "bits": [ 302 ],
           "attributes": {
           }
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         "lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E": {
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-        "lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O": {
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@@ -29320,57 +29264,55 @@
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-            "src": "top.v:262.12-272.5|lvds_rx.v:28.17-28.23"
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           "hide_name": 0,
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           "hide_name": 0,
-          "bits": [ 273, 270 ],
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-            "src": "top.v:262.12-272.5|lvds_rx.v:25.17-25.27"
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         "lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_D": {
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           "hide_name": 0,
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-        "lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I3": {
+        "lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 271, 273, 286 ],
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-        "lvds_rx_09_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I2": {
+        "lvds_rx_09_inst.r_state_if_SB_LUT4_I3_O": {
           "hide_name": 0,
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         "lvds_rx_24_inst.i_ddr_clk": {
@@ -29378,7 +29320,7 @@
           "bits": [ 193 ],
           "attributes": {
             "hdlname": "lvds_rx_24_inst i_ddr_clk",
-            "src": "top.v:290.12-299.5|lvds_rx.v:4.29-4.38"
+            "src": "top.v:287.12-296.5|lvds_rx.v:4.29-4.38"
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         "lvds_rx_24_inst.i_ddr_data": {
@@ -29386,72 +29328,47 @@
           "bits": [ 194, 195 ],
           "attributes": {
             "hdlname": "lvds_rx_24_inst i_ddr_data",
-            "src": "top.v:290.12-299.5|lvds_rx.v:5.29-5.39"
+            "src": "top.v:287.12-296.5|lvds_rx.v:5.29-5.39"
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         "lvds_rx_24_inst.i_fifo_full": {
           "hide_name": 0,
-          "bits": [ 401 ],
+          "bits": [ 407 ],
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-            "src": "top.v:290.12-299.5|lvds_rx.v:7.29-7.40"
+            "src": "top.v:287.12-296.5|lvds_rx.v:7.29-7.40"
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         "lvds_rx_24_inst.i_reset": {
           "hide_name": 0,
-          "bits": [ 54 ],
+          "bits": [ 49 ],
           "attributes": {
             "hdlname": "lvds_rx_24_inst i_reset",
-            "src": "top.v:290.12-299.5|lvds_rx.v:3.29-3.36"
+            "src": "top.v:287.12-296.5|lvds_rx.v:3.29-3.36"
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         "lvds_rx_24_inst.o_debug_state": {
           "hide_name": 0,
-          "bits": [ 392, 389 ],
+          "bits": [ 398, 395 ],
           "attributes": {
             "hdlname": "lvds_rx_24_inst o_debug_state",
-            "src": "top.v:290.12-299.5|lvds_rx.v:11.29-11.42"
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-            "src": "top.v:290.12-299.5|lvds_rx.v:10.29-10.40"
+            "src": "top.v:287.12-296.5|lvds_rx.v:10.29-10.40"
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         "lvds_rx_24_inst.o_fifo_push": {
           "hide_name": 0,
-          "bits": [ 352 ],
+          "bits": [ 385 ],
           "attributes": {
             "hdlname": "lvds_rx_24_inst o_fifo_push",
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-        "lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I0": {
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-          "bits": [ "0", 371, 369, 367, 365, 363, 361, 359, 353 ],
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-        "lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_I2": {
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-          "bits": [ 924, 378, 377, 376, 375, 374, 373, 355, 353 ],
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-        "lvds_rx_24_inst.o_fifo_push_SB_LUT4_I3_O": {
-          "hide_name": 0,
-          "bits": [ 600, 373, 356, 381 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+            "src": "top.v:287.12-296.5|lvds_rx.v:9.29-9.40"
           }
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         "lvds_rx_24_inst.o_fifo_write_clk": {
@@ -29459,35 +29376,35 @@
           "bits": [ 193 ],
           "attributes": {
             "hdlname": "lvds_rx_24_inst o_fifo_write_clk",
-            "src": "top.v:290.12-299.5|lvds_rx.v:8.29-8.45"
+            "src": "top.v:287.12-296.5|lvds_rx.v:8.29-8.45"
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         "lvds_rx_24_inst.r_data": {
           "hide_name": 0,
-          "bits": [ 333, 331, 329, 327, 325, 323, 321, 319, 317, 315, 311, 309, 307, 305, 303, 301, 299, 297, 295, 293, 349, 347, 345, 343, 341, 339, 335, 313, 291, 288, "x", "x" ],
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           "attributes": {
             "hdlname": "lvds_rx_24_inst r_data",
-            "src": "top.v:290.12-299.5|lvds_rx.v:27.17-27.23"
+            "src": "top.v:287.12-296.5|lvds_rx.v:27.17-27.23"
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         "lvds_rx_24_inst.r_data_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 382 ],
+          "bits": [ 388 ],
           "attributes": {
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         "lvds_rx_24_inst.r_phase_count": {
           "hide_name": 0,
-          "bits": [ 386, 384, 925 ],
+          "bits": [ 392, 390, 921 ],
           "attributes": {
             "hdlname": "lvds_rx_24_inst r_phase_count",
-            "src": "top.v:290.12-299.5|lvds_rx.v:26.17-26.30",
+            "src": "top.v:287.12-296.5|lvds_rx.v:26.17-26.30",
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           }
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         "lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 383 ],
+          "bits": [ 389 ],
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@@ -29495,47 +29412,47 @@
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         "lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 387 ],
+          "bits": [ 393 ],
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         "lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 388 ],
+          "bits": [ 394 ],
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         "lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E_SB_DFFESR_E_1_D": {
           "hide_name": 0,
-          "bits": [ 395 ],
+          "bits": [ 401 ],
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         "lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E_SB_DFFESR_E_1_Q": {
           "hide_name": 0,
-          "bits": [ 385, 391, 397 ],
+          "bits": [ 391, 397, 403 ],
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-            "src": "top.v:290.12-299.5|lvds_rx.v:78.42-78.59|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
+            "src": "top.v:287.12-296.5|lvds_rx.v:78.42-78.59|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
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           "hide_name": 0,
-          "bits": [ "1", 386, 396 ],
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+            "src": "top.v:287.12-296.5|lvds_rx.v:78.42-78.59|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
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           "hide_name": 0,
-          "bits": [ 393 ],
+          "bits": [ 399 ],
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         "lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFESR_Q_E_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 389, 195, 194, 398 ],
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@@ -29543,15 +29460,15 @@
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           "hide_name": 0,
-          "bits": [ 394, "0", "1", 396 ],
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+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
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         "lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 390, 54, 389, 392 ],
+          "bits": [ 395, 396, 49, 398 ],
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@@ -29559,55 +29476,63 @@
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           "hide_name": 0,
-          "bits": [ 289 ],
+          "bits": [ 322 ],
           "attributes": {
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         "lvds_rx_24_inst.r_push": {
           "hide_name": 0,
-          "bits": [ 351 ],
+          "bits": [ 384 ],
           "attributes": {
             "hdlname": "lvds_rx_24_inst r_push",
-            "src": "top.v:290.12-299.5|lvds_rx.v:28.17-28.23"
+            "src": "top.v:287.12-296.5|lvds_rx.v:28.17-28.23"
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         "lvds_rx_24_inst.r_push_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 399 ],
+          "bits": [ 405 ],
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         "lvds_rx_24_inst.r_push_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 400 ],
+          "bits": [ 406 ],
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         },
         "lvds_rx_24_inst.r_state_if": {
           "hide_name": 0,
-          "bits": [ 392, 389 ],
+          "bits": [ 398, 395 ],
           "attributes": {
             "hdlname": "lvds_rx_24_inst r_state_if",
-            "src": "top.v:290.12-299.5|lvds_rx.v:25.17-25.27"
+            "src": "top.v:287.12-296.5|lvds_rx.v:25.17-25.27"
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         },
         "lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 404, 402 ],
+          "bits": [ 410, 408 ],
           "attributes": {
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-            "src": "top.v:290.12-299.5|lvds_rx.v:58.13-94.20|lvds_rx.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22"
+            "src": "top.v:287.12-296.5|lvds_rx.v:58.13-94.20|lvds_rx.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22"
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         "lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 403 ],
+          "bits": [ 409 ],
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         "lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 392, 390, 54, 405 ],
+          "bits": [ 396, 398, 411 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "lvds_rx_24_inst.r_state_if_SB_DFFESR_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I2": {
+          "hide_name": 0,
+          "bits": [ 395, 398, 412, 49 ],
           "attributes": {
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@@ -29671,7 +29596,7 @@
         },
         "o_miso_$_TBUF__Y_E": {
           "hide_name": 0,
-          "bits": [ 407 ],
+          "bits": [ 69 ],
           "attributes": {
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@@ -29754,16 +29679,16 @@
         },
         "r_counter": {
           "hide_name": 0,
-          "bits": [ 410 ],
+          "bits": [ 70 ],
           "attributes": {
             "src": "top.v:65.16-65.25"
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         "r_counter_SB_DFF_Q_D": {
           "hide_name": 0,
-          "bits": [ 409 ],
+          "bits": [ 415 ],
           "attributes": {
-            "src": "top.v:172.4-175.7"
+            "src": "top.v:172.4-183.7"
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         "r_reset": {
@@ -29775,148 +29700,163 @@
         },
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         "r_tx_data_SB_DFFESR_Q_5_D": {
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           }
         },
+        "r_tx_data_SB_DFFESR_Q_5_D_SB_LUT4_O_I2": {
+          "hide_name": 0,
+          "bits": [ 430, 118 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
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         "r_tx_data_SB_DFFESR_Q_D": {
           "hide_name": 0,
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         "r_tx_data_SB_DFFE_Q_D": {
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-          "bits": [ 429, 938, 939, 940, 941, 942, 943, 944 ],
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         },
         "r_tx_data_SB_DFFE_Q_E": {
           "hide_name": 0,
-          "bits": [ 412 ],
+          "bits": [ 417 ],
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         },
         "rx_09_fifo.empty_o": {
           "hide_name": 0,
-          "bits": [ 432 ],
+          "bits": [ 438 ],
           "attributes": {
             "hdlname": "rx_09_fifo empty_o",
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         "rx_09_fifo.empty_o_SB_DFFSS_Q_D": {
           "hide_name": 0,
-          "bits": [ 431 ],
+          "bits": [ 437 ],
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         },
         "rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0": {
           "hide_name": 0,
-          "bits": [ 433, 434, 432, 435 ],
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             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
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         },
-        "rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0": {
+        "rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3": {
           "hide_name": 0,
-          "bits": [ 439, 440, 441, 442 ],
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             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
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         },
-        "rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1": {
+        "rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I0": {
           "hide_name": 0,
-          "bits": [ "0", 452, 467, 466, 465, 464, 463, 462, 461, 436 ],
+          "bits": [ "0", 458, 456, 455, 454, 453, 452, 451, 450, 447 ],
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             "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:277.17-288.5|complex_fifo.v:49.25-49.36|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
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+          }
+        },
+        "rx_09_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I2": {
+          "hide_name": 0,
+          "bits": [ 268, 269, 270, 271 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_09_fifo.empty_o_SB_LUT4_I0_I1": {
+          "hide_name": 0,
+          "bits": [ 438, 460, 461, 462 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_09_fifo.empty_o_SB_LUT4_I0_O": {
+          "hide_name": 0,
+          "bits": [ 442, 283, 443 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
         "rx_09_fifo.full_o": {
           "hide_name": 0,
-          "bits": [ 282 ],
+          "bits": [ 316 ],
           "attributes": {
             "hdlname": "rx_09_fifo full_o",
-            "src": "top.v:277.17-288.5|complex_fifo.v:16.19-16.25"
+            "src": "top.v:274.17-285.5|complex_fifo.v:16.19-16.25"
           }
         },
         "rx_09_fifo.full_o_SB_DFFSR_Q_D": {
           "hide_name": 0,
-          "bits": [ 468 ],
+          "bits": [ 463 ],
           "attributes": {
           }
         },
-        "rx_09_fifo.full_o_SB_LUT4_I2_I3": {
+        "rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0": {
           "hide_name": 0,
-          "bits": [ 451, 452, 282, 472 ],
+          "bits": [ 464, 263, 465, 466 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "rx_09_fifo.full_o_SB_LUT4_I2_O": {
+        "rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 469, 470, 471, 260 ],
+          "bits": [ 467, 442, 468, 469 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I0": {
+        "rx_09_fifo.full_o_SB_LUT4_I3_I2": {
           "hide_name": 0,
-          "bits": [ "0", 453, 486, 485, 484, 483, 482, 481, 478 ],
+          "bits": [ 485, 484, 472, 467, 473, 470, 471, 478, 474 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:277.17-288.5|complex_fifo.v:30.24-30.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
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           }
         },
-        "rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I2": {
+        "rx_09_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 945, 490, 489, 479, 488, 487, 492, 491, 478 ],
+          "bits": [ "0", 459, 483, 482, 481, 480, 479, 477, 476 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:277.17-288.5|complex_fifo.v:30.24-30.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27",
-            "unused_bits": "0 "
+            "src": "top.v:274.17-285.5|complex_fifo.v:29.24-29.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
           }
         },
-        "rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3": {
+        "rx_09_fifo.full_o_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 478, 455, 479, 480 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0": {
-          "hide_name": 0,
-          "bits": [ 493, 494, 495, 496 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "rx_09_fifo.full_o_SB_LUT4_I2_O_SB_LUT4_O_I1": {
-          "hide_name": 0,
-          "bits": [ 475, 476, 477 ],
+          "bits": [ 486, 487, 268, 475 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -29924,21 +29864,28 @@
         },
         "rx_09_fifo.mem_i.0.0.0_RCLKE": {
           "hide_name": 0,
-          "bits": [ 503 ],
+          "bits": [ 488 ],
           "attributes": {
           }
         },
         "rx_09_fifo.mem_i.0.0.0_RDATA": {
           "hide_name": 0,
-          "bits": [ 504, 505, 506, 507, 508, 509, 510, 511, 512, 513, 514, 515, 516, 517, 68, 518 ],
+          "bits": [ 489, 490, 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, 63, 501, 502, 503 ],
           "attributes": {
             "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23",
             "unused_bits": "1 3 5 7 9 11 13 15"
           }
         },
+        "rx_09_fifo.mem_i.0.0.0_WCLKE": {
+          "hide_name": 0,
+          "bits": [ 295 ],
+          "attributes": {
+            "src": "top.v:274.17-285.5|complex_fifo.v:23.1-37.4"
+          }
+        },
         "rx_09_fifo.mem_i.1.0.0_RDATA": {
           "hide_name": 0,
-          "bits": [ 519, 520, 521, 522, 523, 524, 525, 526, 527, 528, 529, 530, 531, 532, 63, 533 ],
+          "bits": [ 504, 505, 506, 507, 508, 509, 510, 511, 512, 513, 514, 515, 58, 516, 517, 518 ],
           "attributes": {
             "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23",
             "unused_bits": "1 3 5 7 9 11 13 15"
@@ -29946,7 +29893,7 @@
         },
         "rx_09_fifo.mem_q.0.0.0_RDATA": {
           "hide_name": 0,
-          "bits": [ 534, 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 69, 548 ],
+          "bits": [ 519, 520, 521, 522, 523, 524, 525, 526, 527, 528, 529, 530, 64, 531, 532, 533 ],
           "attributes": {
             "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23",
             "unused_bits": "1 3 5 7 9 11 13 15"
@@ -29954,7 +29901,7 @@
         },
         "rx_09_fifo.mem_q.1.0.0_RDATA": {
           "hide_name": 0,
-          "bits": [ 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 64, 563 ],
+          "bits": [ 534, 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 59, 546, 547, 548 ],
           "attributes": {
             "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23",
             "unused_bits": "1 3 5 7 9 11 13 15"
@@ -29962,80 +29909,70 @@
         },
         "rx_09_fifo.rd_addr": {
           "hide_name": 0,
-          "bits": [ 452, 454, 457, 447, 455, 449, 459, 444, 445 ],
+          "bits": [ 458, 294, 457, 442, 270, 264, 291, 292, 293 ],
           "attributes": {
             "hdlname": "rx_09_fifo rd_addr",
-            "src": "top.v:277.17-288.5|complex_fifo.v:21.22-21.29"
+            "src": "top.v:274.17-285.5|complex_fifo.v:21.22-21.29"
           }
         },
         "rx_09_fifo.rd_addr_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 573, 572, 571, 570, 569, 568, 567, 566, 564 ],
+          "bits": [ 558, 557, 556, 555, 554, 553, 552, 551, 549 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:277.17-288.5|complex_fifo.v:48.24-48.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
+            "src": "top.v:274.17-285.5|complex_fifo.v:48.24-48.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
           }
         },
         "rx_09_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ "0", 452, 580, 579, 578, 577, 576, 575, 574 ],
+          "bits": [ "0", 458, 565, 564, 563, 562, 561, 560, 559 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:277.17-288.5|complex_fifo.v:48.24-48.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
+            "src": "top.v:274.17-285.5|complex_fifo.v:48.24-48.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
           }
         },
         "rx_09_fifo.rd_addr_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 565 ],
+          "bits": [ 550 ],
           "attributes": {
           }
         },
         "rx_09_fifo.rd_clk_i": {
           "hide_name": 0,
-          "bits": [ 82 ],
+          "bits": [ 70 ],
           "attributes": {
             "hdlname": "rx_09_fifo rd_clk_i",
-            "src": "top.v:277.17-288.5|complex_fifo.v:12.31-12.39"
+            "src": "top.v:274.17-285.5|complex_fifo.v:12.31-12.39"
           }
         },
         "rx_09_fifo.rd_data_o": {
           "hide_name": 0,
-          "bits": [ 519, 521, 523, 525, 527, 529, 531, 63, 504, 506, 508, 510, 512, 514, 516, 68, 549, 551, 553, 555, 557, 559, 561, 64, 534, 536, 538, 540, 542, 544, 546, 69 ],
+          "bits": [ 504, 506, 508, 510, 512, 514, 58, 517, 489, 491, 493, 495, 497, 499, 63, 502, 534, 536, 538, 540, 542, 544, 59, 547, 519, 521, 523, 525, 527, 529, 64, 532 ],
           "attributes": {
             "hdlname": "rx_09_fifo rd_data_o",
-            "src": "top.v:277.17-288.5|complex_fifo.v:14.35-14.44"
+            "src": "top.v:274.17-285.5|complex_fifo.v:14.35-14.44"
           }
         },
         "rx_09_fifo.rd_rst_i": {
           "hide_name": 0,
-          "bits": [ 54 ],
+          "bits": [ 49 ],
           "attributes": {
             "hdlname": "rx_09_fifo rd_rst_i",
-            "src": "top.v:277.17-288.5|complex_fifo.v:11.31-11.39"
+            "src": "top.v:274.17-285.5|complex_fifo.v:11.31-11.39"
           }
         },
         "rx_09_fifo.wr_addr": {
           "hide_name": 0,
-          "bits": [ 451, 453, 458, 448, 456, 450, 460, 443, 446 ],
+          "bits": [ 459, 284, 285, 283, 281, 279, 277, 275, 273 ],
           "attributes": {
             "hdlname": "rx_09_fifo wr_addr",
-            "src": "top.v:277.17-288.5|complex_fifo.v:20.22-20.29"
+            "src": "top.v:274.17-285.5|complex_fifo.v:20.22-20.29"
           }
         },
-        "rx_09_fifo.wr_addr_SB_DFFESR_Q_D": {
+        "rx_09_fifo.wr_addr_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 581, 499, 473, 500, 497, 501, 498, 502, 474 ],
+          "bits": [ 296 ],
           "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:277.17-288.5|complex_fifo.v:29.24-29.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
-          }
-        },
-        "rx_09_fifo.wr_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3": {
-          "hide_name": 0,
-          "bits": [ "0", 451, 588, 587, 586, 585, 584, 583, 582 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:277.17-288.5|complex_fifo.v:29.24-29.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
           }
         },
         "rx_09_fifo.wr_clk_i": {
@@ -30043,7 +29980,7 @@
           "bits": [ 193 ],
           "attributes": {
             "hdlname": "rx_09_fifo wr_clk_i",
-            "src": "top.v:277.17-288.5|complex_fifo.v:7.31-7.39"
+            "src": "top.v:274.17-285.5|complex_fifo.v:7.31-7.39"
           }
         },
         "rx_09_fifo.wr_data_i": {
@@ -30051,7 +29988,7 @@
           "bits": [ 246, 245, 242, 240, 238, 236, 234, 232, 230, 228, 226, 224, 220, 218, 216, 214, 212, 210, 208, 206, 204, 202, 258, 256, 254, 252, 250, 248, 244, 222, 200, 198 ],
           "attributes": {
             "hdlname": "rx_09_fifo wr_data_i",
-            "src": "top.v:277.17-288.5|complex_fifo.v:9.35-9.44"
+            "src": "top.v:274.17-285.5|complex_fifo.v:9.35-9.44"
           }
         },
         "rx_09_fifo.wr_en_i": {
@@ -30059,66 +29996,50 @@
           "bits": [ 260 ],
           "attributes": {
             "hdlname": "rx_09_fifo wr_en_i",
-            "src": "top.v:277.17-288.5|complex_fifo.v:8.31-8.38"
+            "src": "top.v:274.17-285.5|complex_fifo.v:8.31-8.38"
           }
         },
         "rx_09_fifo.wr_rst_i": {
           "hide_name": 0,
-          "bits": [ 54 ],
+          "bits": [ 49 ],
           "attributes": {
             "hdlname": "rx_09_fifo wr_rst_i",
-            "src": "top.v:277.17-288.5|complex_fifo.v:6.31-6.39"
+            "src": "top.v:274.17-285.5|complex_fifo.v:6.31-6.39"
           }
         },
         "rx_24_fifo.empty_o": {
           "hide_name": 0,
-          "bits": [ 590 ],
+          "bits": [ 567 ],
           "attributes": {
             "hdlname": "rx_24_fifo empty_o",
-            "src": "top.v:301.17-312.5|complex_fifo.v:17.19-17.26"
+            "src": "top.v:298.17-309.5|complex_fifo.v:17.19-17.26"
           }
         },
         "rx_24_fifo.empty_o_SB_DFFSS_Q_D": {
           "hide_name": 0,
-          "bits": [ 589 ],
+          "bits": [ 566 ],
           "attributes": {
           }
         },
-        "rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I1": {
+        "rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0": {
           "hide_name": 0,
-          "bits": [ 591, 592, 593 ],
+          "bits": [ 568, 569, 567, 570 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I0": {
+        "rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_2_I1": {
           "hide_name": 0,
-          "bits": [ "0", 596, 607, 605, 604, 602, 601, 599, 598, 594 ],
+          "bits": [ "0", 594, 592, 591, 589, 587, 586, 584, 582, 579 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:301.17-312.5|complex_fifo.v:49.25-49.36|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
+            "src": "top.v:298.17-309.5|complex_fifo.v:49.25-49.36|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
           }
         },
-        "rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3": {
+        "rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0": {
           "hide_name": 0,
-          "bits": [ 594, 595, 596, 597 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "rx_24_fifo.empty_o_SB_LUT4_I2_I3": {
-          "hide_name": 0,
-          "bits": [ 608, 372, 590, 612 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "rx_24_fifo.empty_o_SB_LUT4_I2_I3_SB_LUT4_O_I0": {
-          "hide_name": 0,
-          "bits": [ 613, 614, 615, 616 ],
+          "bits": [ 571, 572, 573, 574 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30126,53 +30047,70 @@
         },
         "rx_24_fifo.full_o": {
           "hide_name": 0,
-          "bits": [ 401 ],
+          "bits": [ 407 ],
           "attributes": {
             "hdlname": "rx_24_fifo full_o",
-            "src": "top.v:301.17-312.5|complex_fifo.v:16.19-16.25"
+            "src": "top.v:298.17-309.5|complex_fifo.v:16.19-16.25"
           }
         },
         "rx_24_fifo.full_o_SB_DFFSR_Q_D": {
           "hide_name": 0,
-          "bits": [ 617 ],
+          "bits": [ 603 ],
           "attributes": {
           }
         },
-        "rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0": {
-          "hide_name": 0,
-          "bits": [ 618, 619, 620, 621 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "rx_24_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0": {
-          "hide_name": 0,
-          "bits": [ 624, 625, 626, 627 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
         "rx_24_fifo.full_o_SB_LUT4_I3_I2": {
           "hide_name": 0,
-          "bits": [ 642, 622, 641, 623, 638, 628, 635, 633, 631 ],
+          "bits": [ 623, 622, 621, 619, 608, 616, 614, 612, 610 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:301.17-312.5|complex_fifo.v:29.24-29.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
+            "src": "top.v:298.17-309.5|complex_fifo.v:29.24-29.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
           }
         },
         "rx_24_fifo.full_o_SB_LUT4_I3_I2_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ "0", 595, 640, 639, 637, 636, 634, 632, 630 ],
+          "bits": [ "0", 601, 620, 618, 617, 615, 613, 611, 609 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:301.17-312.5|complex_fifo.v:29.24-29.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
+            "src": "top.v:298.17-309.5|complex_fifo.v:29.24-29.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
           }
         },
         "rx_24_fifo.full_o_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 643, 644, 645, 629 ],
+          "bits": [ 604, 605, 606, 607 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_1_I0": {
+          "hide_name": 0,
+          "bits": [ 628, 629, 630, 631 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I0": {
+          "hide_name": 0,
+          "bits": [ "0", 602, 645, 644, 643, 642, 641, 640, 638 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:298.17-309.5|complex_fifo.v:30.24-30.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
+          }
+        },
+        "rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_2_I2": {
+          "hide_name": 0,
+          "bits": [ 941, 632, 636, 633, 637, 639, 634, 635, 638 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:298.17-309.5|complex_fifo.v:30.24-30.35|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27",
+            "unused_bits": "0 "
+          }
+        },
+        "rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_O_I0": {
+          "hide_name": 0,
+          "bits": [ 624, 625, 626, 627 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30186,7 +30124,7 @@
         },
         "rx_24_fifo.mem_i.0.0.0_RDATA": {
           "hide_name": 0,
-          "bits": [ 647, 648, 649, 650, 651, 652, 653, 654, 655, 656, 657, 658, 659, 660, 59, 661 ],
+          "bits": [ 647, 648, 649, 650, 651, 652, 653, 654, 655, 656, 657, 658, 54, 659, 660, 661 ],
           "attributes": {
             "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23",
             "unused_bits": "1 3 5 7 9 11 13 15"
@@ -30194,14 +30132,14 @@
         },
         "rx_24_fifo.mem_i.0.0.0_WCLKE": {
           "hide_name": 0,
-          "bits": [ 357 ],
+          "bits": [ 386 ],
           "attributes": {
-            "src": "top.v:301.17-312.5|complex_fifo.v:23.1-37.4"
+            "src": "top.v:298.17-309.5|complex_fifo.v:23.1-37.4"
           }
         },
         "rx_24_fifo.mem_i.1.0.0_RDATA": {
           "hide_name": 0,
-          "bits": [ 662, 663, 664, 665, 666, 667, 668, 669, 670, 671, 672, 673, 674, 675, 58, 676 ],
+          "bits": [ 662, 663, 664, 665, 666, 667, 668, 669, 670, 671, 672, 673, 53, 674, 675, 676 ],
           "attributes": {
             "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23",
             "unused_bits": "1 3 5 7 9 11 13 15"
@@ -30209,7 +30147,7 @@
         },
         "rx_24_fifo.mem_q.0.0.0_RDATA": {
           "hide_name": 0,
-          "bits": [ 677, 678, 679, 680, 681, 682, 683, 684, 685, 686, 687, 688, 689, 690, 72, 691 ],
+          "bits": [ 677, 678, 679, 680, 681, 682, 683, 684, 685, 686, 687, 688, 67, 689, 690, 691 ],
           "attributes": {
             "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23",
             "unused_bits": "1 3 5 7 9 11 13 15"
@@ -30217,7 +30155,7 @@
         },
         "rx_24_fifo.mem_q.1.0.0_RDATA": {
           "hide_name": 0,
-          "bits": [ 692, 693, 694, 695, 696, 697, 698, 699, 700, 701, 702, 703, 704, 705, 71, 706 ],
+          "bits": [ 692, 693, 694, 695, 696, 697, 698, 699, 700, 701, 702, 703, 66, 704, 705, 706 ],
           "attributes": {
             "src": "/usr/local/bin/../share/yosys/ice40/brams_map.v:255.14-255.23",
             "unused_bits": "1 3 5 7 9 11 13 15"
@@ -30225,10 +30163,10 @@
         },
         "rx_24_fifo.rd_addr": {
           "hide_name": 0,
-          "bits": [ 596, 609, 608, 606, 380, 603, 379, 600, 354 ],
+          "bits": [ 594, 595, 593, 575, 590, 588, 577, 585, 583 ],
           "attributes": {
             "hdlname": "rx_24_fifo rd_addr",
-            "src": "top.v:301.17-312.5|complex_fifo.v:21.22-21.29"
+            "src": "top.v:298.17-309.5|complex_fifo.v:21.22-21.29"
           }
         },
         "rx_24_fifo.rd_addr_SB_DFFESR_Q_D": {
@@ -30236,15 +30174,15 @@
           "bits": [ 716, 715, 714, 713, 712, 711, 710, 709, 707 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:301.17-312.5|complex_fifo.v:48.24-48.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
+            "src": "top.v:298.17-309.5|complex_fifo.v:48.24-48.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
           }
         },
         "rx_24_fifo.rd_addr_SB_DFFESR_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ "0", 596, 723, 722, 721, 720, 719, 718, 717 ],
+          "bits": [ "0", 594, 723, 722, 721, 720, 719, 718, 717 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:301.17-312.5|complex_fifo.v:48.24-48.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
+            "src": "top.v:298.17-309.5|complex_fifo.v:48.24-48.38|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
           }
         },
         "rx_24_fifo.rd_addr_SB_DFFESR_Q_E": {
@@ -30255,39 +30193,39 @@
         },
         "rx_24_fifo.rd_clk_i": {
           "hide_name": 0,
-          "bits": [ 82 ],
+          "bits": [ 70 ],
           "attributes": {
             "hdlname": "rx_24_fifo rd_clk_i",
-            "src": "top.v:301.17-312.5|complex_fifo.v:12.31-12.39"
+            "src": "top.v:298.17-309.5|complex_fifo.v:12.31-12.39"
           }
         },
         "rx_24_fifo.rd_data_o": {
           "hide_name": 0,
-          "bits": [ 662, 664, 666, 668, 670, 672, 674, 58, 647, 649, 651, 653, 655, 657, 659, 59, 692, 694, 696, 698, 700, 702, 704, 71, 677, 679, 681, 683, 685, 687, 689, 72 ],
+          "bits": [ 662, 664, 666, 668, 670, 672, 53, 675, 647, 649, 651, 653, 655, 657, 54, 660, 692, 694, 696, 698, 700, 702, 66, 705, 677, 679, 681, 683, 685, 687, 67, 690 ],
           "attributes": {
             "hdlname": "rx_24_fifo rd_data_o",
-            "src": "top.v:301.17-312.5|complex_fifo.v:14.35-14.44"
+            "src": "top.v:298.17-309.5|complex_fifo.v:14.35-14.44"
           }
         },
         "rx_24_fifo.rd_rst_i": {
           "hide_name": 0,
-          "bits": [ 54 ],
+          "bits": [ 49 ],
           "attributes": {
             "hdlname": "rx_24_fifo rd_rst_i",
-            "src": "top.v:301.17-312.5|complex_fifo.v:11.31-11.39"
+            "src": "top.v:298.17-309.5|complex_fifo.v:11.31-11.39"
           }
         },
         "rx_24_fifo.wr_addr": {
           "hide_name": 0,
-          "bits": [ 595, 371, 372, 370, 368, 366, 364, 362, 360 ],
+          "bits": [ 601, 602, 600, 576, 598, 599, 578, 597, 596 ],
           "attributes": {
             "hdlname": "rx_24_fifo wr_addr",
-            "src": "top.v:301.17-312.5|complex_fifo.v:20.22-20.29"
+            "src": "top.v:298.17-309.5|complex_fifo.v:20.22-20.29"
           }
         },
         "rx_24_fifo.wr_addr_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 358 ],
+          "bits": [ 387 ],
           "attributes": {
           }
         },
@@ -30296,31 +30234,31 @@
           "bits": [ 193 ],
           "attributes": {
             "hdlname": "rx_24_fifo wr_clk_i",
-            "src": "top.v:301.17-312.5|complex_fifo.v:7.31-7.39"
+            "src": "top.v:298.17-309.5|complex_fifo.v:7.31-7.39"
           }
         },
         "rx_24_fifo.wr_data_i": {
           "hide_name": 0,
-          "bits": [ 338, 337, 334, 332, 330, 328, 326, 324, 322, 320, 318, 316, 312, 310, 308, 306, 304, 302, 300, 298, 296, 294, 350, 348, 346, 344, 342, 340, 336, 314, 292, 290 ],
+          "bits": [ 371, 370, 367, 365, 363, 361, 359, 357, 355, 353, 351, 349, 345, 343, 341, 339, 337, 335, 333, 331, 329, 327, 383, 381, 379, 377, 375, 373, 369, 347, 325, 323 ],
           "attributes": {
             "hdlname": "rx_24_fifo wr_data_i",
-            "src": "top.v:301.17-312.5|complex_fifo.v:9.35-9.44"
+            "src": "top.v:298.17-309.5|complex_fifo.v:9.35-9.44"
           }
         },
         "rx_24_fifo.wr_en_i": {
           "hide_name": 0,
-          "bits": [ 352 ],
+          "bits": [ 385 ],
           "attributes": {
             "hdlname": "rx_24_fifo wr_en_i",
-            "src": "top.v:301.17-312.5|complex_fifo.v:8.31-8.38"
+            "src": "top.v:298.17-309.5|complex_fifo.v:8.31-8.38"
           }
         },
         "rx_24_fifo.wr_rst_i": {
           "hide_name": 0,
-          "bits": [ 54 ],
+          "bits": [ 49 ],
           "attributes": {
             "hdlname": "rx_24_fifo wr_rst_i",
-            "src": "top.v:301.17-312.5|complex_fifo.v:6.31-6.39"
+            "src": "top.v:298.17-309.5|complex_fifo.v:6.31-6.39"
           }
         },
         "smi_ctrl_ins.i_cs": {
@@ -30328,95 +30266,103 @@
           "bits": [ 725 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_cs",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:9.29-9.33"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:9.29-9.33"
+          }
+        },
+        "smi_ctrl_ins.i_cs_SB_LUT4_I2_O": {
+          "hide_name": 0,
+          "bits": [ 105, 726 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
         "smi_ctrl_ins.i_data_in": {
           "hide_name": 0,
-          "bits": [ 86, 83, 163, 162, 161, 160, 158, 155 ],
+          "bits": [ 74, 71, 165, 164, 163, 161, 159, 156 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_data_in",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:7.29-7.38"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:7.29-7.38"
           }
         },
         "smi_ctrl_ins.i_fetch_cmd": {
           "hide_name": 0,
-          "bits": [ 825 ],
+          "bits": [ 89 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_fetch_cmd",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:10.29-10.40"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:10.29-10.40"
           }
         },
         "smi_ctrl_ins.i_fifo_09_empty": {
           "hide_name": 0,
-          "bits": [ 432 ],
+          "bits": [ 438 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_fifo_09_empty",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:17.29-17.44"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:17.29-17.44"
           }
         },
         "smi_ctrl_ins.i_fifo_09_full": {
           "hide_name": 0,
-          "bits": [ 282 ],
+          "bits": [ 316 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_fifo_09_full",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:16.29-16.43"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:16.29-16.43"
           }
         },
         "smi_ctrl_ins.i_fifo_09_pulled_data": {
           "hide_name": 0,
-          "bits": [ 519, 521, 523, 525, 527, 529, 531, 63, 504, 506, 508, 510, 512, 514, 516, 68, 549, 551, 553, 555, 557, 559, 561, 64, 534, 536, 538, 540, 542, 544, 546, 69 ],
+          "bits": [ 504, 506, 508, 510, 512, 514, 58, 517, 489, 491, 493, 495, 497, 499, 63, 502, 534, 536, 538, 540, 542, 544, 59, 547, 519, 521, 523, 525, 527, 529, 64, 532 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_fifo_09_pulled_data",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:15.29-15.50"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:15.29-15.50"
           }
         },
         "smi_ctrl_ins.i_fifo_24_empty": {
           "hide_name": 0,
-          "bits": [ 590 ],
+          "bits": [ 567 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_fifo_24_empty",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:23.29-23.44"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:23.29-23.44"
           }
         },
         "smi_ctrl_ins.i_fifo_24_full": {
           "hide_name": 0,
-          "bits": [ 401 ],
+          "bits": [ 407 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_fifo_24_full",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:22.29-22.43"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:22.29-22.43"
           }
         },
         "smi_ctrl_ins.i_fifo_24_pulled_data": {
           "hide_name": 0,
-          "bits": [ 662, 664, 666, 668, 670, 672, 674, 58, 647, 649, 651, 653, 655, 657, 659, 59, 692, 694, 696, 698, 700, 702, 704, 71, 677, 679, 681, 683, 685, 687, 689, 72 ],
+          "bits": [ 662, 664, 666, 668, 670, 672, 53, 675, 647, 649, 651, 653, 655, 657, 54, 660, 692, 694, 696, 698, 700, 702, 66, 705, 677, 679, 681, 683, 685, 687, 67, 690 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_fifo_24_pulled_data",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:21.29-21.50"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:21.29-21.50"
           }
         },
         "smi_ctrl_ins.i_ioc": {
           "hide_name": 0,
-          "bits": [ 51, 53, 832, 831, 830 ],
+          "bits": [ 101, 104, 108, 107, 106 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_ioc",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:6.29-6.34"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:6.29-6.34"
           }
         },
         "smi_ctrl_ins.i_load_cmd": {
           "hide_name": 0,
-          "bits": [ 834 ],
+          "bits": [ 90 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_load_cmd",
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+            "src": "top.v:311.13-342.5|smi_ctrl.v:11.29-11.39"
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         "smi_ctrl_ins.i_reset": {
           "hide_name": 0,
-          "bits": [ 54 ],
+          "bits": [ 49 ],
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             "hdlname": "smi_ctrl_ins i_reset",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:3.29-3.36"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:3.29-3.36"
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         "smi_ctrl_ins.i_smi_a": {
@@ -30424,7 +30370,7 @@
           "bits": [ 28, 29, 30 ],
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             "hdlname": "smi_ctrl_ins i_smi_a",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:26.29-26.36"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:26.29-26.36"
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         "smi_ctrl_ins.i_smi_data_in": {
@@ -30432,7 +30378,7 @@
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             "hdlname": "smi_ctrl_ins i_smi_data_in",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:30.29-30.42"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:30.29-30.42"
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         "smi_ctrl_ins.i_smi_soe_se": {
@@ -30440,7 +30386,7 @@
           "bits": [ 31 ],
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             "hdlname": "smi_ctrl_ins i_smi_soe_se",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:27.29-27.41"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:27.29-27.41"
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         "smi_ctrl_ins.i_smi_swe_srw": {
@@ -30448,7 +30394,7 @@
           "bits": [ 32 ],
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             "hdlname": "smi_ctrl_ins i_smi_swe_srw",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:28.29-28.42",
+            "src": "top.v:311.13-342.5|smi_ctrl.v:28.29-28.42",
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@@ -30457,78 +30403,78 @@
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             "hdlname": "smi_ctrl_ins i_smi_test",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:34.29-34.39"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:34.29-34.39"
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         "smi_ctrl_ins.i_sys_clk": {
           "hide_name": 0,
-          "bits": [ 82 ],
+          "bits": [ 70 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_sys_clk",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:4.29-4.38"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:4.29-4.38"
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         "smi_ctrl_ins.int_cnt_09": {
           "hide_name": 0,
-          "bits": [ "1", "1", "1", 65, 66 ],
+          "bits": [ "1", "1", "1", 60, 61 ],
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             "hdlname": "smi_ctrl_ins int_cnt_09",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:92.15-92.25"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:92.15-92.25"
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         "smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_D": {
           "hide_name": 0,
-          "bits": [ 729, 727 ],
+          "bits": [ 730, 728 ],
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-            "src": "top.v:314.13-345.5|smi_ctrl.v:122.35-122.49|/usr/local/bin/../share/yosys/techmap.v:270.26-270.27"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:122.35-122.49|/usr/local/bin/../share/yosys/techmap.v:270.26-270.27"
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         "smi_ctrl_ins.int_cnt_09_SB_DFFNESS_Q_E": {
           "hide_name": 0,
-          "bits": [ 728 ],
+          "bits": [ 729 ],
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         "smi_ctrl_ins.int_cnt_24": {
           "hide_name": 0,
-          "bits": [ "1", "1", "1", 73, 60 ],
+          "bits": [ "1", "1", "1", 68, 55 ],
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             "hdlname": "smi_ctrl_ins int_cnt_24",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:93.15-93.25"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:93.15-93.25"
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         },
         "smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_D": {
           "hide_name": 0,
-          "bits": [ 731, 730 ],
+          "bits": [ 732, 731 ],
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-            "src": "top.v:314.13-345.5|smi_ctrl.v:131.35-131.49|/usr/local/bin/../share/yosys/techmap.v:270.26-270.27"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:131.35-131.49|/usr/local/bin/../share/yosys/techmap.v:270.26-270.27"
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         "smi_ctrl_ins.int_cnt_24_SB_DFFNESS_Q_E": {
           "hide_name": 0,
-          "bits": [ 55 ],
+          "bits": [ 50 ],
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         "smi_ctrl_ins.o_data_out": {
           "hide_name": 0,
-          "bits": [ 736, 735, 734, 733, "0", "0", "0", "0" ],
+          "bits": [ 737, 736, 735, 734, "0", "0", "0", "0" ],
           "attributes": {
             "hdlname": "smi_ctrl_ins o_data_out",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:8.29-8.39"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:8.29-8.39"
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         "smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E": {
           "hide_name": 0,
-          "bits": [ 732 ],
+          "bits": [ 733 ],
           "attributes": {
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         },
-        "smi_ctrl_ins.o_data_out_SB_LUT4_I2_I3": {
+        "smi_ctrl_ins.o_data_out_SB_LUT4_I0_2_O": {
           "hide_name": 0,
-          "bits": [ 737, 734, 739 ],
+          "bits": [ 433, 434 ],
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             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30539,7 +30485,7 @@
           "bits": [ 33, 190, 189, 188, 187, 186, 185, 184 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins o_smi_data_out",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:29.29-29.43"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:29.29-29.43"
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         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D": {
@@ -30548,31 +30494,15 @@
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-        "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0": {
-          "hide_name": 0,
-          "bits": [ 742, 743, 744, 57 ],
-          "attributes": {
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-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_1_D_SB_LUT4_O_I0_SB_LUT4_O_I3": {
-          "hide_name": 0,
-          "bits": [ 674, 659, 60, 745 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D": {
           "hide_name": 0,
-          "bits": [ 746 ],
+          "bits": [ 742 ],
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         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0": {
           "hide_name": 0,
-          "bits": [ 747, 748, 749, 57 ],
+          "bits": [ 743, 744, 745, 52 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30580,7 +30510,7 @@
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         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 672, 657, 60, 750 ],
+          "bits": [ 672, 657, 55, 746 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30588,13 +30518,13 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D": {
           "hide_name": 0,
-          "bits": [ 751 ],
+          "bits": [ 747 ],
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         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0": {
           "hide_name": 0,
-          "bits": [ 752, 753, 754, 57 ],
+          "bits": [ 748, 749, 750, 52 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30602,7 +30532,7 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 670, 655, 60, 755 ],
+          "bits": [ 670, 655, 55, 751 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30610,13 +30540,13 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D": {
           "hide_name": 0,
-          "bits": [ 756 ],
+          "bits": [ 752 ],
           "attributes": {
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         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0": {
           "hide_name": 0,
-          "bits": [ 757, 758, 759, 57 ],
+          "bits": [ 753, 754, 755, 52 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30624,7 +30554,7 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_4_D_SB_LUT4_O_I0_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 668, 653, 60, 760 ],
+          "bits": [ 668, 653, 55, 756 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30632,13 +30562,13 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D": {
           "hide_name": 0,
-          "bits": [ 761 ],
+          "bits": [ 757 ],
           "attributes": {
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         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0": {
           "hide_name": 0,
-          "bits": [ 762, 763, 764, 57 ],
+          "bits": [ 758, 759, 760, 52 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30646,7 +30576,7 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 666, 651, 60, 765 ],
+          "bits": [ 666, 651, 55, 761 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30654,13 +30584,13 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D": {
           "hide_name": 0,
-          "bits": [ 766 ],
+          "bits": [ 762 ],
           "attributes": {
           }
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0": {
           "hide_name": 0,
-          "bits": [ 767, 768, 769, 57 ],
+          "bits": [ 763, 764, 765, 52 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30668,7 +30598,7 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 664, 649, 60, 770 ],
+          "bits": [ 664, 649, 55, 766 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30676,13 +30606,13 @@
         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D": {
           "hide_name": 0,
-          "bits": [ 771 ],
+          "bits": [ 767 ],
           "attributes": {
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         },
         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0": {
           "hide_name": 0,
-          "bits": [ 772, 773, 774, 57 ],
+          "bits": [ 768, 769, 770, 52 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30690,7 +30620,7 @@
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         "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 662, 647, 60, 775 ],
+          "bits": [ 662, 647, 55, 771 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30702,12 +30632,28 @@
           "attributes": {
           }
         },
+        "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0": {
+          "hide_name": 0,
+          "bits": [ 772, 773, 774, 52 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "smi_ctrl_ins.o_smi_data_out_SB_DFFNE_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3": {
+          "hide_name": 0,
+          "bits": [ 675, 660, 55, 775 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
         "smi_ctrl_ins.o_smi_read_req": {
           "hide_name": 0,
-          "bits": [ 408 ],
+          "bits": [ 414 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins o_smi_read_req",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:31.29-31.43"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:31.29-31.43"
           }
         },
         "smi_ctrl_ins.o_smi_write_req": {
@@ -30715,7 +30661,7 @@
           "bits": [ "x" ],
           "attributes": {
             "hdlname": "smi_ctrl_ins o_smi_write_req",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:32.29-32.44"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:32.29-32.44"
           }
         },
         "smi_ctrl_ins.o_smi_writing": {
@@ -30723,7 +30669,7 @@
           "bits": [ 30 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins o_smi_writing",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:33.29-33.42"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:33.29-33.42"
           }
         },
         "smi_ctrl_ins.r_fifo_09_pull": {
@@ -30731,7 +30677,7 @@
           "bits": [ 776 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins r_fifo_09_pull",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:94.9-94.23"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:94.9-94.23"
           }
         },
         "smi_ctrl_ins.r_fifo_09_pull_1": {
@@ -30739,12 +30685,12 @@
           "bits": [ 777 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins r_fifo_09_pull_1",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:95.9-95.25"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:95.9-95.25"
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         "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O": {
           "hide_name": 0,
-          "bits": [ 779, 780, 778, 781 ],
+          "bits": [ 779, 778, 780, 781 ],
           "attributes": {
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@@ -30752,108 +30698,116 @@
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         "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I0_O": {
           "hide_name": 0,
-          "bits": [ 436, 437, 438 ],
+          "bits": [ 447, 285, 448, 449 ],
           "attributes": {
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         },
-        "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_LUT4_O_I1": {
+        "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I0": {
           "hide_name": 0,
-          "bits": [ 446, 782, 445, 461 ],
+          "bits": [ 558, 444, 448, 785, 786, 784, 783, 782, 446, 447 ],
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-            "src": "top.v:277.17-288.5|complex_fifo.v:49.25-49.36|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
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-        "smi_ctrl_ins.r_fifo_09_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1": {
-          "hide_name": 0,
-          "bits": [ 573, 786, 787, 784, 783, 785, 788, 789, 946, 436 ],
-          "attributes": {
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-            "src": "top.v:277.17-288.5|complex_fifo.v:49.25-49.36|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27",
-            "unused_bits": "8"
+            "src": "top.v:274.17-285.5|complex_fifo.v:49.25-49.36|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
           }
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         "smi_ctrl_ins.r_fifo_24_pull": {
           "hide_name": 0,
-          "bits": [ 791 ],
+          "bits": [ 788 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins r_fifo_24_pull",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:97.9-97.23"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:97.9-97.23"
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         "smi_ctrl_ins.r_fifo_24_pull_1": {
           "hide_name": 0,
-          "bits": [ 792 ],
+          "bits": [ 789 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins r_fifo_24_pull_1",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:98.9-98.25"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:98.9-98.25"
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           "hide_name": 0,
-          "bits": [ 793, 794, 795, 796 ],
+          "bits": [ 791, 792, 790, 793 ],
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-        "smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1": {
+        "smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I0_O": {
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-          "bits": [ 716, 610, 611, 799, 800, 797, 798, 801, 802, 594 ],
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+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_LUT4_O_I1": {
+          "hide_name": 0,
+          "bits": [ 596, 794, 583, 582 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:298.17-309.5|complex_fifo.v:49.25-49.36|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "smi_ctrl_ins.r_fifo_24_pull_1_SB_LUT4_I1_O_SB_LUT4_O_I1": {
+          "hide_name": 0,
+          "bits": [ 716, 942, 797, 799, 800, 798, 795, 796, 943, 579 ],
+          "attributes": {
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+            "src": "top.v:298.17-309.5|complex_fifo.v:49.25-49.36|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27",
+            "unused_bits": "1 8"
           }
         },
         "smi_ctrl_ins.soe_and_reset": {
           "hide_name": 0,
-          "bits": [ 726 ],
+          "bits": [ 727 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins soe_and_reset",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:103.10-103.23"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:103.10-103.23"
           }
         },
         "smi_ctrl_ins.w_fifo_09_pull_trigger": {
           "hide_name": 0,
-          "bits": [ 790 ],
+          "bits": [ 787 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins w_fifo_09_pull_trigger",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:96.10-96.32"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:96.10-96.32"
           }
         },
         "smi_ctrl_ins.w_fifo_09_pull_trigger_SB_DFFNE_Q_D": {
           "hide_name": 0,
-          "bits": [ 804 ],
+          "bits": [ 802 ],
           "attributes": {
-            "src": "top.v:314.13-345.5|smi_ctrl.v:114.39-114.79"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:114.39-114.79"
           }
         },
         "smi_ctrl_ins.w_fifo_24_pull_trigger": {
           "hide_name": 0,
-          "bits": [ 803 ],
+          "bits": [ 801 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins w_fifo_24_pull_trigger",
-            "src": "top.v:314.13-345.5|smi_ctrl.v:99.10-99.32"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:99.10-99.32"
           }
         },
         "smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_D": {
           "hide_name": 0,
-          "bits": [ 806 ],
+          "bits": [ 804 ],
           "attributes": {
-            "src": "top.v:314.13-345.5|smi_ctrl.v:115.39-115.79"
+            "src": "top.v:311.13-342.5|smi_ctrl.v:115.39-115.79"
           }
         },
         "smi_ctrl_ins.w_fifo_24_pull_trigger_SB_DFFNE_Q_E": {
           "hide_name": 0,
-          "bits": [ 805 ],
+          "bits": [ 803 ],
           "attributes": {
           }
         },
         "spi_if_ins.i_data_out": {
           "hide_name": 0,
-          "bits": [ 430, 413, 416, 418, 420, 422, 424, 427 ],
+          "bits": [ 436, 418, 421, 423, 425, 427, 429, 432 ],
           "attributes": {
             "hdlname": "spi_if_ins i_data_out",
             "src": "top.v:92.11-108.5|spi_if.v:10.29-10.39"
@@ -30861,7 +30815,7 @@
         },
         "spi_if_ins.i_rst_b": {
           "hide_name": 0,
-          "bits": [ 54 ],
+          "bits": [ 49 ],
           "attributes": {
             "hdlname": "spi_if_ins i_rst_b",
             "src": "top.v:92.11-108.5|spi_if.v:5.29-5.36"
@@ -30893,7 +30847,7 @@
         },
         "spi_if_ins.i_sys_clk": {
           "hide_name": 0,
-          "bits": [ 82 ],
+          "bits": [ 70 ],
           "attributes": {
             "hdlname": "spi_if_ins i_sys_clk",
             "src": "top.v:92.11-108.5|spi_if.v:6.29-6.38"
@@ -30901,7 +30855,7 @@
         },
         "spi_if_ins.o_cs": {
           "hide_name": 0,
-          "bits": [ 811, 94, 725, 808 ],
+          "bits": [ 809, 82, 725, 806 ],
           "attributes": {
             "hdlname": "spi_if_ins o_cs",
             "src": "top.v:92.11-108.5|spi_if.v:11.29-11.33"
@@ -30909,7 +30863,7 @@
         },
         "spi_if_ins.o_cs_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ "0", "0", "0", 807, "0", "0", 724, "0", "0", 92, "0", "0" ],
+          "bits": [ "0", "0", "0", 805, "0", "0", 724, "0", "0", 80, "0", "0" ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:92.11-108.5|spi_if.v:65.21-70.28|spi_if.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:583.28-583.35"
@@ -30917,7 +30871,7 @@
         },
         "spi_if_ins.o_cs_SB_DFFESR_Q_R": {
           "hide_name": 0,
-          "bits": [ 95, 947, 948, 949 ],
+          "bits": [ 83, 944, 945, 946 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:92.11-108.5|spi_if.v:65.21-70.28|spi_if.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22",
@@ -30926,7 +30880,7 @@
         },
         "spi_if_ins.o_cs_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 736, 737, 425, 153 ],
+          "bits": [ 737, 738, 430, 153 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30934,7 +30888,7 @@
         },
         "spi_if_ins.o_cs_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 905, 414, 428, 738 ],
+          "bits": [ 902, 419, 433, 739 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30942,7 +30896,7 @@
         },
         "spi_if_ins.o_data_in": {
           "hide_name": 0,
-          "bits": [ 86, 83, 163, 162, 161, 160, 158, 155 ],
+          "bits": [ 74, 71, 165, 164, 163, 161, 159, 156 ],
           "attributes": {
             "hdlname": "spi_if_ins o_data_in",
             "src": "top.v:92.11-108.5|spi_if.v:9.29-9.38"
@@ -30950,13 +30904,13 @@
         },
         "spi_if_ins.o_data_in_SB_DFFE_Q_E": {
           "hide_name": 0,
-          "bits": [ 813 ],
+          "bits": [ 811 ],
           "attributes": {
           }
         },
         "spi_if_ins.o_fetch_cmd": {
           "hide_name": 0,
-          "bits": [ 825 ],
+          "bits": [ 89 ],
           "attributes": {
             "hdlname": "spi_if_ins o_fetch_cmd",
             "src": "top.v:92.11-108.5|spi_if.v:12.29-12.40"
@@ -30964,19 +30918,19 @@
         },
         "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 823 ],
+          "bits": [ 821 ],
           "attributes": {
           }
         },
         "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 824 ],
+          "bits": [ 822 ],
           "attributes": {
           }
         },
         "spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 143, 148, 144 ],
+          "bits": [ 102, 105, 155 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -30984,67 +30938,43 @@
         },
         "spi_if_ins.o_ioc": {
           "hide_name": 0,
-          "bits": [ 51, 53, 832, 831, 830 ],
+          "bits": [ 101, 104, 108, 107, 106 ],
           "attributes": {
             "hdlname": "spi_if_ins o_ioc",
             "src": "top.v:92.11-108.5|spi_if.v:8.29-8.34"
           }
         },
+        "spi_if_ins.o_ioc_SB_DFFE_Q_E": {
+          "hide_name": 0,
+          "bits": [ 81 ],
+          "attributes": {
+          }
+        },
         "spi_if_ins.o_load_cmd": {
           "hide_name": 0,
-          "bits": [ 834 ],
+          "bits": [ 90 ],
           "attributes": {
             "hdlname": "spi_if_ins o_load_cmd",
             "src": "top.v:92.11-108.5|spi_if.v:13.29-13.39"
           }
         },
-        "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D": {
-          "hide_name": 0,
-          "bits": [ 827, 820 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O": {
-          "hide_name": 0,
-          "bits": [ 819, 812, 828, 829 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I2_O_SB_LUT4_I3_O": {
-          "hide_name": 0,
-          "bits": [ 820, 835, 93 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
         "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 833 ],
+          "bits": [ 826 ],
           "attributes": {
           }
         },
+        "spi_if_ins.o_load_cmd_SB_LUT4_I3_1_O": {
+          "hide_name": 0,
+          "bits": [ 170, 49 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
         "spi_if_ins.o_load_cmd_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 54, 99 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O": {
-          "hide_name": 0,
-          "bits": [ 84 ],
-          "attributes": {
-          }
-        },
-        "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O": {
-          "hide_name": 0,
-          "bits": [ 164, 108, 51 ],
+          "bits": [ 131, 166 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -31052,7 +30982,7 @@
         },
         "spi_if_ins.o_spi_miso": {
           "hide_name": 0,
-          "bits": [ 406 ],
+          "bits": [ 413 ],
           "attributes": {
             "hdlname": "spi_if_ins o_spi_miso",
             "src": "top.v:92.11-108.5|spi_if.v:17.29-17.39"
@@ -31060,7 +30990,7 @@
         },
         "spi_if_ins.r_tx_byte": {
           "hide_name": 0,
-          "bits": [ 844, 843, 842, 841, 840, 839, 838, 837 ],
+          "bits": [ 835, 834, 833, 832, 831, 830, 829, 828 ],
           "attributes": {
             "hdlname": "spi_if_ins r_tx_byte",
             "src": "top.v:92.11-108.5|spi_if.v:32.17-32.26"
@@ -31068,7 +30998,7 @@
         },
         "spi_if_ins.r_tx_data_valid": {
           "hide_name": 0,
-          "bits": [ 847 ],
+          "bits": [ 838 ],
           "attributes": {
             "hdlname": "spi_if_ins r_tx_data_valid",
             "src": "top.v:92.11-108.5|spi_if.v:31.17-31.32"
@@ -31076,7 +31006,7 @@
         },
         "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 820, 845 ],
+          "bits": [ 818, 836 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -31084,62 +31014,40 @@
         },
         "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 836 ],
+          "bits": [ 827 ],
           "attributes": {
           }
         },
         "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 846 ],
+          "bits": [ 837 ],
           "attributes": {
           }
         },
-        "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O": {
-          "hide_name": 0,
-          "bits": [ 837, 854, 849 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O_SB_LUT4_O_I0": {
-          "hide_name": 0,
-          "bits": [ 850, 851, 852, 853 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_1_O_SB_LUT4_O_I0_SB_LUT4_O_I3": {
-          "hide_name": 0,
-          "bits": [ 855, 856, 857, 858 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_I2": {
-          "hide_name": 0,
-          "bits": [ 45, 866, 81 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
         "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 848 ],
+          "bits": [ 839 ],
           "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
         "spi_if_ins.spi.SCKr": {
           "hide_name": 0,
-          "bits": [ 867, 75, 74 ],
+          "bits": [ 842, 840, 841 ],
           "attributes": {
             "hdlname": "spi_if_ins spi SCKr",
             "src": "top.v:92.11-108.5|spi_slave.v:80.13-80.17|spi_if.v:42.15-54.6"
           }
         },
+        "spi_if_ins.spi.SCKr_SB_LUT4_I0_O": {
+          "hide_name": 0,
+          "bits": [ 858, 845, 839 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
         "spi_if_ins.spi.i_spi_cs_b": {
           "hide_name": 0,
           "bits": [ 45 ],
@@ -31166,7 +31074,7 @@
         },
         "spi_if_ins.spi.i_sys_clk": {
           "hide_name": 0,
-          "bits": [ 82 ],
+          "bits": [ 70 ],
           "attributes": {
             "hdlname": "spi_if_ins spi i_sys_clk",
             "src": "top.v:92.11-108.5|spi_slave.v:5.23-5.32|spi_if.v:42.15-54.6"
@@ -31174,7 +31082,7 @@
         },
         "spi_if_ins.spi.i_tx_byte": {
           "hide_name": 0,
-          "bits": [ 844, 843, 842, 841, 840, 839, 838, 837 ],
+          "bits": [ 835, 834, 833, 832, 831, 830, 829, 828 ],
           "attributes": {
             "hdlname": "spi_if_ins spi i_tx_byte",
             "src": "top.v:92.11-108.5|spi_slave.v:9.23-9.32|spi_if.v:42.15-54.6"
@@ -31182,7 +31090,7 @@
         },
         "spi_if_ins.spi.i_tx_data_valid": {
           "hide_name": 0,
-          "bits": [ 847 ],
+          "bits": [ 838 ],
           "attributes": {
             "hdlname": "spi_if_ins spi i_tx_data_valid",
             "src": "top.v:92.11-108.5|spi_slave.v:8.23-8.38|spi_if.v:42.15-54.6"
@@ -31190,7 +31098,7 @@
         },
         "spi_if_ins.spi.o_rx_byte": {
           "hide_name": 0,
-          "bits": [ 818, 817, 816, 815, 814, 810, 809, 812 ],
+          "bits": [ 816, 815, 814, 813, 812, 808, 807, 810 ],
           "attributes": {
             "hdlname": "spi_if_ins spi o_rx_byte",
             "src": "top.v:92.11-108.5|spi_slave.v:7.23-7.32|spi_if.v:42.15-54.6"
@@ -31198,7 +31106,7 @@
         },
         "spi_if_ins.spi.o_rx_data_valid": {
           "hide_name": 0,
-          "bits": [ 820 ],
+          "bits": [ 818 ],
           "attributes": {
             "hdlname": "spi_if_ins spi o_rx_data_valid",
             "src": "top.v:92.11-108.5|spi_slave.v:6.23-6.38|spi_if.v:42.15-54.6"
@@ -31206,7 +31114,7 @@
         },
         "spi_if_ins.spi.o_spi_miso": {
           "hide_name": 0,
-          "bits": [ 406 ],
+          "bits": [ 413 ],
           "attributes": {
             "hdlname": "spi_if_ins spi o_spi_miso",
             "src": "top.v:92.11-108.5|spi_slave.v:13.23-13.33|spi_if.v:42.15-54.6"
@@ -31214,14 +31122,44 @@
         },
         "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 877 ],
+          "bits": [ 856 ],
           "attributes": {
             "src": "top.v:92.11-108.5|spi_slave.v:87.3-104.6|spi_if.v:42.15-54.6"
           }
         },
+        "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2": {
+          "hide_name": 0,
+          "bits": [ 828, 857, 839 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1": {
+          "hide_name": 0,
+          "bits": [ 858, 859, 860, 861 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_2_I0": {
+          "hide_name": 0,
+          "bits": [ 866, 867, 843, 858 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E": {
+          "hide_name": 0,
+          "bits": [ 846 ],
+          "attributes": {
+          }
+        },
         "spi_if_ins.spi.r2_rx_done": {
           "hide_name": 0,
-          "bits": [ 879 ],
+          "bits": [ 873 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r2_rx_done",
             "src": "top.v:92.11-108.5|spi_slave.v:22.7-22.17|spi_if.v:42.15-54.6"
@@ -31229,7 +31167,7 @@
         },
         "spi_if_ins.spi.r3_rx_done": {
           "hide_name": 0,
-          "bits": [ 880 ],
+          "bits": [ 874 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r3_rx_done",
             "src": "top.v:92.11-108.5|spi_slave.v:23.7-23.17|spi_if.v:42.15-54.6"
@@ -31237,74 +31175,82 @@
         },
         "spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 869 ],
+          "bits": [ 848 ],
           "attributes": {
             "src": "top.v:92.11-108.5|spi_slave.v:66.3-78.6|spi_if.v:42.15-54.6"
           }
         },
         "spi_if_ins.spi.r_rx_bit_count": {
           "hide_name": 0,
-          "bits": [ 77, 79, 78 ],
+          "bits": [ 880, 878, 876 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_rx_bit_count",
             "src": "top.v:92.11-108.5|spi_slave.v:17.13-17.27|spi_if.v:42.15-54.6"
           }
         },
-        "spi_if_ins.spi.r_rx_bit_count_SB_DFFESR_Q_2_D": {
+        "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_2_D": {
           "hide_name": 0,
-          "bits": [ 883, 79, 78 ],
+          "bits": [ 879, 878, 876 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:92.11-108.5|spi_slave.v:52.25-52.43|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.23-33.24"
+            "src": "top.v:92.11-108.5|spi_slave.v:34.25-34.43|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.23-33.24"
           }
         },
-        "spi_if_ins.spi.r_rx_bit_count_SB_DFFESR_Q_D": {
+        "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D": {
           "hide_name": 0,
-          "bits": [ 883, 882, 881 ],
+          "bits": [ 879, 877, 875 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:92.11-108.5|spi_slave.v:52.25-52.43|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
+            "src": "top.v:92.11-108.5|spi_slave.v:34.25-34.43|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
           }
         },
-        "spi_if_ins.spi.r_rx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3": {
+        "spi_if_ins.spi.r_rx_bit_count_SB_DFFSR_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ "0", 77, 884 ],
+          "bits": [ "0", 880, 881 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:92.11-108.5|spi_slave.v:52.25-52.43|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
+            "src": "top.v:92.11-108.5|spi_slave.v:34.25-34.43|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
           }
         },
         "spi_if_ins.spi.r_rx_byte": {
           "hide_name": 0,
-          "bits": [ 876, 875, 874, 873, 872, 871, 870, 868 ],
+          "bits": [ 855, 854, 853, 852, 851, 850, 849, 847 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_rx_byte",
             "src": "top.v:92.11-108.5|spi_slave.v:20.13-20.22|spi_if.v:42.15-54.6"
           }
         },
-        "spi_if_ins.spi.r_rx_byte_SB_DFFE_Q_E": {
-          "hide_name": 0,
-          "bits": [ 886 ],
-          "attributes": {
-          }
-        },
         "spi_if_ins.spi.r_rx_done": {
           "hide_name": 0,
-          "bits": [ 878 ],
+          "bits": [ 872 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_rx_done",
             "src": "top.v:92.11-108.5|spi_slave.v:21.7-21.16|spi_if.v:42.15-54.6"
           }
         },
+        "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D": {
+          "hide_name": 0,
+          "bits": [ 45, 890 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_D_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 883 ],
+          "attributes": {
+          }
+        },
         "spi_if_ins.spi.r_rx_done_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 893 ],
+          "bits": [ 891 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.r_temp_rx_byte": {
           "hide_name": 0,
-          "bits": [ 892, 891, 890, 889, 888, 887, 885, "x" ],
+          "bits": [ 889, 888, 887, 886, 885, 884, 882, "x" ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_temp_rx_byte",
             "src": "top.v:92.11-108.5|spi_slave.v:19.13-19.27|spi_if.v:42.15-54.6"
@@ -31312,7 +31258,7 @@
         },
         "spi_if_ins.spi.r_tx_bit_count": {
           "hide_name": 0,
-          "bits": [ 857, 853, 861 ],
+          "bits": [ 843, 858, 844 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_tx_bit_count",
             "src": "top.v:92.11-108.5|spi_slave.v:18.13-18.27|spi_if.v:42.15-54.6"
@@ -31320,7 +31266,7 @@
         },
         "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 894, 898, 897 ],
+          "bits": [ 892, 896, 895 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:92.11-108.5|spi_slave.v:95.27-95.45|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
@@ -31328,7 +31274,7 @@
         },
         "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ "1", 857, 896 ],
+          "bits": [ "1", 843, 894 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:92.11-108.5|spi_slave.v:95.27-95.45|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
@@ -31336,13 +31282,13 @@
         },
         "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R": {
           "hide_name": 0,
-          "bits": [ 895 ],
+          "bits": [ 893 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.r_tx_byte": {
           "hide_name": 0,
-          "bits": [ 855, 864, 859, 862, 856, 865, 860, 863 ],
+          "bits": [ 864, 862, 868, 870, 865, 863, 869, 871 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_tx_byte",
             "src": "top.v:92.11-108.5|spi_slave.v:24.13-24.22|spi_if.v:42.15-54.6"
@@ -31350,37 +31296,21 @@
         },
         "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 899 ],
+          "bits": [ 897 ],
           "attributes": {
           }
         },
-        "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E_SB_LUT4_O_I2": {
-          "hide_name": 0,
-          "bits": [ 853, 900, 849 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
         "spi_if_ins.state_if": {
           "hide_name": 0,
-          "bits": [ 821, 822, 819 ],
+          "bits": [ 819, 820, 817 ],
           "attributes": {
             "hdlname": "spi_if_ins state_if",
             "src": "top.v:92.11-108.5|spi_if.v:28.17-28.25"
           }
         },
-        "spi_if_ins.state_if_SB_DFFESR_Q_1_D": {
-          "hide_name": 0,
-          "bits": [ 835, 820 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
         "spi_if_ins.state_if_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 901, 812, 835, 820 ],
+          "bits": [ 898, 810, 900, 818 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -31388,26 +31318,27 @@
         },
         "spi_if_ins.state_if_SB_DFFESR_Q_R": {
           "hide_name": 0,
-          "bits": [ 826 ],
+          "bits": [ 823 ],
           "attributes": {
           }
         },
         "spi_if_ins.state_if_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 903 ],
+          "bits": [ 824, 825, 818 ],
           "attributes": {
-            "src": "top.v:92.11-108.5|spi_if.v:56.5-111.8"
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
         "spi_if_ins.state_if_SB_DFFE_Q_E": {
           "hide_name": 0,
-          "bits": [ 902 ],
+          "bits": [ 899 ],
           "attributes": {
           }
         },
         "spi_if_ins.w_rx_data": {
           "hide_name": 0,
-          "bits": [ 818, 817, 816, 815, 814, 810, 809, 812 ],
+          "bits": [ 816, 815, 814, 813, 812, 808, 807, 810 ],
           "attributes": {
             "hdlname": "spi_if_ins w_rx_data",
             "src": "top.v:92.11-108.5|spi_if.v:30.17-30.26"
@@ -31415,7 +31346,7 @@
         },
         "spi_if_ins.w_rx_data_valid": {
           "hide_name": 0,
-          "bits": [ 820 ],
+          "bits": [ 818 ],
           "attributes": {
             "hdlname": "spi_if_ins w_rx_data_valid",
             "src": "top.v:92.11-108.5|spi_if.v:29.17-29.32"
@@ -31423,7 +31354,7 @@
         },
         "sys_ctrl_ins.i_cs": {
           "hide_name": 0,
-          "bits": [ 811 ],
+          "bits": [ 809 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_cs",
             "src": "top.v:113.13-126.5|sys_ctrl.v:9.29-9.33"
@@ -31431,7 +31362,7 @@
         },
         "sys_ctrl_ins.i_data_in": {
           "hide_name": 0,
-          "bits": [ 86, 83, 163, 162, 161, 160, 158, 155 ],
+          "bits": [ 74, 71, 165, 164, 163, 161, 159, 156 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_data_in",
             "src": "top.v:113.13-126.5|sys_ctrl.v:7.29-7.38"
@@ -31447,7 +31378,7 @@
         },
         "sys_ctrl_ins.i_fetch_cmd": {
           "hide_name": 0,
-          "bits": [ 825 ],
+          "bits": [ 89 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_fetch_cmd",
             "src": "top.v:113.13-126.5|sys_ctrl.v:10.29-10.40"
@@ -31455,7 +31386,7 @@
         },
         "sys_ctrl_ins.i_ioc": {
           "hide_name": 0,
-          "bits": [ 51, 53, 832, 831, 830 ],
+          "bits": [ 101, 104, 108, 107, 106 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_ioc",
             "src": "top.v:113.13-126.5|sys_ctrl.v:6.29-6.34"
@@ -31463,7 +31394,7 @@
         },
         "sys_ctrl_ins.i_load_cmd": {
           "hide_name": 0,
-          "bits": [ 834 ],
+          "bits": [ 90 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_load_cmd",
             "src": "top.v:113.13-126.5|sys_ctrl.v:11.29-11.39"
@@ -31479,7 +31410,7 @@
         },
         "sys_ctrl_ins.i_sys_clk": {
           "hide_name": 0,
-          "bits": [ 82 ],
+          "bits": [ 70 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_sys_clk",
             "src": "top.v:113.13-126.5|sys_ctrl.v:4.29-4.38"
@@ -31487,7 +31418,7 @@
         },
         "sys_ctrl_ins.o_data_out": {
           "hide_name": 0,
-          "bits": [ 905, "0", "0", "0", "0", "0", "0", "0" ],
+          "bits": [ 902, "0", "0", "0", "0", "0", "0", "0" ],
           "attributes": {
             "hdlname": "sys_ctrl_ins o_data_out",
             "src": "top.v:113.13-126.5|sys_ctrl.v:8.29-8.39"
@@ -31495,21 +31426,13 @@
         },
         "sys_ctrl_ins.o_data_out_SB_DFFE_Q_E": {
           "hide_name": 0,
-          "bits": [ 904 ],
+          "bits": [ 901 ],
           "attributes": {
           }
         },
         "sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1": {
           "hide_name": 0,
-          "bits": [ 53, 52 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I1_SB_LUT4_I3_O": {
-          "hide_name": 0,
-          "bits": [ 103, 104, 97, 85 ],
+          "bits": [ 105, 104, 101 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -31517,7 +31440,7 @@
         },
         "sys_ctrl_ins.o_soft_reset": {
           "hide_name": 0,
-          "bits": [ 54 ],
+          "bits": [ 49 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins o_soft_reset",
             "src": "top.v:113.13-126.5|sys_ctrl.v:13.29-13.41"
@@ -31525,13 +31448,13 @@
         },
         "sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E": {
           "hide_name": 0,
-          "bits": [ 906 ],
+          "bits": [ 903 ],
           "attributes": {
           }
         },
         "sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S": {
           "hide_name": 0,
-          "bits": [ 907 ],
+          "bits": [ 904 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:113.13-126.5|sys_ctrl.v:72.17-72.36|/usr/local/bin/../share/yosys/cmp2lut.v:24.22-24.23"
@@ -31539,7 +31462,7 @@
         },
         "sys_ctrl_ins.reset_cmd": {
           "hide_name": 0,
-          "bits": [ 908 ],
+          "bits": [ 905 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins reset_cmd",
             "src": "top.v:113.13-126.5|sys_ctrl.v:35.9-35.18"
@@ -31547,33 +31470,19 @@
         },
         "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 913 ],
-          "attributes": {
-          }
-        },
-        "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1": {
-          "hide_name": 0,
-          "bits": [ 915, 164 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I2_O": {
-          "hide_name": 0,
-          "bits": [ 165 ],
+          "bits": [ 910 ],
           "attributes": {
           }
         },
         "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R": {
           "hide_name": 0,
-          "bits": [ 914 ],
+          "bits": [ 911 ],
           "attributes": {
           }
         },
         "sys_ctrl_ins.reset_count": {
           "hide_name": 0,
-          "bits": [ 912, 910, 911, 909 ],
+          "bits": [ 909, 907, 908, 906 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins reset_count",
             "src": "top.v:113.13-126.5|sys_ctrl.v:34.15-34.26"
@@ -31581,31 +31490,31 @@
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 918 ],
+          "bits": [ 914 ],
           "attributes": {
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_2_D": {
           "hide_name": 0,
-          "bits": [ 920 ],
+          "bits": [ 916 ],
           "attributes": {
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_3_D": {
           "hide_name": 0,
-          "bits": [ 921 ],
+          "bits": [ 917 ],
           "attributes": {
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 917 ],
+          "bits": [ 913 ],
           "attributes": {
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ "0", 912, 919, 922 ],
+          "bits": [ "0", 909, 915, 918 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:113.13-126.5|sys_ctrl.v:73.32-73.50|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
@@ -31613,41 +31522,41 @@
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 916 ],
+          "bits": [ 912 ],
           "attributes": {
           }
         },
         "w_clock_sys": {
           "hide_name": 0,
-          "bits": [ 82 ],
+          "bits": [ 70 ],
           "attributes": {
             "src": "top.v:67.16-67.27"
           }
         },
         "w_cs": {
           "hide_name": 0,
-          "bits": [ 811, 94, 725, 808 ],
+          "bits": [ 809, 82, 725, 806 ],
           "attributes": {
             "src": "top.v:71.16-71.20"
           }
         },
         "w_fetch": {
           "hide_name": 0,
-          "bits": [ 825 ],
+          "bits": [ 89 ],
           "attributes": {
             "src": "top.v:72.16-72.23"
           }
         },
         "w_ioc": {
           "hide_name": 0,
-          "bits": [ 51, 53, 832, 831, 830 ],
+          "bits": [ 101, 104, 108, 107, 106 ],
           "attributes": {
             "src": "top.v:68.16-68.21"
           }
         },
         "w_load": {
           "hide_name": 0,
-          "bits": [ 834 ],
+          "bits": [ 90 ],
           "attributes": {
             "src": "top.v:73.16-73.22"
           }
@@ -31656,117 +31565,117 @@
           "hide_name": 0,
           "bits": [ 191 ],
           "attributes": {
-            "src": "top.v:241.9-241.24"
+            "src": "top.v:238.9-238.24"
           }
         },
         "w_lvds_rx_09_d1": {
           "hide_name": 0,
           "bits": [ 192 ],
           "attributes": {
-            "src": "top.v:242.9-242.24"
+            "src": "top.v:239.9-239.24"
           }
         },
         "w_lvds_rx_24_d0": {
           "hide_name": 0,
           "bits": [ 194 ],
           "attributes": {
-            "src": "top.v:243.9-243.24"
+            "src": "top.v:240.9-240.24"
           }
         },
         "w_lvds_rx_24_d1": {
           "hide_name": 0,
           "bits": [ 195 ],
           "attributes": {
-            "src": "top.v:244.9-244.24"
+            "src": "top.v:241.9-241.24"
           }
         },
         "w_rx_09_fifo_data": {
           "hide_name": 0,
           "bits": [ 246, 245, 242, 240, 238, 236, 234, 232, 230, 228, 226, 224, 220, 218, 216, 214, 212, 210, 208, 206, 204, 202, 258, 256, 254, 252, 250, 248, 244, 222, 200, 198 ],
           "attributes": {
-            "src": "top.v:250.16-250.33"
+            "src": "top.v:247.16-247.33"
           }
         },
         "w_rx_09_fifo_empty": {
           "hide_name": 0,
-          "bits": [ 432 ],
+          "bits": [ 438 ],
           "attributes": {
-            "src": "top.v:247.9-247.27"
+            "src": "top.v:244.9-244.27"
           }
         },
         "w_rx_09_fifo_full": {
           "hide_name": 0,
-          "bits": [ 282 ],
+          "bits": [ 316 ],
           "attributes": {
-            "src": "top.v:246.9-246.26"
+            "src": "top.v:243.9-243.26"
           }
         },
         "w_rx_09_fifo_pulled_data": {
           "hide_name": 0,
-          "bits": [ 519, 521, 523, 525, 527, 529, 531, 63, 504, 506, 508, 510, 512, 514, 516, 68, 549, 551, 553, 555, 557, 559, 561, 64, 534, 536, 538, 540, 542, 544, 546, 69 ],
+          "bits": [ 504, 506, 508, 510, 512, 514, 58, 517, 489, 491, 493, 495, 497, 499, 63, 502, 534, 536, 538, 540, 542, 544, 59, 547, 519, 521, 523, 525, 527, 529, 64, 532 ],
           "attributes": {
-            "src": "top.v:252.16-252.40"
+            "src": "top.v:249.16-249.40"
           }
         },
         "w_rx_09_fifo_push": {
           "hide_name": 0,
           "bits": [ 260 ],
           "attributes": {
-            "src": "top.v:249.9-249.26"
+            "src": "top.v:246.9-246.26"
           }
         },
         "w_rx_09_fifo_write_clk": {
           "hide_name": 0,
           "bits": [ 193 ],
           "attributes": {
-            "src": "top.v:248.9-248.31"
+            "src": "top.v:245.9-245.31"
           }
         },
         "w_rx_24_fifo_data": {
           "hide_name": 0,
-          "bits": [ 338, 337, 334, 332, 330, 328, 326, 324, 322, 320, 318, 316, 312, 310, 308, 306, 304, 302, 300, 298, 296, 294, 350, 348, 346, 344, 342, 340, 336, 314, 292, 290 ],
+          "bits": [ 371, 370, 367, 365, 363, 361, 359, 357, 355, 353, 351, 349, 345, 343, 341, 339, 337, 335, 333, 331, 329, 327, 383, 381, 379, 377, 375, 373, 369, 347, 325, 323 ],
           "attributes": {
-            "src": "top.v:258.16-258.33"
+            "src": "top.v:255.16-255.33"
           }
         },
         "w_rx_24_fifo_empty": {
           "hide_name": 0,
-          "bits": [ 590 ],
+          "bits": [ 567 ],
           "attributes": {
-            "src": "top.v:255.9-255.27"
+            "src": "top.v:252.9-252.27"
           }
         },
         "w_rx_24_fifo_full": {
           "hide_name": 0,
-          "bits": [ 401 ],
+          "bits": [ 407 ],
           "attributes": {
-            "src": "top.v:254.9-254.26"
+            "src": "top.v:251.9-251.26"
           }
         },
         "w_rx_24_fifo_pulled_data": {
           "hide_name": 0,
-          "bits": [ 662, 664, 666, 668, 670, 672, 674, 58, 647, 649, 651, 653, 655, 657, 659, 59, 692, 694, 696, 698, 700, 702, 704, 71, 677, 679, 681, 683, 685, 687, 689, 72 ],
+          "bits": [ 662, 664, 666, 668, 670, 672, 53, 675, 647, 649, 651, 653, 655, 657, 54, 660, 692, 694, 696, 698, 700, 702, 66, 705, 677, 679, 681, 683, 685, 687, 67, 690 ],
           "attributes": {
-            "src": "top.v:260.16-260.40"
+            "src": "top.v:257.16-257.40"
           }
         },
         "w_rx_24_fifo_push": {
           "hide_name": 0,
-          "bits": [ 352 ],
+          "bits": [ 385 ],
           "attributes": {
-            "src": "top.v:257.9-257.26"
+            "src": "top.v:254.9-254.26"
           }
         },
         "w_rx_24_fifo_write_clk": {
           "hide_name": 0,
           "bits": [ 193 ],
           "attributes": {
-            "src": "top.v:256.9-256.31"
+            "src": "top.v:253.9-253.31"
           }
         },
         "w_rx_data": {
           "hide_name": 0,
-          "bits": [ 86, 83, 163, 162, 161, 160, 158, 155 ],
+          "bits": [ 74, 71, 165, 164, 163, 161, 159, 156 ],
           "attributes": {
             "src": "top.v:69.16-69.25"
           }
@@ -31775,74 +31684,74 @@
           "hide_name": 0,
           "bits": [ 28, 29, 30 ],
           "attributes": {
-            "src": "top.v:347.15-347.25"
+            "src": "top.v:344.15-344.25"
           }
         },
         "w_smi_data_input": {
           "hide_name": 0,
           "bits": [ 33, 34, 35, 36, 37, 38, 39, 40 ],
           "attributes": {
-            "src": "top.v:349.15-349.31"
+            "src": "top.v:346.15-346.31"
           }
         },
         "w_smi_data_output": {
           "hide_name": 0,
           "bits": [ 33, 190, 189, 188, 187, 186, 185, 184 ],
           "attributes": {
-            "src": "top.v:348.15-348.32"
+            "src": "top.v:345.15-345.32"
           }
         },
         "w_smi_read_req": {
           "hide_name": 0,
-          "bits": [ 408 ],
+          "bits": [ 414 ],
           "attributes": {
-            "src": "top.v:350.9-350.23"
+            "src": "top.v:347.9-347.23"
           }
         },
         "w_smi_test": {
           "hide_name": 0,
           "bits": [ "0" ],
           "attributes": {
-            "src": "top.v:353.9-353.19"
+            "src": "top.v:350.9-350.19"
           }
         },
         "w_smi_write_req": {
           "hide_name": 0,
           "bits": [ "x" ],
           "attributes": {
-            "src": "top.v:351.9-351.24"
+            "src": "top.v:348.9-348.24"
           }
         },
         "w_smi_writing": {
           "hide_name": 0,
           "bits": [ 30 ],
           "attributes": {
-            "src": "top.v:352.9-352.22"
+            "src": "top.v:349.9-349.22"
           }
         },
         "w_soft_reset": {
           "hide_name": 0,
-          "bits": [ 54 ],
+          "bits": [ 49 ],
           "attributes": {
             "src": "top.v:75.16-75.28"
           }
         },
         "w_tx_data_io": {
           "hide_name": 0,
-          "bits": [ 153, 119, 147, 122, 127, 133, 139, 142 ],
+          "bits": [ 153, 128, 144, 133, 138, 115, 118, 123 ],
           "attributes": {
             "src": "top.v:78.16-78.28"
           }
         },
         "w_tx_data_smi": {
           "hide_name": 0,
-          "bits": [ 736, 735, 734, 733 ],
+          "bits": [ 737, 736, 735, 734 ],
           "attributes": {
           }
         },
         "w_tx_data_sys": {
           "hide_name": 0,
-          "bits": [ 905, "0", "0", "0", "0", "0", "0", "0" ],
+          "bits": [ 902, "0", "0", "0", "0", "0", "0", "0" ],
           "attributes": {
             "src": "top.v:77.16-77.29"
           }
diff --git a/firmware/top.v b/firmware/top.v
index a169c0c..c3933cb 100644
--- a/firmware/top.v
+++ b/firmware/top.v
@@ -159,12 +159,12 @@ module top(
    // CONBINATORIAL ASSIGNMENTS
    //=========================================================================
    //assign w_clock_spi = r_counter[0];
-   //assign w_clock_sys = r_counter[0];
+   assign w_clock_sys = r_counter;
 
-   SB_GB sys_clk_buffer (          // Improve 'lvds_clock' fanout by pushing it into
+   /*SB_GB sys_clk_buffer (          // Improve 'lvds_clock' fanout by pushing it into
                                     // a global high-fanout buffer
       .USER_SIGNAL_TO_GLOBAL_BUFFER (r_counter),
-      .GLOBAL_BUFFER_OUTPUT(w_clock_sys) );
+      .GLOBAL_BUFFER_OUTPUT(w_clock_sys) );*/
 
    //=========================================================================
    // CLOCK AND DATA-FLOW
@@ -172,15 +172,12 @@ module top(
    always @(posedge i_glob_clock)
    begin
       r_counter <= !r_counter;
-   end
 
-   always @(posedge w_clock_sys)
-   begin
       case (w_cs)
          4'b0001: r_tx_data <= w_tx_data_sys;
          4'b0010: r_tx_data <= w_tx_data_io;
          4'b0100: r_tx_data <= w_tx_data_smi;
-         4'b1000: r_tx_data <= 8'b10100101;  // reserved
+         4'b1000: r_tx_data <= 8'b10100101;  // 0xA5: reserved
          4'b0000: r_tx_data <= 8'b00000000;  // no module selected
       endcase
    end
diff --git a/software/libcariboulite/src/caribou_fpga/build/test_caribou_fpga b/software/libcariboulite/src/caribou_fpga/build/test_caribou_fpga
index 8592c47..978bf9b 100755
Binary files a/software/libcariboulite/src/caribou_fpga/build/test_caribou_fpga and b/software/libcariboulite/src/caribou_fpga/build/test_caribou_fpga differ
diff --git a/software/libcariboulite/src/caribou_fpga/caribou_fpga.c b/software/libcariboulite/src/caribou_fpga/caribou_fpga.c
index 0bd11ff..62a2471 100644
--- a/software/libcariboulite/src/caribou_fpga/caribou_fpga.c
+++ b/software/libcariboulite/src/caribou_fpga/caribou_fpga.c
@@ -119,7 +119,7 @@ int caribou_fpga_init(caribou_fpga_st* dev, io_utils_spi_st* io_spi)
     ZF_LOGI("Initializing io_utils_spi");
     io_utils_hard_spi_st hard_dev_fpga = {  .spi_dev_id = dev->spi_dev,
                                             .spi_dev_channel = dev->spi_channel, };
-	dev->io_spi_handle = io_utils_spi_add_chip(dev->io_spi, dev->cs_pin, 4000000, 0, 0,
+	dev->io_spi_handle = io_utils_spi_add_chip(dev->io_spi, dev->cs_pin, 2000000, 0, 0,
                         						io_utils_spi_chip_type_fpga_comm,
                                                 &hard_dev_fpga);
 
diff --git a/software/libcariboulite/src/caribou_smi/build/test_caribou_smi b/software/libcariboulite/src/caribou_smi/build/test_caribou_smi
index c5d0cfd..1a0aaec 100755
Binary files a/software/libcariboulite/src/caribou_smi/build/test_caribou_smi and b/software/libcariboulite/src/caribou_smi/build/test_caribou_smi differ
diff --git a/software/libcariboulite/src/caribou_smi/test_caribou_smi.c b/software/libcariboulite/src/caribou_smi/test_caribou_smi.c
index 99be481..3153f35 100644
--- a/software/libcariboulite/src/caribou_smi/test_caribou_smi.c
+++ b/software/libcariboulite/src/caribou_smi/test_caribou_smi.c
@@ -120,7 +120,7 @@ void print_iq(uint32_t* array, int len)
         if (i_val >= 0x1000) i_val-=0x2000;
         float fi = i_val, fq = q_val;
         float mod = sqrt(fi*fi + fq*fq);
-        float arg = atan(fq / fi);
+        float arg = atan2(fq, fi);
         printf("%d, %d, %d, %.4f, %.2f\n", cnt, i_val, q_val, mod, arg);
         last_cnt = cnt;
     }