diff --git a/firmware/smi_ctrl.v b/firmware/smi_ctrl.v
index 24191d3..7f6badf 100644
--- a/firmware/smi_ctrl.v
+++ b/firmware/smi_ctrl.v
@@ -97,6 +97,9 @@ module smi_ctrl
     reg r_fifo_24_pull;
     reg [7:0] r_smi_test_count_09;
     reg [7:0] r_smi_test_count_24;
+    wire soe_change_falling;
+
+    assign soe_change_falling = (r_last_soe_2 == 1'b1 && r_last_soe_1 == 1'b0);
 
     always @(posedge i_sys_clk)
     begin
@@ -114,23 +117,19 @@ module smi_ctrl
             //  0.9 GHz Data Sender
             //==========================
             if (i_smi_a == smi_address_read_900) begin
-                if (r_last_soe_2 == 1'b0 && r_last_soe_1 == 1'b1) begin
-                    if (i_smi_test) begin
+                if (soe_change_falling) begin
+                    if (i_smi_test == 1'b1) begin
                         o_smi_data_out <= r_smi_test_count_09;
                         r_smi_test_count_09 <= r_smi_test_count_09 + 1'b1;
-                    end
-                end
-                /*if (r_last_soe != i_smi_soe_se) begin
-                    if (int_cnt_09 > 8) int_cnt_09 <= int_cnt_09 - 8;
+                    end else begin
+                        if (int_cnt_09 > 8) int_cnt_09 <= int_cnt_09 - 8;
 
-                    if (i_smi_test) begin
-                        r_smi_test_count_09 <= r_smi_test_count_09 + 1'b1;
-                        o_smi_data_out <= r_smi_test_count_09;
-                    end else if (r_fifo_09_pull) begin
-                        r_fifo_09_pull <= 1'b0;
-                        o_smi_data_out <= i_fifo_09_pulled_data[int_cnt_09-1:int_cnt_09-8];
+                        if (r_fifo_09_pull) begin
+                            r_fifo_09_pull <= 1'b0;
+                            o_smi_data_out <= i_fifo_09_pulled_data[int_cnt_09-1:int_cnt_09-8];
+                        end
                     end
-                end else if (i_smi_soe_se == 1'b1) begin
+                end else if (r_last_soe_1 == 1'b1 && i_smi_test == 1'b0) begin
                     if (int_cnt_09 > 0) begin
                         r_fifo_09_pull <= 1'b0;
                         o_smi_data_out <= i_fifo_09_pulled_data[int_cnt_09-1:int_cnt_09-8];
@@ -138,29 +137,25 @@ module smi_ctrl
                         r_fifo_09_pull <=1'b1;
                         int_cnt_09 <= 6'd32;
                     end
-                end*/
+                end
             end
             //==========================
             //  2.4 GHz Data Sender
             //==========================
             else if (i_smi_a == smi_address_read_2400) begin
-                if (r_last_soe_2 == 1'b0 && i_smi_soe_se == 1'b1) begin
-                    if (i_smi_test) begin
+                if (soe_change_falling) begin
+                    if (i_smi_test == 1'b1) begin
                         o_smi_data_out <= r_smi_test_count_24;
                         r_smi_test_count_24 <= r_smi_test_count_24 + 1'b1;
-                    end
-                end
-                /*if (r_last_soe != i_smi_soe_se) begin
-                    if (int_cnt_24 > 8) int_cnt_24 <= int_cnt_24 - 8;
+                    end else begin
+                        if (int_cnt_24 > 8) int_cnt_24 <= int_cnt_24 - 8;
 
-                    if (i_smi_test) begin
-                        r_smi_test_count_24 <= r_smi_test_count_24 + 1'b1;
-                        o_smi_data_out <= r_smi_test_count_24;
-                    end else if (r_fifo_24_pull) begin
-                        r_fifo_24_pull <= 1'b0;
-                        o_smi_data_out <= i_fifo_24_pulled_data[int_cnt_24-1:int_cnt_24-8];
+                        if (r_fifo_24_pull) begin
+                            r_fifo_24_pull <= 1'b0;
+                            o_smi_data_out <= i_fifo_24_pulled_data[int_cnt_24-1:int_cnt_24-8];
+                        end
                     end
-                end else if (i_smi_soe_se == 1'b1) begin
+                end else if (r_last_soe_1 == 1'b1 && i_smi_test == 1'b0) begin
                     if (int_cnt_24 > 0) begin
                         r_fifo_24_pull <= 1'b0;
                         o_smi_data_out <= i_fifo_24_pulled_data[int_cnt_24-1:int_cnt_24-8];
@@ -168,10 +163,10 @@ module smi_ctrl
                         r_fifo_24_pull <=1'b1;
                         int_cnt_24 <= 6'd32;
                     end
-                end*/
+                end
             end
             else begin
-                o_smi_data_out <= 8'b00000000;
+                //o_smi_data_out <= 8'b00000000;
                 // error with address
                 o_address_error <= 1'b1;
             end
diff --git a/firmware/top.asc b/firmware/top.asc
index e271990..498481a 100644
--- a/firmware/top.asc
+++ b/firmware/top.asc
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 .sym 8 i_glob_clock$SB_IO_IN_$glb_clk
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+.sym 524 w_rx_24_fifo_data[21]
+.sym 525 w_rx_24_fifo_data[27]
+.sym 526 w_rx_24_fifo_data[23]
+.sym 544 w_rx_24_fifo_data[5]
+.sym 545 i_smi_a1_SB_LUT4_I2_O[1]
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+.sym 863 rx_24_fifo.wr_addr[6]
+.sym 864 rx_24_fifo.wr_addr[2]
+.sym 865 rx_24_fifo.wr_addr[3]
+.sym 866 rx_24_fifo.wr_addr[5]
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 .sym 940 lvds_clock
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-.sym 980 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O[1]
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-.sym 1095 w_lvds_rx_24_d1_SB_LUT4_I2_O[3]
-.sym 1097 spi_if_ins.spi.SCKr[2]
-.sym 1169 $PACKER_VCC_NET
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+.sym 959 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 975 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[1]
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+.sym 977 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
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+.sym 1015 rx_24_fifo.wr_addr[5]
+.sym 1017 rx_24_fifo.wr_addr[0]
+.sym 1042 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 1049 rx_24_fifo.wr_addr[4]
+.sym 1053 rx_24_fifo.wr_addr[7]
+.sym 1054 i_smi_a3$SB_IO_IN
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+.sym 1089 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[3]
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+.sym 1094 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 1095 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
+.sym 1151 lvds_rx_24_inst.r_push_SB_LUT4_I3_1_O
 .sym 1173 w_lvds_rx_09_d0
 .sym 1174 w_lvds_rx_09_d1
 .sym 1183 $PACKER_VCC_NET
 .sym 1184 lvds_clock_buf
-.sym 1196 $PACKER_VCC_NET
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-.sym 1207 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
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-.sym 1212 w_lvds_rx_09_d1
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+.sym 1236 w_lvds_rx_09_d1
+.sym 1278 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
 .sym 1287 lvds_clock
 .sym 1297 $PACKER_VCC_NET
-.sym 1305 $PACKER_VCC_NET
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+.sym 1317 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[1]
+.sym 1318 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[2]
+.sym 1319 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_E_SB_LUT4_O_I1_SB_LUT4_O_I2[0]
+.sym 1320 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[0]
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+.sym 1322 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2]
+.sym 1323 lvds_rx_24_inst.r_state_if_SB_DFFNESR_Q_E_SB_LUT4_O_I0[2]
+.sym 1324 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
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 .sym 1401 w_lvds_rx_24_d0
 .sym 1402 w_lvds_rx_24_d1
 .sym 1411 $PACKER_VCC_NET
 .sym 1412 lvds_clock_buf
 .sym 1427 $PACKER_VCC_NET
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+.sym 2861 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[5]
+.sym 2862 rx_24_fifo.rd_addr_gray_wr_r[6]
+.sym 2863 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[6]
+.sym 2867 lvds_rx_24_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 2869 w_rx_24_fifo_data[28]
+.sym 2873 lvds_rx_24_inst.r_push_SB_LUT4_I3_O[1]
+.sym 2874 lvds_rx_24_inst.r_push_SB_LUT4_I3_O[0]
+.sym 2875 lvds_rx_24_inst.r_push_SB_LUT4_I3_O[2]
+.sym 2879 lvds_rx_24_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 2880 w_rx_24_fifo_data[26]
+.sym 2891 w_rx_24_fifo_data[20]
+.sym 2893 lvds_rx_24_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 2896 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[6]
+.sym 2898 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[7]
+.sym 2902 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[3]
+.sym 2903 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
+.sym 2904 w_rx_24_fifo_push
+.sym 2905 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[2]
+.sym 2906 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
+.sym 2907 lvds_clock_buf
+.sym 2908 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 2909 rx_24_fifo.rd_addr_gray_wr_r[7]
+.sym 2910 rx_24_fifo.rd_addr_gray_wr[7]
+.sym 2911 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0]
+.sym 2912 lvds_rx_24_inst.r_push_SB_LUT4_I3_O[1]
+.sym 2913 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
+.sym 2914 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_O_I1[2]
+.sym 2915 rx_24_fifo.rd_addr_gray_wr[3]
+.sym 2916 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_O_I1[1]
+.sym 2917 i_smi_a2$SB_IO_IN
+.sym 2920 i_smi_a2$SB_IO_IN
+.sym 2923 w_rx_24_fifo_data[22]
+.sym 2924 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 2927 w_rx_24_fifo_push
+.sym 2928 i_smi_soe_se$rename$0
+.sym 2929 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[6]
+.sym 2930 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 2931 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[7]
+.sym 2933 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 2935 rx_24_fifo.rd_addr[4]
+.sym 2936 rx_24_fifo.wr_addr[0]
+.sym 2938 w_rx_24_fifo_data[1]
+.sym 2939 w_rx_24_fifo_push
+.sym 2942 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 2945 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[6]
+.sym 2947 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[7]
+.sym 2955 w_rx_24_fifo_push
+.sym 2962 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_E_SB_LUT4_O_I1_SB_LUT4_O_I2[1]
+.sym 2967 lvds_rx_24_inst.r_state_if[0]
+.sym 2970 rx_24_fifo.wr_addr[4]
+.sym 2971 rx_24_fifo.wr_addr[1]
+.sym 2972 rx_24_fifo.wr_addr[7]
+.sym 2973 rx_24_fifo.wr_addr[6]
+.sym 2974 rx_24_fifo.wr_addr[2]
+.sym 2975 rx_24_fifo.wr_addr[3]
+.sym 2976 rx_24_fifo.wr_addr[5]
+.sym 2989 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_E
+.sym 2992 w_rx_24_fifo_full
+.sym 2994 $nextpnr_ICESTORM_LC_9$O
+.sym 2997 rx_24_fifo.wr_addr[1]
+.sym 3000 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2]
+.sym 3003 rx_24_fifo.wr_addr[2]
+.sym 3004 rx_24_fifo.wr_addr[1]
+.sym 3006 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3]
+.sym 3009 rx_24_fifo.wr_addr[3]
+.sym 3010 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2]
+.sym 3012 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4]
+.sym 3015 rx_24_fifo.wr_addr[4]
+.sym 3016 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3]
+.sym 3018 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5]
+.sym 3020 rx_24_fifo.wr_addr[5]
+.sym 3022 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4]
+.sym 3024 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6]
+.sym 3026 rx_24_fifo.wr_addr[6]
+.sym 3028 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5]
+.sym 3032 rx_24_fifo.wr_addr[7]
+.sym 3034 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6]
+.sym 3037 w_rx_24_fifo_full
+.sym 3038 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_E_SB_LUT4_O_I1_SB_LUT4_O_I2[1]
+.sym 3039 lvds_rx_24_inst.r_state_if[0]
+.sym 3041 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_E
 .sym 3042 lvds_clock_buf
-.sym 3043 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]_$glb_sr
-.sym 3044 w_tx_data_sys[0]
-.sym 3060 $PACKER_VCC_NET
-.sym 3066 w_rx_24_fifo_full
-.sym 3069 w_lvds_rx_09_d0
-.sym 3070 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
-.sym 3082 w_lvds_rx_24_d1_SB_LUT4_I2_O[3]
-.sym 3090 $PACKER_VCC_NET
-.sym 3097 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 3098 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q[2]
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-.sym 3107 w_lvds_rx_24_d1_SB_LUT4_I2_O[1]
-.sym 3110 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q[1]
-.sym 3112 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0]
-.sym 3116 lvds_rx_24_inst.r_phase_count[1]
-.sym 3117 w_lvds_rx_24_d1_SB_LUT4_I2_O[2]
-.sym 3119 $PACKER_VCC_NET
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-.sym 3127 w_lvds_rx_24_d1_SB_LUT4_I2_O[3]
-.sym 3128 lvds_rx_24_inst.r_phase_count[0]
-.sym 3129 $nextpnr_ICESTORM_LC_3$O
-.sym 3132 lvds_rx_24_inst.r_phase_count[0]
-.sym 3135 lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[2]
-.sym 3137 $PACKER_VCC_NET
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-.sym 3139 lvds_rx_24_inst.r_phase_count[0]
-.sym 3142 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q[1]
-.sym 3144 $PACKER_VCC_NET
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-.sym 3150 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q[2]
-.sym 3155 w_lvds_rx_24_d1_SB_LUT4_I2_O[3]
-.sym 3156 w_lvds_rx_24_d1_SB_LUT4_I2_O[2]
-.sym 3160 w_lvds_rx_24_d1_SB_LUT4_I2_O[1]
-.sym 3161 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 3162 w_lvds_rx_24_d1_SB_LUT4_I2_O[3]
-.sym 3163 w_lvds_rx_24_d1_SB_LUT4_I2_O[2]
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+.sym 3044 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[3]
+.sym 3045 rx_24_fifo.full_o_SB_LUT4_I3_O[3]
+.sym 3046 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
+.sym 3047 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
+.sym 3048 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
+.sym 3050 rx_24_fifo.rd_addr_gray[3]
+.sym 3051 rx_24_fifo.rd_addr[4]
+.sym 3056 rx_24_fifo.rd_addr[6]
+.sym 3057 w_rx_24_fifo_data[30]
+.sym 3058 w_rx_24_fifo_data[27]
+.sym 3059 smi_ctrl_ins.r_fifo_24_pull_SB_DFFESR_Q_E
+.sym 3060 w_rx_24_fifo_data[26]
+.sym 3063 lvds_rx_24_inst.r_state_if[0]
+.sym 3064 w_rx_24_fifo_data[29]
+.sym 3065 smi_ctrl_ins.r_fifo_24_pull_SB_DFFESR_Q_E
+.sym 3066 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_E_SB_LUT4_O_I1_SB_LUT4_O_I2[1]
+.sym 3068 rx_24_fifo.wr_addr[2]
+.sym 3070 rx_24_fifo.wr_addr[3]
+.sym 3071 rx_24_fifo.rd_addr_gray_wr_r[0]
+.sym 3072 rx_24_fifo.wr_addr[5]
+.sym 3073 lvds_rx_24_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 3075 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 3077 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
+.sym 3078 rx_24_fifo.wr_addr[1]
+.sym 3079 rx_24_fifo.rd_addr_gray_wr_r[6]
+.sym 3081 lvds_rx_24_inst.r_state_if[0]
+.sym 3089 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_E_SB_LUT4_O_I1_SB_LUT4_O_I2[1]
+.sym 3099 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 3100 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 3102 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[5]
+.sym 3106 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[1]
+.sym 3108 lvds_rx_24_inst.r_push_SB_LUT4_I3_1_O
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+.sym 3111 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[6]
+.sym 3112 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[7]
+.sym 3128 rx_24_fifo.wr_addr[0]
+.sym 3133 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 3139 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[1]
+.sym 3142 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[7]
+.sym 3150 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[6]
+.sym 3156 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 3162 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 3169 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[5]
+.sym 3175 rx_24_fifo.wr_addr[0]
+.sym 3176 lvds_rx_24_inst.r_push_SB_LUT4_I3_1_O
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-.sym 3178 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]_$glb_sr
-.sym 3180 int_miso
-.sym 3182 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
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-.sym 3237 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q[1]
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-.sym 3241 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[1]
-.sym 3242 w_lvds_rx_24_d1_SB_LUT4_I2_O[2]
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-.sym 3247 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
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-.sym 3252 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q_SB_DFFNESR_Q_D_SB_LUT4_O_I1[2]
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-.sym 3268 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q[1]
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-.sym 3273 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O[1]
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-.sym 3285 w_lvds_rx_24_d1_SB_LUT4_I2_O[2]
-.sym 3286 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
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+.sym 3264 $nextpnr_ICESTORM_LC_13$O
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+.sym 3696 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_E_SB_LUT4_O_I1[0]
+.sym 3697 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[2]
+.sym 3700 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0]
+.sym 3703 lvds_rx_24_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 3706 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_E_SB_LUT4_O_I1[3]
+.sym 3707 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[3]
+.sym 3708 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_E_SB_LUT4_O_I1[0]
+.sym 3709 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[1]
+.sym 3712 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0]
+.sym 3713 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[3]
+.sym 3714 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[0]
+.sym 3715 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2]
+.sym 3716 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3_SB_DFFNESR_Q_E
+.sym 3717 lvds_clock_buf
+.sym 3718 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 3720 rx_24_fifo.wr_addr_gray_rd[5]
+.sym 3723 rx_24_fifo.wr_addr_gray_rd[0]
+.sym 3726 rx_24_fifo.wr_addr_gray_rd[4]
+.sym 3731 $PACKER_VCC_NET
+.sym 3760 i_smi_a2$SB_IO_IN
+.sym 3777 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0]
+.sym 3778 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2]
+.sym 3830 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_1_I3[0]
+.sym 3836 lvds_rx_24_inst.r_phase_count_SB_LUT4_O_I3[2]
 .sym 4138 i_smi_a2$SB_IO_IN
-.sym 4252 lvds_rx_24_inst.r_push_SB_LUT4_I3_O
-.sym 4676 i_smi_a3$SB_IO_IN
-.sym 4798 rx_24_fifo.wr_addr[7]
+.sym 4159 o_shdn_tx_lna$SB_IO_OUT
+.sym 4207 i_smi_a3$SB_IO_IN
+.sym 4237 w_rx_09_fifo_pulled_data[16]
+.sym 4238 w_rx_09_fifo_pulled_data[17]
+.sym 4239 w_rx_09_fifo_pulled_data[18]
+.sym 4240 w_rx_09_fifo_pulled_data[19]
+.sym 4241 w_rx_09_fifo_pulled_data[20]
+.sym 4242 w_rx_09_fifo_pulled_data[21]
+.sym 4243 w_rx_09_fifo_pulled_data[22]
+.sym 4244 w_rx_09_fifo_pulled_data[23]
+.sym 4248 io_pmod[7]$SB_IO_IN
+.sym 4249 io_pmod[6]$SB_IO_IN
+.sym 4257 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4261 w_rx_24_fifo_data[0]
+.sym 4279 lvds_rx_09_inst.o_fifo_data[16]
+.sym 4280 lvds_rx_09_inst.o_fifo_data[28]
+.sym 4281 lvds_rx_09_inst.o_fifo_data[24]
+.sym 4286 lvds_rx_09_inst.o_fifo_data[18]
+.sym 4287 lvds_rx_09_inst.o_fifo_data[25]
+.sym 4297 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4300 lvds_rx_09_inst.o_fifo_data[22]
+.sym 4301 lvds_rx_09_inst.o_fifo_data[20]
+.sym 4303 lvds_rx_09_inst.o_fifo_data[26]
+.sym 4312 lvds_rx_09_inst.o_fifo_data[24]
+.sym 4314 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4319 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4320 lvds_rx_09_inst.o_fifo_data[26]
+.sym 4325 lvds_rx_09_inst.o_fifo_data[22]
+.sym 4326 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4332 lvds_rx_09_inst.o_fifo_data[28]
+.sym 4333 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4336 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4337 lvds_rx_09_inst.o_fifo_data[25]
+.sym 4343 lvds_rx_09_inst.o_fifo_data[20]
+.sym 4345 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4350 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4351 lvds_rx_09_inst.o_fifo_data[18]
+.sym 4355 lvds_rx_09_inst.o_fifo_data[16]
+.sym 4357 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4358 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
+.sym 4359 lvds_clock_buf
+.sym 4360 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 4365 w_rx_09_fifo_pulled_data[24]
+.sym 4366 w_rx_09_fifo_pulled_data[25]
+.sym 4367 w_rx_09_fifo_pulled_data[26]
+.sym 4368 w_rx_09_fifo_pulled_data[27]
+.sym 4369 w_rx_09_fifo_pulled_data[28]
+.sym 4370 w_rx_09_fifo_pulled_data[29]
+.sym 4371 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
+.sym 4372 w_rx_09_fifo_pulled_data[31]
+.sym 4378 rx_09_fifo.wr_addr[0]
+.sym 4379 $PACKER_VCC_NET
+.sym 4383 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4385 $PACKER_VCC_NET
+.sym 4387 lvds_rx_09_inst.o_fifo_data[25]
+.sym 4398 rx_09_fifo.wr_addr[5]
+.sym 4399 rx_09_fifo.wr_addr[3]
+.sym 4407 i_smi_a3$SB_IO_IN
+.sym 4409 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4420 i_smi_a1_SB_LUT4_I2_O[2]
+.sym 4421 lvds_rx_09_inst.o_fifo_data[15]
+.sym 4424 rx_09_fifo.wr_addr[7]
+.sym 4429 w_rx_09_fifo_push
+.sym 4446 lvds_rx_09_inst.o_fifo_data[13]
+.sym 4447 lvds_rx_09_inst.o_fifo_data[15]
+.sym 4452 lvds_rx_09_inst.o_fifo_data[14]
+.sym 4457 lvds_rx_09_inst.o_fifo_data[12]
+.sym 4464 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4471 lvds_rx_09_inst.o_fifo_data[31]
+.sym 4476 lvds_rx_09_inst.o_fifo_data[14]
+.sym 4477 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4487 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4489 lvds_rx_09_inst.o_fifo_data[12]
+.sym 4500 lvds_rx_09_inst.o_fifo_data[15]
+.sym 4501 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4506 lvds_rx_09_inst.o_fifo_data[13]
+.sym 4508 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4511 lvds_rx_09_inst.o_fifo_data[31]
+.sym 4521 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
+.sym 4522 lvds_clock_buf
+.sym 4523 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 4524 w_rx_09_fifo_pulled_data[0]
+.sym 4525 w_rx_09_fifo_pulled_data[1]
+.sym 4526 w_rx_09_fifo_pulled_data[2]
+.sym 4527 w_rx_09_fifo_pulled_data[3]
+.sym 4528 w_rx_09_fifo_pulled_data[4]
+.sym 4529 w_rx_09_fifo_pulled_data[5]
+.sym 4530 w_rx_09_fifo_pulled_data[6]
+.sym 4531 w_rx_09_fifo_pulled_data[7]
+.sym 4532 lvds_rx_09_inst.r_push_SB_LUT4_I3_1_O
+.sym 4534 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4537 rx_09_fifo.rd_addr[5]
+.sym 4540 io_smi_data[7]$SB_IO_OUT
+.sym 4544 lvds_rx_09_inst.o_fifo_data[29]
+.sym 4546 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[1]
+.sym 4549 lvds_rx_09_inst.o_fifo_data[14]
+.sym 4552 $PACKER_VCC_NET
+.sym 4553 i_smi_a3$SB_IO_IN
+.sym 4554 rx_09_fifo.rd_addr[2]
+.sym 4556 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 4559 $PACKER_VCC_NET
+.sym 4566 lvds_rx_09_inst.o_fifo_data[9]
+.sym 4573 lvds_rx_09_inst.o_fifo_data[8]
+.sym 4576 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4583 lvds_rx_09_inst.o_fifo_data[7]
+.sym 4584 lvds_rx_09_inst.o_fifo_data[11]
+.sym 4586 lvds_rx_09_inst.o_fifo_data[6]
+.sym 4587 lvds_rx_09_inst.o_fifo_data[10]
+.sym 4589 io_pmod[6]$SB_IO_IN
+.sym 4596 io_pmod[7]$SB_IO_IN
+.sym 4599 lvds_rx_09_inst.o_fifo_data[6]
+.sym 4600 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4605 lvds_rx_09_inst.o_fifo_data[7]
+.sym 4607 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4610 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4612 io_pmod[7]$SB_IO_IN
+.sym 4618 lvds_rx_09_inst.o_fifo_data[9]
+.sym 4619 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4623 lvds_rx_09_inst.o_fifo_data[11]
+.sym 4624 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4628 io_pmod[6]$SB_IO_IN
+.sym 4629 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4636 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4637 lvds_rx_09_inst.o_fifo_data[8]
+.sym 4641 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4643 lvds_rx_09_inst.o_fifo_data[10]
+.sym 4644 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
+.sym 4645 lvds_clock_buf
+.sym 4646 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 4647 w_rx_09_fifo_pulled_data[8]
+.sym 4648 w_rx_09_fifo_pulled_data[9]
+.sym 4649 w_rx_09_fifo_pulled_data[10]
+.sym 4650 w_rx_09_fifo_pulled_data[11]
+.sym 4651 w_rx_09_fifo_pulled_data[12]
+.sym 4652 w_rx_09_fifo_pulled_data[13]
+.sym 4653 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
+.sym 4654 w_rx_09_fifo_pulled_data[15]
+.sym 4656 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2[0]
+.sym 4663 rx_09_fifo.wr_addr[0]
+.sym 4665 io_pmod[5]$SB_IO_IN
+.sym 4676 w_rx_24_fifo_pulled_data[10]
+.sym 4678 io_pmod[7]$SB_IO_IN
+.sym 4679 smi_ctrl_ins.int_cnt_24[4]
+.sym 4680 w_rx_24_fifo_pulled_data[12]
+.sym 4681 w_rx_24_fifo_data[1]
+.sym 4682 w_rx_24_fifo_pulled_data[13]
+.sym 4688 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 4689 w_rx_24_fifo_pulled_data[13]
+.sym 4691 w_rx_24_fifo_pulled_data[12]
+.sym 4693 w_rx_09_fifo_data[0]
+.sym 4696 i_smi_a1_SB_LUT4_I2_O[2]
+.sym 4700 w_rx_24_fifo_pulled_data[10]
+.sym 4703 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 4704 i_smi_a1_SB_LUT4_I2_O[0]
+.sym 4707 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4708 w_rx_24_fifo_pulled_data[4]
+.sym 4709 w_rx_24_fifo_pulled_data[5]
+.sym 4712 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 4714 w_rx_24_fifo_pulled_data[2]
+.sym 4716 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 4721 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 4722 w_rx_24_fifo_pulled_data[13]
+.sym 4723 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 4724 w_rx_24_fifo_pulled_data[5]
+.sym 4739 w_rx_09_fifo_data[0]
+.sym 4741 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4745 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 4746 w_rx_24_fifo_pulled_data[2]
+.sym 4747 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 4748 w_rx_24_fifo_pulled_data[10]
+.sym 4751 w_rx_24_fifo_pulled_data[12]
+.sym 4752 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 4753 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 4754 w_rx_24_fifo_pulled_data[4]
+.sym 4758 i_smi_a1_SB_LUT4_I2_O[2]
+.sym 4759 i_smi_a1_SB_LUT4_I2_O[0]
+.sym 4760 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 4767 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
+.sym 4768 lvds_clock_buf
+.sym 4769 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 4770 i_smi_a1_SB_LUT4_I2_O[0]
+.sym 4771 w_rx_24_fifo_pulled_data[1]
+.sym 4772 w_rx_24_fifo_pulled_data[2]
+.sym 4773 w_rx_24_fifo_pulled_data[3]
+.sym 4774 w_rx_24_fifo_pulled_data[4]
+.sym 4775 w_rx_24_fifo_pulled_data[5]
+.sym 4776 w_rx_24_fifo_pulled_data[6]
+.sym 4777 w_rx_24_fifo_pulled_data[7]
+.sym 4783 $PACKER_VCC_NET
+.sym 4786 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2]
+.sym 4787 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 4788 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[1]
+.sym 4790 $io_pmod[4]$iobuf_i
+.sym 4791 $PACKER_VCC_NET
+.sym 4796 w_rx_24_fifo_data[15]
+.sym 4798 rx_24_fifo.rd_addr_gray_wr_r[4]
+.sym 4800 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4801 w_rx_24_fifo_pulled_data[27]
+.sym 4802 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
 .sym 4805 i_smi_a3$SB_IO_IN
-.sym 4813 lvds_rx_24_inst.r_push_SB_LUT4_I3_O
-.sym 4818 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0]
-.sym 4820 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
-.sym 4833 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[6]
-.sym 4842 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[7]
-.sym 4847 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0]
-.sym 4856 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[7]
-.sym 4858 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[6]
-.sym 4875 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
-.sym 4880 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[7]
-.sym 4890 lvds_rx_24_inst.r_push_SB_LUT4_I3_O
+.sym 4811 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 4813 $PACKER_VCC_NET
+.sym 4814 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 4815 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 4816 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 4817 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 4819 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 4821 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 4823 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 4824 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 4825 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 4826 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 4827 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 4828 w_rx_24_fifo_pulled_data[1]
+.sym 4829 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 4830 w_rx_24_fifo_pulled_data[11]
+.sym 4835 w_rx_24_fifo_data[4]
+.sym 4836 w_rx_24_fifo_pulled_data[9]
+.sym 4838 w_rx_24_fifo_pulled_data[3]
+.sym 4839 smi_ctrl_ins.int_cnt_24[4]
+.sym 4842 lvds_rx_24_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4845 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 4846 $PACKER_VCC_NET
+.sym 4847 smi_ctrl_ins.int_cnt_24[4]
+.sym 4850 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 4851 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 4852 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 4853 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 4856 w_rx_24_fifo_pulled_data[3]
+.sym 4857 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 4858 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 4859 w_rx_24_fifo_pulled_data[11]
+.sym 4862 w_rx_24_fifo_data[4]
+.sym 4865 lvds_rx_24_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4868 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 4869 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 4870 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 4871 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 4874 i_smi_a1_SB_LUT4_I2_O[1]
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+.sym 4880 w_rx_24_fifo_pulled_data[9]
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+.sym 4883 w_rx_24_fifo_pulled_data[1]
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+.sym 4890 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
 .sym 4891 lvds_clock_buf
-.sym 4892 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]_$glb_sr
-.sym 4905 rx_24_fifo.wr_addr_gray[3]
-.sym 4907 lvds_rx_24_inst.r_push_SB_LUT4_I3_O
-.sym 4911 rx_24_fifo.wr_addr_gray[6]
-.sym 4917 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
-.sym 4937 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[3]
-.sym 4938 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[4]
-.sym 4939 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[5]
-.sym 4943 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[1]
-.sym 4944 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[2]
-.sym 4945 lvds_rx_24_inst.r_push_SB_LUT4_I3_O
-.sym 4958 rx_24_fifo.wr_addr[0]
-.sym 4970 rx_24_fifo.wr_addr[0]
-.sym 4973 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[3]
-.sym 4975 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[2]
-.sym 4980 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[3]
-.sym 4985 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[5]
-.sym 4991 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[1]
-.sym 4994 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[2]
-.sym 5000 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[1]
-.sym 5005 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[1]
-.sym 5006 rx_24_fifo.wr_addr[0]
-.sym 5011 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[3]
-.sym 5012 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[4]
-.sym 5013 lvds_rx_24_inst.r_push_SB_LUT4_I3_O
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+.sym 4893 w_rx_24_fifo_pulled_data[8]
+.sym 4894 w_rx_24_fifo_pulled_data[9]
+.sym 4895 w_rx_24_fifo_pulled_data[10]
+.sym 4896 w_rx_24_fifo_pulled_data[11]
+.sym 4897 w_rx_24_fifo_pulled_data[12]
+.sym 4898 w_rx_24_fifo_pulled_data[13]
+.sym 4899 w_rx_24_fifo_pulled_data[14]
+.sym 4900 w_rx_24_fifo_pulled_data[15]
+.sym 4906 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 4907 $PACKER_VCC_NET
+.sym 4910 rx_24_fifo.wr_addr[1]
+.sym 4911 w_rx_24_fifo_data[4]
+.sym 4912 rx_24_fifo.wr_addr[7]
+.sym 4913 rx_24_fifo.wr_addr[4]
+.sym 4915 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1[3]
+.sym 4916 rx_24_fifo.wr_addr[2]
+.sym 4917 w_rx_24_fifo_data[0]
+.sym 4918 w_rx_24_fifo_push
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+.sym 4922 w_rx_24_fifo_pulled_data[26]
+.sym 4923 rx_24_fifo.rd_addr[5]
+.sym 4924 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 4925 w_rx_24_fifo_data[13]
+.sym 4926 w_rx_09_fifo_push
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+.sym 4928 w_rx_24_fifo_pulled_data[29]
+.sym 4934 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 4935 w_rx_24_fifo_data[16]
+.sym 4936 w_rx_24_fifo_pulled_data[25]
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+.sym 4941 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 4942 i_smi_a1_SB_LUT4_I2_O[0]
+.sym 4944 lvds_rx_24_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4946 w_rx_24_fifo_pulled_data[26]
+.sym 4949 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 4950 w_rx_24_fifo_pulled_data[16]
+.sym 4951 w_rx_24_fifo_pulled_data[17]
+.sym 4952 w_rx_24_fifo_pulled_data[29]
+.sym 4953 w_rx_24_fifo_pulled_data[19]
+.sym 4954 w_rx_24_fifo_pulled_data[30]
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+.sym 4960 w_rx_24_fifo_pulled_data[18]
+.sym 4961 w_rx_24_fifo_pulled_data[27]
+.sym 4964 w_rx_24_fifo_pulled_data[22]
+.sym 4968 w_rx_24_fifo_data[16]
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+.sym 4973 lvds_rx_24_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 4974 w_rx_24_fifo_data[29]
+.sym 4979 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 4980 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
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+.sym 4985 w_rx_24_fifo_pulled_data[21]
+.sym 4986 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 4987 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 4988 w_rx_24_fifo_pulled_data[29]
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+.sym 4992 w_rx_24_fifo_pulled_data[18]
+.sym 4993 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 4994 w_rx_24_fifo_pulled_data[26]
+.sym 4997 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 4998 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 4999 w_rx_24_fifo_pulled_data[22]
+.sym 5000 w_rx_24_fifo_pulled_data[30]
+.sym 5003 w_rx_24_fifo_pulled_data[16]
+.sym 5004 i_smi_a1_SB_LUT4_I2_O[0]
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+.sym 5009 w_rx_24_fifo_pulled_data[19]
+.sym 5010 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 5011 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 5012 w_rx_24_fifo_pulled_data[27]
+.sym 5013 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
 .sym 5014 lvds_clock_buf
-.sym 5015 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]_$glb_sr
-.sym 5044 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 5045 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
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-.sym 5066 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
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-.sym 5071 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
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-.sym 5092 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[5]
-.sym 5096 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[7]
-.sym 5097 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[6]
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-.sym 5104 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[6]
-.sym 5108 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[2]
-.sym 5117 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[4]
-.sym 5120 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
-.sym 5121 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0]
-.sym 5123 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[2]
-.sym 5128 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[6]
-.sym 5132 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
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-.sym 5134 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
-.sym 5135 rx_24_fifo.full_o_SB_LUT4_I3_O[3]
-.sym 5136 lvds_rx_24_inst.r_push_SB_LUT4_I3_O
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-.sym 5138 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]_$glb_sr
-.sym 5151 w_lvds_rx_09_d0
-.sym 5165 int_miso
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-.sym 5172 i_smi_a3$SB_IO_IN
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-.sym 5184 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
-.sym 5188 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
-.sym 5189 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
-.sym 5204 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
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-.sym 5214 w_rx_24_fifo_push
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-.sym 5232 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
-.sym 5237 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
-.sym 5243 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
-.sym 5259 lvds_rx_24_inst.r_push_SB_LUT4_I3_O
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+.sym 5017 w_rx_24_fifo_pulled_data[17]
+.sym 5018 w_rx_24_fifo_pulled_data[18]
+.sym 5019 w_rx_24_fifo_pulled_data[19]
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+.sym 5022 w_rx_24_fifo_pulled_data[22]
+.sym 5023 w_rx_24_fifo_pulled_data[23]
+.sym 5024 io_pmod[7]$SB_IO_IN
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+.sym 5030 w_rx_24_fifo_data[12]
+.sym 5031 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
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+.sym 5035 w_rx_24_fifo_data[9]
+.sym 5036 smi_ctrl_ins.int_cnt_24_SB_DFFESR_Q_E
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+.sym 5040 w_rx_24_fifo_pulled_data[30]
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+.sym 5043 $PACKER_VCC_NET
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+.sym 5045 rx_24_fifo.wr_addr[5]
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+.sym 5091 w_rx_24_fifo_data[24]
+.sym 5099 i_smi_a1_SB_LUT4_I1_O[1]
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+.sym 5105 rx_24_fifo.rd_addr_gray_wr_r[0]
+.sym 5110 i_smi_soe_se$rename$0
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+.sym 5115 w_rx_24_fifo_pulled_data[24]
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+.sym 5128 rx_24_fifo.rd_addr_gray_wr_r[4]
+.sym 5137 i_glob_clock$SB_IO_IN_$glb_clk
+.sym 5138 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 5139 w_rx_24_fifo_pulled_data[24]
+.sym 5140 w_rx_24_fifo_pulled_data[25]
+.sym 5141 w_rx_24_fifo_pulled_data[26]
+.sym 5142 w_rx_24_fifo_pulled_data[27]
+.sym 5143 w_rx_24_fifo_pulled_data[28]
+.sym 5144 w_rx_24_fifo_pulled_data[29]
+.sym 5145 w_rx_24_fifo_pulled_data[30]
+.sym 5146 w_rx_24_fifo_pulled_data[31]
+.sym 5147 io_pmod[6]$SB_IO_IN
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+.sym 5153 w_rx_24_fifo_data[16]
+.sym 5155 w_rx_24_fifo_data[23]
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+.sym 5157 rx_24_fifo.wr_addr[1]
+.sym 5158 rx_24_fifo.wr_addr[5]
+.sym 5159 i_smi_a1_SB_LUT4_I1_O[1]
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+.sym 5161 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2]
+.sym 5162 w_rx_24_fifo_data[20]
+.sym 5166 w_rx_24_fifo_data[21]
+.sym 5172 w_rx_24_fifo_data[1]
+.sym 5174 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 5180 rx_24_fifo.rd_addr_gray_wr_r[5]
+.sym 5181 rx_24_fifo.rd_addr[7]
+.sym 5182 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I0[0]
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+.sym 5185 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[5]
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+.sym 5188 rx_24_fifo.rd_addr_gray_wr_r[1]
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+.sym 5190 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[2]
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+.sym 5205 rx_24_fifo.rd_addr_gray_wr[7]
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+.sym 5215 rx_24_fifo.rd_addr_gray_wr[7]
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+.sym 5228 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_O_I1[0]
+.sym 5231 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[2]
+.sym 5232 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
+.sym 5234 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[1]
+.sym 5238 rx_24_fifo.rd_addr_gray_wr[3]
+.sym 5243 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[5]
+.sym 5244 rx_24_fifo.rd_addr_gray_wr_r[5]
+.sym 5245 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0]
+.sym 5246 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[4]
+.sym 5251 rx_24_fifo.rd_addr_gray[3]
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+.sym 5257 rx_24_fifo.wr_addr[1]
+.sym 5258 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I0[0]
 .sym 5260 lvds_clock_buf
-.sym 5261 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]_$glb_sr
-.sym 5276 rx_24_fifo.wr_addr_gray[4]
-.sym 5282 rx_24_fifo.wr_addr_gray[1]
-.sym 5284 rx_24_fifo.wr_addr_gray[0]
-.sym 5294 w_tx_data_sys[0]
-.sym 5296 spi_if_ins.spi.SCKr[2]
-.sym 5305 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
-.sym 5315 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 5337 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 5382 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
+.sym 5274 rx_24_fifo.rd_addr_gray_wr_r[1]
+.sym 5275 rx_24_fifo.rd_addr[0]
+.sym 5277 rx_24_fifo.rd_addr[1]
+.sym 5278 smi_ctrl_ins.r_fifo_24_pull_SB_LUT4_I3_1_O
+.sym 5280 w_rx_24_fifo_data[28]
+.sym 5281 rx_24_fifo.wr_addr[7]
+.sym 5283 $PACKER_VCC_NET
+.sym 5284 rx_24_fifo.rd_addr_gray_wr_r[5]
+.sym 5285 rx_24_fifo.rd_addr[7]
+.sym 5287 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0]
+.sym 5288 w_rx_24_fifo_pulled_data[27]
+.sym 5289 w_rx_24_fifo_full
+.sym 5292 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 5293 i_smi_a3$SB_IO_IN
+.sym 5294 rx_24_fifo.rd_addr_gray_wr_r[4]
+.sym 5296 rx_24_fifo.rd_addr_gray_wr_r[6]
+.sym 5303 rx_24_fifo.rd_addr_gray_wr_r[6]
+.sym 5304 rx_24_fifo.full_o_SB_LUT4_I3_O[3]
+.sym 5305 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
+.sym 5307 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
+.sym 5308 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 5311 rx_24_fifo.rd_addr_gray_wr_r[7]
+.sym 5312 rx_24_fifo.rd_addr_gray_wr_r[1]
+.sym 5314 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0]
+.sym 5315 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 5316 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[4]
+.sym 5318 w_rx_24_fifo_full
+.sym 5319 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
+.sym 5320 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[1]
+.sym 5321 smi_ctrl_ins.r_fifo_24_pull_SB_LUT4_I3_1_O
+.sym 5322 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 5323 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 5326 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[7]
+.sym 5327 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
+.sym 5329 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 5334 w_rx_24_fifo_push
+.sym 5336 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
+.sym 5337 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 5338 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
+.sym 5339 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 5342 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[7]
+.sym 5343 w_rx_24_fifo_full
+.sym 5344 rx_24_fifo.rd_addr_gray_wr_r[7]
+.sym 5345 w_rx_24_fifo_push
+.sym 5348 rx_24_fifo.rd_addr_gray_wr_r[1]
+.sym 5349 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[1]
+.sym 5354 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
+.sym 5355 rx_24_fifo.rd_addr_gray_wr_r[6]
+.sym 5356 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 5357 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0]
+.sym 5360 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
+.sym 5361 rx_24_fifo.full_o_SB_LUT4_I3_O[3]
+.sym 5362 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 5363 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 5375 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 5379 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[4]
+.sym 5382 smi_ctrl_ins.r_fifo_24_pull_SB_LUT4_I3_1_O
 .sym 5383 r_counter[0]_$glb_clk
-.sym 5397 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
-.sym 5398 sys_ctrl_ins.reset_cmd
-.sym 5400 lvds_rx_24_inst.r_push_SB_LUT4_I3_O
-.sym 5405 sys_ctrl_ins.reset_cmd
-.sym 5412 spi_if_ins.spi.SCKr[1]
-.sym 5415 $PACKER_VCC_NET
-.sym 5431 spi_if_ins.spi.SCKr[2]
-.sym 5434 spi_if_ins.spi.SCKr[1]
-.sym 5437 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1]
-.sym 5438 spi_if_ins.r_tx_byte[7]
-.sym 5453 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
-.sym 5455 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
-.sym 5457 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
-.sym 5466 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
-.sym 5467 spi_if_ins.r_tx_byte[7]
-.sym 5468 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1]
-.sym 5480 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
-.sym 5501 spi_if_ins.spi.SCKr[2]
-.sym 5502 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
-.sym 5503 spi_if_ins.spi.SCKr[1]
-.sym 5505 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
-.sym 5506 r_counter[0]_$glb_clk
-.sym 5529 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
-.sym 5530 spi_if_ins.r_tx_byte[4]
-.sym 5551 spi_if_ins.spi.r_tx_bit_count[2]
-.sym 5553 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
-.sym 5554 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0]
-.sym 5555 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3]
-.sym 5560 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
-.sym 5562 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R
-.sym 5563 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[3]
-.sym 5564 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1]
-.sym 5565 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
-.sym 5568 spi_if_ins.spi.SCKr[2]
-.sym 5572 spi_if_ins.spi.SCKr[1]
-.sym 5575 $PACKER_VCC_NET
-.sym 5581 $nextpnr_ICESTORM_LC_11$O
-.sym 5584 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3]
-.sym 5587 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
-.sym 5589 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
-.sym 5590 $PACKER_VCC_NET
-.sym 5595 $PACKER_VCC_NET
-.sym 5596 spi_if_ins.spi.r_tx_bit_count[2]
-.sym 5597 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
-.sym 5600 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[3]
-.sym 5601 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
-.sym 5602 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0]
-.sym 5603 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1]
-.sym 5606 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
-.sym 5607 $PACKER_VCC_NET
-.sym 5608 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3]
-.sym 5615 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
-.sym 5620 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3]
-.sym 5624 spi_if_ins.spi.SCKr[1]
-.sym 5625 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3]
-.sym 5626 spi_if_ins.spi.SCKr[2]
-.sym 5627 spi_if_ins.spi.r_tx_bit_count[2]
-.sym 5628 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
-.sym 5629 r_counter[0]_$glb_clk
-.sym 5630 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R
-.sym 5663 spi_if_ins.r_tx_byte[7]
-.sym 5664 i_smi_a3$SB_IO_IN
-.sym 5672 spi_if_ins.spi.r_tx_byte[2]
-.sym 5674 spi_if_ins.r_tx_byte[7]
-.sym 5675 spi_if_ins.r_tx_byte[1]
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-.sym 5678 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3]
-.sym 5680 spi_if_ins.spi.r_tx_byte[3]
-.sym 5682 spi_if_ins.spi.r_tx_bit_count[2]
-.sym 5683 spi_if_ins.r_tx_byte[2]
-.sym 5684 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
-.sym 5685 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1]
-.sym 5686 spi_if_ins.spi.r_tx_byte[6]
-.sym 5687 spi_if_ins.r_tx_byte[5]
-.sym 5689 spi_if_ins.spi.r_tx_byte[1]
-.sym 5690 spi_if_ins.spi.r_tx_byte[5]
-.sym 5691 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0]
-.sym 5692 spi_if_ins.spi.r_tx_byte[7]
-.sym 5699 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
-.sym 5707 spi_if_ins.r_tx_byte[2]
-.sym 5711 spi_if_ins.r_tx_byte[1]
-.sym 5719 spi_if_ins.r_tx_byte[5]
-.sym 5723 spi_if_ins.spi.r_tx_byte[1]
-.sym 5724 spi_if_ins.spi.r_tx_byte[5]
-.sym 5725 spi_if_ins.spi.r_tx_bit_count[2]
-.sym 5731 spi_if_ins.r_tx_byte[7]
-.sym 5735 spi_if_ins.spi.r_tx_bit_count[2]
-.sym 5736 spi_if_ins.spi.r_tx_byte[7]
-.sym 5737 spi_if_ins.spi.r_tx_byte[3]
-.sym 5738 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3]
-.sym 5741 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[1]
-.sym 5742 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0]
-.sym 5743 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3]
-.sym 5744 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
-.sym 5747 spi_if_ins.spi.r_tx_bit_count[2]
-.sym 5748 spi_if_ins.spi.r_tx_byte[2]
-.sym 5749 spi_if_ins.spi.r_tx_byte[6]
-.sym 5750 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0[3]
-.sym 5751 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
-.sym 5752 r_counter[0]_$glb_clk
-.sym 5753 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
-.sym 5771 spi_if_ins.r_tx_byte[2]
-.sym 5775 spi_if_ins.r_tx_byte[5]
-.sym 5782 i_ss$SB_IO_IN
-.sym 5796 spi_if_ins.spi.r_tx_byte[0]
-.sym 5797 spi_if_ins.r_tx_byte[0]
-.sym 5799 spi_if_ins.spi.r_tx_bit_count[2]
-.sym 5800 i_ss$SB_IO_IN
-.sym 5802 spi_if_ins.r_tx_byte[6]
-.sym 5808 spi_if_ins.r_tx_byte[4]
-.sym 5811 spi_if_ins.spi.r_tx_byte[4]
-.sym 5813 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
-.sym 5815 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
-.sym 5819 spi_if_ins.r_tx_data_valid
-.sym 5830 spi_if_ins.r_tx_byte[4]
-.sym 5837 spi_if_ins.r_tx_byte[0]
-.sym 5853 spi_if_ins.r_tx_data_valid
-.sym 5855 i_ss$SB_IO_IN
-.sym 5859 spi_if_ins.spi.r_tx_byte[4]
-.sym 5860 spi_if_ins.spi.r_tx_byte[0]
-.sym 5861 spi_if_ins.spi.r_tx_bit_count[2]
-.sym 5865 spi_if_ins.r_tx_byte[6]
-.sym 5874 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
-.sym 5875 r_counter[0]_$glb_clk
-.sym 5876 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O
-.sym 5920 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
-.sym 5922 r_tx_data[6]
-.sym 5925 r_tx_data[0]
-.sym 5966 r_tx_data[0]
-.sym 5994 r_tx_data[6]
-.sym 5997 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 5384 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 5397 w_rx_09_fifo_data[0]
+.sym 5398 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_E
+.sym 5401 $io_pmod[5]$iobuf_i
+.sym 5404 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[4]
+.sym 5409 w_rx_24_fifo_data[0]
+.sym 5418 w_rx_09_fifo_push
+.sym 5420 rx_24_fifo.rd_addr_gray_wr[0]
+.sym 5426 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[2]
+.sym 5427 rx_24_fifo.rd_addr_gray_wr_r[0]
+.sym 5428 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 5429 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 5432 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[6]
+.sym 5434 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[3]
+.sym 5435 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[1]
+.sym 5437 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
+.sym 5438 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
+.sym 5439 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[5]
+.sym 5441 rx_24_fifo.rd_addr_gray_wr_r[5]
+.sym 5442 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[2]
+.sym 5444 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3]
+.sym 5447 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0]
+.sym 5449 rx_24_fifo.wr_addr[0]
+.sym 5451 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3]
+.sym 5454 rx_24_fifo.rd_addr_gray_wr_r[4]
+.sym 5456 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 5459 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3]
+.sym 5460 rx_24_fifo.rd_addr_gray_wr_r[0]
+.sym 5461 rx_24_fifo.rd_addr_gray_wr_r[5]
+.sym 5462 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 5465 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[3]
+.sym 5466 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[2]
+.sym 5467 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
+.sym 5468 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
+.sym 5471 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[5]
+.sym 5473 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[6]
+.sym 5478 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 5479 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 5496 rx_24_fifo.wr_addr[0]
+.sym 5497 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[1]
+.sym 5501 rx_24_fifo.rd_addr_gray_wr_r[4]
+.sym 5502 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[2]
+.sym 5503 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0]
+.sym 5504 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3]
+.sym 5506 lvds_clock_buf
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+.sym 5521 w_rx_24_fifo_push
+.sym 5524 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 5526 lvds_rx_24_inst.r_push_SB_LUT4_I3_1_O
+.sym 5533 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3]
+.sym 5536 rx_24_fifo.rd_addr[2]
+.sym 5539 $PACKER_VCC_NET
+.sym 5540 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[2]
+.sym 5542 w_lvds_rx_24_d0
+.sym 5549 rx_24_fifo.rd_addr_gray_wr[6]
+.sym 5552 rx_24_fifo.rd_addr_gray_wr[2]
+.sym 5554 rx_24_fifo.rd_addr_gray_wr[5]
+.sym 5557 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[0]
+.sym 5558 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[3]
+.sym 5569 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_E_SB_LUT4_O_I1_SB_LUT4_O_I2[1]
+.sym 5573 lvds_rx_24_inst.r_state_if[0]
+.sym 5577 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 5578 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[5]
+.sym 5580 rx_24_fifo.rd_addr_gray_wr[0]
+.sym 5584 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[5]
+.sym 5585 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 5589 rx_24_fifo.rd_addr_gray_wr[0]
+.sym 5595 lvds_rx_24_inst.r_state_if[0]
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+.sym 5600 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[0]
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+.sym 5775 $PACKER_VCC_NET
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+.sym 5927 rx_24_fifo.wr_addr_gray[4]
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+.sym 5957 rx_24_fifo.wr_addr_gray[5]
+.sym 5975 rx_24_fifo.wr_addr_gray[0]
+.sym 5996 rx_24_fifo.wr_addr_gray[4]
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-.sym 6029 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
-.sym 6045 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
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-.sym 6052 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
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-.sym 6121 r_counter[0]_$glb_clk
-.sym 6122 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
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-.sym 6151 i_smi_a3$SB_IO_IN
+.sym 6016 rx_24_fifo.wr_addr_gray_rd[5]
+.sym 6029 rx_24_fifo.wr_addr_gray_rd[0]
+.sym 6139 o_shdn_tx_lna$SB_IO_OUT
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-.sym 6301 o_shdn_tx_lna$SB_IO_OUT
-.sym 6316 i_smi_a3$SB_IO_IN
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-.sym 6348 i_smi_a2_SB_LUT4_I1_O[1]
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-.sym 6350 smi_ctrl_ins.r_smi_test_count_24[4]
-.sym 6351 smi_ctrl_ins.r_smi_test_count_24[5]
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-.sym 6460 i_smi_a3$SB_IO_IN
-.sym 6463 i_smi_a3$SB_IO_IN
-.sym 6608 i_smi_a3$SB_IO_IN
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-.sym 6665 lvds_rx_09_inst.r_push_SB_DFFNESR_Q_E_SB_LUT4_O_I1_SB_LUT4_O_I2[2]
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+.sym 6310 o_shdn_tx_lna$SB_IO_OUT
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+.sym 6378 i_smi_a3$SB_IO_IN
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+.sym 6387 rx_09_fifo.wr_addr[5]
+.sym 6388 rx_09_fifo.wr_addr[6]
+.sym 6389 rx_09_fifo.wr_addr[7]
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+.sym 6393 $PACKER_VCC_NET
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+.sym 6397 $PACKER_VCC_NET
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+.sym 6401 $PACKER_VCC_NET
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+.sym 6423 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
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+.sym 6426 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 6427 io_smi_data[7]$SB_IO_OUT
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+.sym 6430 $PACKER_VCC_NET
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+.sym 6432 $PACKER_VCC_NET
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+.sym 6434 $PACKER_VCC_NET
+.sym 6435 $PACKER_VCC_NET
+.sym 6436 $PACKER_VCC_NET
+.sym 6437 $PACKER_VCC_NET
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+.sym 6441 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
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+.sym 6443 rx_09_fifo.wr_addr[4]
+.sym 6444 rx_09_fifo.wr_addr[5]
+.sym 6445 rx_09_fifo.wr_addr[6]
+.sym 6446 rx_09_fifo.wr_addr[7]
+.sym 6449 lvds_clock_buf
+.sym 6450 $PACKER_VCC_NET
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+.sym 6467 rx_09_fifo.wr_addr[7]
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+.sym 6475 i_smi_a3$SB_IO_IN
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+.sym 6530 $PACKER_VCC_NET
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+.sym 6677 $PACKER_VCC_NET
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+.sym 6681 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
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+.sym 6683 rx_09_fifo.wr_addr[4]
+.sym 6684 rx_09_fifo.wr_addr[5]
+.sym 6685 rx_09_fifo.wr_addr[6]
+.sym 6686 rx_09_fifo.wr_addr[7]
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+.sym 6690 $PACKER_VCC_NET
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+.sym 6694 io_pmod[5]$SB_IO_IN
+.sym 6695 io_pmod[6]$SB_IO_IN
+.sym 6696 io_pmod[7]$SB_IO_IN
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-.sym 6767 lvds_rx_09_inst.r_push_SB_DFFNESR_Q_E_SB_LUT4_O_I1_SB_LUT4_I0_O_SB_DFFNESR_D_E
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-.sym 6872 rx_24_fifo.wr_addr_gray_rd_r[2]
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+.sym 7177 $io_pmod[5]$iobuf_i
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+.sym 7180 $PACKER_VCC_NET
+.sym 7181 $PACKER_VCC_NET
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+.sym 7183 $PACKER_VCC_NET
+.sym 7184 $PACKER_VCC_NET
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+.sym 7186 $PACKER_VCC_NET
+.sym 7187 $PACKER_VCC_NET
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+.sym 7194 rx_24_fifo.rd_addr[5]
+.sym 7195 rx_24_fifo.rd_addr[6]
+.sym 7196 rx_24_fifo.rd_addr[7]
+.sym 7199 r_counter[0]_$glb_clk
+.sym 7200 $PACKER_VCC_NET
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+.sym 7275 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
+.sym 7276 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1]
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+.sym 7383 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[0]
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+.sym 7521 io_ctrl_ins.led0_state_SB_LUT4_I3_I0[0]
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+.sym 7583 lvds_rx_09_inst.r_phase_count[1]
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+.sym 7725 $PACKER_VCC_NET
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 .sym 8088 i_smi_a3$SB_IO_IN
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-.sym 8120 w_smi_data_output[2]
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-.sym 8122 w_smi_data_output[7]
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-.sym 8201 smi_ctrl_ins.r_smi_test_count_24[1]
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-.sym 8206 i_smi_a2_SB_LUT4_I1_O[1]
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-.sym 8213 smi_ctrl_ins.r_smi_test_count_24[3]
-.sym 8214 smi_ctrl_ins.r_smi_test_count_24_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
-.sym 8216 smi_ctrl_ins.r_smi_test_count_24_SB_DFFESR_Q_D_SB_LUT4_O_I3[5]
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-.sym 8222 smi_ctrl_ins.r_smi_test_count_24_SB_DFFESR_Q_D_SB_LUT4_O_I3[6]
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+.sym 8206 lvds_rx_09_inst.o_fifo_data[21]
+.sym 8211 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 8219 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 8220 lvds_rx_09_inst.o_fifo_data[17]
+.sym 8224 i_smi_a3$SB_IO_IN
+.sym 8225 w_smi_data_output[6]
+.sym 8235 lvds_rx_09_inst.o_fifo_data[19]
+.sym 8238 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 8239 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
+.sym 8240 lvds_clock_buf
+.sym 8241 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 8246 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_O[1]
+.sym 8247 rx_09_fifo.rd_addr[3]
+.sym 8248 rx_09_fifo.rd_addr[5]
+.sym 8249 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
+.sym 8250 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 8252 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_O[0]
+.sym 8253 rx_09_fifo.rd_addr[1]
+.sym 8259 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[6]
+.sym 8262 rx_09_fifo.rd_addr[2]
+.sym 8263 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[7]
+.sym 8264 rx_09_fifo.rd_addr[4]
+.sym 8280 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 8284 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 8294 io_smi_data[1]$SB_IO_OUT
+.sym 8305 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1[1]
+.sym 8308 rx_09_fifo.rd_addr[1]
+.sym 8310 io_smi_data[2]$SB_IO_OUT
+.sym 8312 rx_09_fifo.rd_addr[3]
+.sym 8325 rx_09_fifo.rd_addr[0]
+.sym 8326 w_rx_09_fifo_pulled_data[27]
+.sym 8327 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 8329 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8331 w_rx_09_fifo_pulled_data[15]
+.sym 8333 w_rx_09_fifo_pulled_data[23]
+.sym 8334 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 8337 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8338 w_rx_09_fifo_pulled_data[31]
+.sym 8340 w_smi_data_output[7]
+.sym 8341 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 8342 w_rx_09_fifo_pulled_data[3]
+.sym 8344 w_rx_09_fifo_pulled_data[5]
+.sym 8345 w_rx_09_fifo_pulled_data[6]
+.sym 8346 w_rx_09_fifo_pulled_data[11]
+.sym 8348 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 8349 i_smi_a3$SB_IO_IN
+.sym 8350 w_rx_09_fifo_pulled_data[19]
+.sym 8352 w_rx_09_fifo_pulled_data[21]
+.sym 8353 w_rx_09_fifo_pulled_data[22]
+.sym 8354 w_rx_09_fifo_pulled_data[7]
+.sym 8356 w_rx_09_fifo_pulled_data[21]
+.sym 8357 w_rx_09_fifo_pulled_data[5]
+.sym 8358 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 8359 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8362 w_rx_09_fifo_pulled_data[23]
+.sym 8363 w_rx_09_fifo_pulled_data[7]
+.sym 8364 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8365 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 8370 rx_09_fifo.rd_addr[0]
+.sym 8374 w_rx_09_fifo_pulled_data[11]
+.sym 8375 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 8376 w_rx_09_fifo_pulled_data[27]
+.sym 8377 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8380 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 8381 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8382 w_rx_09_fifo_pulled_data[19]
+.sym 8383 w_rx_09_fifo_pulled_data[3]
+.sym 8386 i_smi_a3$SB_IO_IN
+.sym 8388 w_smi_data_output[7]
+.sym 8392 w_rx_09_fifo_pulled_data[31]
+.sym 8393 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8394 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 8395 w_rx_09_fifo_pulled_data[15]
+.sym 8398 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8399 w_rx_09_fifo_pulled_data[6]
+.sym 8400 w_rx_09_fifo_pulled_data[22]
+.sym 8401 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 8402 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 8403 r_counter[0]_$glb_clk
+.sym 8404 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 8405 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 8406 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O_SB_LUT4_I3_O[1]
+.sym 8407 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1[1]
+.sym 8408 io_smi_data[1]$SB_IO_OUT
+.sym 8409 rx_09_fifo.wr_addr[0]
+.sym 8411 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O[3]
+.sym 8412 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
+.sym 8417 w_rx_09_fifo_pulled_data[15]
+.sym 8420 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
+.sym 8422 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 8423 rx_09_fifo.rd_addr[0]
+.sym 8425 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8428 rx_09_fifo.rd_addr[5]
+.sym 8429 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1[3]
+.sym 8430 i_smi_a1_SB_LUT4_I3_O[1]
+.sym 8431 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_2_D_SB_LUT4_O_I1[3]
+.sym 8432 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
+.sym 8433 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
+.sym 8434 i_smi_a3$SB_IO_IN
+.sym 8439 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 8447 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 8449 w_rx_09_fifo_pulled_data[1]
+.sym 8450 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 8452 w_rx_09_fifo_pulled_data[25]
+.sym 8453 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
+.sym 8454 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 8455 w_rx_09_fifo_pulled_data[20]
+.sym 8456 w_rx_09_fifo_pulled_data[2]
+.sym 8457 w_rx_09_fifo_pulled_data[17]
+.sym 8458 w_rx_09_fifo_pulled_data[4]
+.sym 8459 w_rx_09_fifo_pulled_data[18]
+.sym 8460 w_rx_09_fifo_pulled_data[29]
+.sym 8461 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8462 w_rx_09_fifo_pulled_data[24]
+.sym 8463 w_rx_09_fifo_pulled_data[9]
+.sym 8466 w_rx_09_fifo_pulled_data[12]
+.sym 8467 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8468 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
+.sym 8470 w_rx_09_fifo_pulled_data[8]
+.sym 8471 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 8474 w_rx_09_fifo_pulled_data[28]
+.sym 8475 w_rx_09_fifo_pulled_data[13]
+.sym 8476 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
+.sym 8479 w_rx_09_fifo_pulled_data[25]
+.sym 8480 w_rx_09_fifo_pulled_data[9]
+.sym 8481 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 8482 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8485 w_rx_09_fifo_pulled_data[1]
+.sym 8486 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8487 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 8488 w_rx_09_fifo_pulled_data[17]
+.sym 8491 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8492 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 8493 w_rx_09_fifo_pulled_data[13]
+.sym 8494 w_rx_09_fifo_pulled_data[29]
+.sym 8497 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
+.sym 8498 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8499 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
+.sym 8500 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
+.sym 8503 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8504 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 8505 w_rx_09_fifo_pulled_data[20]
+.sym 8506 w_rx_09_fifo_pulled_data[4]
+.sym 8509 w_rx_09_fifo_pulled_data[2]
+.sym 8510 w_rx_09_fifo_pulled_data[18]
+.sym 8511 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 8512 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8515 w_rx_09_fifo_pulled_data[12]
+.sym 8516 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8517 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 8518 w_rx_09_fifo_pulled_data[28]
+.sym 8521 w_rx_09_fifo_pulled_data[8]
+.sym 8522 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8523 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 8524 w_rx_09_fifo_pulled_data[24]
+.sym 8528 w_smi_data_output[1]
+.sym 8530 io_smi_data[0]$SB_IO_OUT
+.sym 8531 w_smi_data_output[2]
+.sym 8532 io_smi_data[2]$SB_IO_OUT
+.sym 8533 w_smi_data_output[5]
+.sym 8534 w_smi_data_output[7]
+.sym 8535 w_smi_data_output[6]
+.sym 8540 w_rx_09_fifo_pulled_data[10]
+.sym 8544 w_rx_09_fifo_pulled_data[26]
+.sym 8545 w_rx_09_fifo_pulled_data[16]
+.sym 8547 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 8549 rx_09_fifo.wr_addr[4]
+.sym 8553 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8556 i_smi_a1_SB_LUT4_I3_O[1]
+.sym 8557 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2_SB_LUT4_O_I1[2]
+.sym 8559 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 8562 smi_ctrl_ins.int_cnt_09[5]
+.sym 8563 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 8569 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 8571 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 8572 i_smi_a1_SB_LUT4_I2_O[2]
+.sym 8573 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2_SB_LUT4_O_I1[2]
+.sym 8574 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 8575 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8579 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 8580 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1]
+.sym 8582 smi_ctrl_ins.int_cnt_09[4]
+.sym 8583 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 8585 w_rx_09_fifo_pulled_data[0]
+.sym 8586 $PACKER_VCC_NET
+.sym 8587 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 8588 smi_ctrl_ins.int_cnt_09[5]
+.sym 8589 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 8592 w_rx_24_fifo_pulled_data[15]
+.sym 8593 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 8594 $PACKER_VCC_NET
+.sym 8595 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2]
+.sym 8596 smi_ctrl_ins.r_fifo_09_pull_SB_DFFESR_Q_E
+.sym 8599 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 8600 w_rx_24_fifo_pulled_data[7]
+.sym 8601 $nextpnr_ICESTORM_LC_5$O
+.sym 8604 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8607 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[2]
+.sym 8609 smi_ctrl_ins.int_cnt_09[4]
+.sym 8610 $PACKER_VCC_NET
+.sym 8611 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8614 $PACKER_VCC_NET
+.sym 8615 smi_ctrl_ins.int_cnt_09[5]
+.sym 8617 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[2]
+.sym 8620 i_smi_a1_SB_LUT4_I2_O[2]
+.sym 8621 w_rx_09_fifo_pulled_data[0]
+.sym 8623 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 8626 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 8627 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 8628 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 8629 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 8632 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 8633 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 8634 w_rx_24_fifo_pulled_data[15]
+.sym 8635 w_rx_24_fifo_pulled_data[7]
+.sym 8638 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2_SB_LUT4_O_I1[2]
+.sym 8639 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 8641 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 8644 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2]
+.sym 8645 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 8646 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 8647 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1]
+.sym 8648 smi_ctrl_ins.r_fifo_09_pull_SB_DFFESR_Q_E
+.sym 8649 i_glob_clock$SB_IO_IN_$glb_clk
+.sym 8650 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 8652 w_smi_data_output[4]
+.sym 8653 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E
+.sym 8654 smi_ctrl_ins.r_fifo_09_pull_SB_DFFESR_Q_E
+.sym 8655 i_smi_a1_SB_LUT4_I3_I0_SB_CARRY_CO_I1[5]
+.sym 8656 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2_SB_LUT4_O_I1[0]
+.sym 8657 i_smi_a1_SB_LUT4_I3_I0_SB_CARRY_CO_I1[4]
+.sym 8658 w_smi_data_output[3]
+.sym 8663 io_pmod[4]$SB_IO_IN
+.sym 8664 w_smi_data_output[7]
+.sym 8668 w_smi_data_output[6]
+.sym 8673 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 8679 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 8681 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 8683 io_pmod[2]$SB_IO_IN
+.sym 8686 smi_ctrl_ins.int_cnt_24_SB_DFFESR_Q_E
+.sym 8694 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 8695 $PACKER_VCC_NET
+.sym 8696 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8697 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 8698 w_rx_24_fifo_pulled_data[6]
+.sym 8701 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 8703 $PACKER_VCC_NET
+.sym 8706 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 8707 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 8708 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 8709 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 8710 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E
+.sym 8713 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 8714 smi_ctrl_ins.int_cnt_24[4]
+.sym 8716 smi_ctrl_ins.int_cnt_24[5]
+.sym 8718 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 8721 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 8722 w_rx_24_fifo_pulled_data[14]
+.sym 8724 $nextpnr_ICESTORM_LC_2$O
+.sym 8727 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 8730 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[2]
+.sym 8732 smi_ctrl_ins.int_cnt_24[4]
+.sym 8733 $PACKER_VCC_NET
+.sym 8738 smi_ctrl_ins.int_cnt_24[5]
+.sym 8739 $PACKER_VCC_NET
+.sym 8740 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[2]
+.sym 8743 w_rx_24_fifo_pulled_data[14]
+.sym 8744 w_rx_24_fifo_pulled_data[6]
+.sym 8745 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 8746 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 8749 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 8750 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 8751 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 8752 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 8755 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 8756 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 8757 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 8761 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 8762 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 8764 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 8771 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E
+.sym 8772 i_glob_clock$SB_IO_IN_$glb_clk
+.sym 8773 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 8776 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_O_I1[5]
+.sym 8777 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[0]
+.sym 8778 i_smi_a1_SB_LUT4_I3_O[0]
+.sym 8779 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 8780 smi_ctrl_ins.int_cnt_24[4]
+.sym 8781 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E_SB_LUT4_O_I1[0]
+.sym 8782 i_smi_a2_SB_LUT4_I2_O_SB_LUT4_I0_O
+.sym 8788 rx_09_fifo.rd_addr_gray_wr_r[5]
+.sym 8790 rx_09_fifo.rd_addr_gray_wr_r[3]
+.sym 8791 w_smi_data_output[3]
+.sym 8798 i_button_SB_LUT4_I3_I2[0]
+.sym 8799 w_rx_09_fifo_push
+.sym 8801 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 8804 w_rx_09_fifo_full
+.sym 8817 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E
+.sym 8819 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 8821 $PACKER_VCC_NET
+.sym 8826 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_CARRY_CO_CI[5]
+.sym 8828 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_O_I1[0]
+.sym 8832 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1[4]
+.sym 8836 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 8837 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_CARRY_CO_CI[3]
+.sym 8839 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 8840 w_rx_24_fifo_pulled_data[28]
+.sym 8841 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 8842 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 8843 w_rx_24_fifo_pulled_data[20]
+.sym 8847 $nextpnr_ICESTORM_LC_0$O
+.sym 8850 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_CARRY_CO_CI[3]
+.sym 8853 i_smi_a2_SB_LUT4_I2_I1[4]
+.sym 8856 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1[4]
+.sym 8859 $nextpnr_ICESTORM_LC_1$I3
+.sym 8862 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_CARRY_CO_CI[5]
+.sym 8865 $nextpnr_ICESTORM_LC_1$COUT
+.sym 8867 $PACKER_VCC_NET
+.sym 8869 $nextpnr_ICESTORM_LC_1$I3
+.sym 8873 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 8874 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_O_I1[0]
+.sym 8875 $nextpnr_ICESTORM_LC_1$COUT
+.sym 8878 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 8880 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 8881 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 8885 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 8890 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 8891 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 8892 w_rx_24_fifo_pulled_data[20]
+.sym 8893 w_rx_24_fifo_pulled_data[28]
+.sym 8894 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E
+.sym 8895 i_glob_clock$SB_IO_IN_$glb_clk
+.sym 8896 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 8898 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1[4]
+.sym 8899 w_tx_data_smi[1]
+.sym 8900 w_tx_data_smi[0]
+.sym 8901 w_tx_data_smi[3]
+.sym 8902 smi_ctrl_ins.int_cnt_24_SB_DFFESR_Q_E
+.sym 8903 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[1]
+.sym 8904 i_smi_a1_SB_LUT4_I1_O[3]
+.sym 8917 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_O_I1[2]
+.sym 8921 i_smi_a2$SB_IO_IN
+.sym 8922 w_rx_24_fifo_pull
+.sym 8926 i_smi_a3$SB_IO_IN
+.sym 8928 rx_24_fifo.rd_addr[6]
+.sym 8929 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 8930 rx_24_fifo.rd_addr[2]
+.sym 8940 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1[5]
+.sym 8941 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_O_I1[2]
+.sym 8942 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 8944 smi_ctrl_ins.int_cnt_24[4]
+.sym 8945 w_rx_24_fifo_empty
+.sym 8949 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_CARRY_CO_CI[5]
+.sym 8950 smi_ctrl_ins.int_cnt_24[5]
+.sym 8951 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 8952 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 8953 w_rx_24_fifo_pulled_data[23]
+.sym 8955 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1[4]
+.sym 8956 smi_ctrl_ins.int_cnt_24_SB_DFFESR_Q_E
+.sym 8960 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 8961 w_rx_24_fifo_pulled_data[31]
+.sym 8964 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 8970 $nextpnr_ICESTORM_LC_17$O
+.sym 8972 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1[4]
+.sym 8976 $nextpnr_ICESTORM_LC_18$I3
+.sym 8978 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_CARRY_CO_CI[5]
+.sym 8986 $nextpnr_ICESTORM_LC_18$I3
+.sym 8989 smi_ctrl_ins.int_cnt_24[5]
+.sym 8995 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 8996 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 8997 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 9001 smi_ctrl_ins.int_cnt_24[5]
+.sym 9002 smi_ctrl_ins.int_cnt_24[4]
+.sym 9003 w_rx_24_fifo_empty
+.sym 9004 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 9007 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1[5]
+.sym 9008 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 9009 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 9010 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_O_I1[2]
+.sym 9013 w_rx_24_fifo_pulled_data[31]
+.sym 9014 w_rx_24_fifo_pulled_data[23]
+.sym 9015 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 9016 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 9017 smi_ctrl_ins.int_cnt_24_SB_DFFESR_Q_E
+.sym 9018 i_glob_clock$SB_IO_IN_$glb_clk
+.sym 9019 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 9020 rx_24_fifo.empty_o_SB_LUT4_I2_I3[2]
+.sym 9021 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0[2]
+.sym 9022 rx_24_fifo.rd_addr[0]
+.sym 9023 smi_ctrl_ins.r_fifo_24_pull_SB_LUT4_I3_I0[0]
+.sym 9024 rx_24_fifo.rd_addr[3]
+.sym 9025 rx_24_fifo.rd_addr[5]
+.sym 9026 rx_24_fifo.rd_addr[7]
+.sym 9027 rx_24_fifo.rd_addr[1]
+.sym 9039 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 9041 w_rx_24_fifo_empty
+.sym 9044 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
+.sym 9045 rx_24_fifo.rd_addr[3]
+.sym 9049 rx_24_fifo.rd_addr[7]
+.sym 9050 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0]
+.sym 9051 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 9052 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 9054 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 9063 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0[3]
+.sym 9064 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3]
+.sym 9067 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[1]
+.sym 9068 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0]
+.sym 9069 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0[1]
+.sym 9072 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0]
+.sym 9073 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0[0]
+.sym 9075 w_rx_24_fifo_pull
+.sym 9078 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 9079 smi_ctrl_ins.r_fifo_24_pull_SB_DFFESR_Q_E
+.sym 9081 rx_24_fifo.rd_addr[3]
+.sym 9082 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 9083 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_O_I1[2]
+.sym 9084 rx_24_fifo.rd_addr[1]
+.sym 9085 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
+.sym 9086 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0[2]
+.sym 9087 rx_24_fifo.rd_addr[0]
+.sym 9089 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 9090 rx_24_fifo.rd_addr[2]
+.sym 9091 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 9100 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0[1]
+.sym 9101 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0[3]
+.sym 9102 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0[0]
+.sym 9103 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0[2]
+.sym 9106 rx_24_fifo.rd_addr[2]
+.sym 9107 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0]
+.sym 9108 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0]
+.sym 9109 rx_24_fifo.rd_addr[1]
+.sym 9112 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 9114 rx_24_fifo.rd_addr[0]
+.sym 9118 rx_24_fifo.rd_addr[3]
+.sym 9119 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3]
+.sym 9120 rx_24_fifo.rd_addr[2]
+.sym 9121 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
+.sym 9124 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 9126 w_rx_24_fifo_pull
+.sym 9131 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 9132 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_O_I1[2]
+.sym 9133 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 9137 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[1]
+.sym 9138 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 9140 smi_ctrl_ins.r_fifo_24_pull_SB_DFFESR_Q_E
+.sym 9141 i_glob_clock$SB_IO_IN_$glb_clk
+.sym 9142 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 9144 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 9145 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 9146 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 9147 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[4]
+.sym 9148 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 9149 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 9150 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[7]
+.sym 9157 smi_ctrl_ins.r_fifo_24_pull_SB_LUT4_I3_1_O
+.sym 9159 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O[3]
+.sym 9160 rx_24_fifo.rd_addr[1]
+.sym 9161 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.sym 9166 rx_24_fifo.rd_addr[0]
+.sym 9167 rx_24_fifo.rd_addr[0]
+.sym 9168 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 9169 w_rx_24_fifo_empty
+.sym 9171 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 9174 smi_ctrl_ins.r_fifo_24_pull_SB_LUT4_I3_1_O
+.sym 9177 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 9185 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
+.sym 9188 rx_24_fifo.rd_addr[3]
+.sym 9189 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 9190 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 9191 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2]
+.sym 9197 rx_24_fifo.rd_addr[5]
+.sym 9198 rx_24_fifo.rd_addr[6]
+.sym 9200 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[3]
+.sym 9201 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_I0[0]
+.sym 9202 w_rx_09_fifo_data[1]
+.sym 9206 rx_24_fifo.rd_addr[4]
+.sym 9208 w_lvds_rx_09_d0
+.sym 9210 w_lvds_rx_09_d1
+.sym 9211 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 9212 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[4]
+.sym 9217 rx_24_fifo.rd_addr[5]
+.sym 9218 rx_24_fifo.rd_addr[6]
+.sym 9219 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 9220 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_I0[0]
+.sym 9223 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2]
+.sym 9224 rx_24_fifo.rd_addr[4]
+.sym 9231 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[3]
+.sym 9232 w_lvds_rx_09_d0
+.sym 9236 rx_24_fifo.rd_addr[3]
+.sym 9237 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
+.sym 9238 rx_24_fifo.rd_addr[4]
+.sym 9241 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[3]
+.sym 9242 w_lvds_rx_09_d1
+.sym 9249 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 9250 w_rx_09_fifo_data[1]
+.sym 9253 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 9256 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[4]
+.sym 9263 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
 .sym 9264 lvds_clock_buf
-.sym 9265 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]_$glb_sr
-.sym 9266 w_tx_data_smi[2]
-.sym 9267 w_tx_data_smi[3]
-.sym 9268 w_tx_data_smi[0]
-.sym 9269 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
-.sym 9271 w_tx_data_smi[1]
-.sym 9288 $PACKER_GND_NET
-.sym 9290 w_rx_24_fifo_full
-.sym 9293 w_tx_data_io[0]
-.sym 9294 w_cs[2]
-.sym 9295 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
-.sym 9296 spi_if_ins.o_cs_SB_LUT4_I1_2_O
-.sym 9318 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
-.sym 9324 r_tx_data[7]
-.sym 9332 r_tx_data[4]
-.sym 9342 r_tx_data[4]
-.sym 9355 r_tx_data[7]
-.sym 9386 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 9265 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 9266 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 9267 rx_24_fifo.wr_addr_gray[6]
+.sym 9268 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 9270 rx_24_fifo.wr_addr_gray[3]
+.sym 9271 rx_24_fifo.wr_addr_gray[1]
+.sym 9272 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0]
+.sym 9273 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3]
+.sym 9291 w_rx_09_fifo_push
+.sym 9292 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1_SB_DFFNESR_Q_E
+.sym 9296 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 9297 rx_24_fifo.rd_addr[6]
+.sym 9298 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 9301 w_rx_09_fifo_full
+.sym 9313 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 9317 rx_24_fifo.wr_addr_gray_rd[1]
+.sym 9318 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0]
+.sym 9320 rx_24_fifo.wr_addr_gray_rd[4]
+.sym 9321 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 9322 rx_24_fifo.wr_addr_gray_rd[3]
+.sym 9323 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 9324 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
+.sym 9327 rx_24_fifo.wr_addr_gray[3]
+.sym 9330 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3]
+.sym 9332 w_rx_24_fifo_push
+.sym 9335 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2]
+.sym 9336 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2]
+.sym 9338 rx_24_fifo.wr_addr_gray_rd[2]
+.sym 9342 rx_24_fifo.wr_addr_gray_rd[2]
+.sym 9349 rx_24_fifo.wr_addr_gray_rd[3]
+.sym 9352 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0]
+.sym 9354 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 9355 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2]
+.sym 9360 rx_24_fifo.wr_addr_gray_rd[1]
+.sym 9364 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2]
+.sym 9365 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3]
+.sym 9366 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 9367 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
+.sym 9373 rx_24_fifo.wr_addr_gray_rd[4]
+.sym 9377 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 9378 w_rx_24_fifo_push
+.sym 9385 rx_24_fifo.wr_addr_gray[3]
 .sym 9387 r_counter[0]_$glb_clk
-.sym 9389 r_tx_data[2]
-.sym 9390 r_tx_data[7]
-.sym 9391 smi_ctrl_ins.o_data_out_SB_LUT4_I2_I3[2]
-.sym 9392 r_tx_data[5]
-.sym 9393 r_tx_data[3]
-.sym 9394 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[1]
-.sym 9395 r_tx_data[1]
-.sym 9420 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
-.sym 9421 spi_if_ins.w_rx_data[6]
-.sym 9432 w_tx_data_smi[0]
-.sym 9434 spi_if_ins.o_cs_SB_LUT4_I0_O[2]
-.sym 9439 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
-.sym 9441 smi_ctrl_ins.o_data_out_SB_LUT4_I2_I3[0]
-.sym 9442 w_tx_data_sys[0]
-.sym 9444 spi_if_ins.o_cs_SB_LUT4_I1_O[2]
-.sym 9453 w_tx_data_io[0]
-.sym 9457 spi_if_ins.o_cs_SB_LUT4_I1_2_O
-.sym 9460 spi_if_ins.o_cs_SB_LUT4_I0_O[3]
-.sym 9481 w_tx_data_sys[0]
-.sym 9482 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
-.sym 9483 spi_if_ins.o_cs_SB_LUT4_I0_O[3]
-.sym 9484 spi_if_ins.o_cs_SB_LUT4_I0_O[2]
-.sym 9489 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
-.sym 9499 w_tx_data_smi[0]
-.sym 9500 spi_if_ins.o_cs_SB_LUT4_I1_O[2]
-.sym 9501 smi_ctrl_ins.o_data_out_SB_LUT4_I2_I3[0]
-.sym 9502 w_tx_data_io[0]
-.sym 9509 spi_if_ins.o_cs_SB_LUT4_I1_2_O
-.sym 9510 i_glob_clock$SB_IO_IN_$glb_clk
-.sym 9512 spi_if_ins.r_tx_byte[1]
-.sym 9515 spi_if_ins.r_tx_byte[2]
-.sym 9516 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
-.sym 9517 spi_if_ins.r_tx_byte[5]
-.sym 9518 spi_if_ins.r_tx_byte[3]
-.sym 9521 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R
-.sym 9537 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
-.sym 9538 spi_if_ins.w_rx_data[5]
-.sym 9539 r_tx_data[0]
-.sym 9541 r_tx_data[6]
-.sym 9542 w_cs[1]
-.sym 9544 spi_if_ins.w_rx_data[5]
-.sym 9564 spi_if_ins.w_rx_data[5]
-.sym 9566 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
-.sym 9569 w_cs[0]
-.sym 9570 spi_if_ins.w_rx_data[5]
-.sym 9571 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O
-.sym 9575 w_cs[1]
-.sym 9576 w_cs[3]
-.sym 9579 w_cs[2]
-.sym 9581 spi_if_ins.w_rx_data[6]
-.sym 9592 w_cs[3]
-.sym 9593 w_cs[0]
-.sym 9594 w_cs[2]
-.sym 9595 w_cs[1]
-.sym 9599 spi_if_ins.w_rx_data[5]
-.sym 9601 spi_if_ins.w_rx_data[6]
-.sym 9604 w_cs[2]
-.sym 9605 w_cs[1]
-.sym 9606 w_cs[3]
-.sym 9607 w_cs[0]
-.sym 9610 w_cs[0]
-.sym 9611 w_cs[3]
-.sym 9612 w_cs[1]
-.sym 9613 w_cs[2]
-.sym 9616 w_cs[3]
-.sym 9617 w_cs[1]
-.sym 9618 w_cs[2]
-.sym 9619 w_cs[0]
-.sym 9622 w_cs[1]
-.sym 9623 w_cs[3]
-.sym 9624 w_cs[0]
-.sym 9625 w_cs[2]
-.sym 9629 spi_if_ins.w_rx_data[5]
-.sym 9630 spi_if_ins.w_rx_data[6]
-.sym 9632 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O
-.sym 9633 r_counter[0]_$glb_clk
-.sym 9634 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
-.sym 9635 w_cs[0]
-.sym 9636 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
-.sym 9637 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O
-.sym 9638 spi_if_ins.o_data_in_SB_DFFE_Q_E
-.sym 9640 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E
-.sym 9651 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
-.sym 9654 $PACKER_VCC_NET
-.sym 9655 w_tx_data_io[4]
-.sym 9661 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O
-.sym 9666 spi_if_ins.o_cs_SB_LUT4_I1_2_O
-.sym 9667 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
-.sym 9670 w_fetch
-.sym 9680 w_tx_data_io[6]
-.sym 9682 spi_if_ins.o_cs_SB_LUT4_I1_O[2]
-.sym 9692 w_cs[0]
-.sym 9697 w_tx_data_io[4]
-.sym 9703 spi_if_ins.o_cs_SB_LUT4_I1_2_O
-.sym 9705 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
-.sym 9709 spi_if_ins.o_cs_SB_LUT4_I1_O[2]
-.sym 9711 w_tx_data_io[6]
-.sym 9721 spi_if_ins.o_cs_SB_LUT4_I1_O[2]
-.sym 9724 w_tx_data_io[4]
-.sym 9728 w_cs[0]
-.sym 9755 spi_if_ins.o_cs_SB_LUT4_I1_2_O
-.sym 9756 i_glob_clock$SB_IO_IN_$glb_clk
-.sym 9757 spi_if_ins.o_cs_SB_LUT4_I0_O[1]
-.sym 9758 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
-.sym 9759 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
-.sym 9760 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
-.sym 9762 spi_if_ins.o_data_in_SB_DFFE_Q_E
-.sym 9763 w_load
-.sym 9765 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O
-.sym 9776 w_rx_data[6]
-.sym 9778 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R
-.sym 9779 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
-.sym 9783 spi_if_ins.o_data_in_SB_DFFE_Q_E
-.sym 9789 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O
-.sym 9791 spi_if_ins.state_if[1]
-.sym 9807 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
-.sym 9810 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O
-.sym 9811 spi_if_ins.w_rx_data[6]
-.sym 9816 spi_if_ins.w_rx_data[5]
-.sym 9819 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
-.sym 9825 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
-.sym 9850 spi_if_ins.w_rx_data[6]
-.sym 9852 spi_if_ins.w_rx_data[5]
-.sym 9874 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
-.sym 9876 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
-.sym 9878 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O
+.sym 9390 rx_24_fifo.rd_addr_gray_wr_r[1]
+.sym 9392 rx_24_fifo.rd_addr_gray_wr[4]
+.sym 9393 rx_24_fifo.rd_addr_gray_wr[5]
+.sym 9395 rx_24_fifo.rd_addr_gray_wr_r[4]
+.sym 9396 rx_24_fifo.rd_addr_gray_wr[2]
+.sym 9403 rx_24_fifo.wr_addr_gray_rd[1]
+.sym 9406 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3]
+.sym 9407 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 9408 rx_24_fifo.wr_addr_gray_rd[4]
+.sym 9413 i_smi_a3$SB_IO_IN
+.sym 9416 rx_24_fifo.rd_addr_gray[5]
+.sym 9418 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 9420 rx_24_fifo.rd_addr[6]
+.sym 9421 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 9422 rx_24_fifo.rd_addr[2]
+.sym 9424 rx_24_fifo.rd_addr_gray_wr_r[1]
+.sym 9432 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 9434 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[0]
+.sym 9435 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O[3]
+.sym 9436 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0]
+.sym 9438 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[2]
+.sym 9440 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1]
+.sym 9442 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[0]
+.sym 9443 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 9445 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[0]
+.sym 9448 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O[0]
+.sym 9451 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[0]
+.sym 9454 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 9456 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 9458 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 9459 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 9461 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[3]
+.sym 9469 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O[3]
+.sym 9470 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 9471 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1]
+.sym 9472 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O[0]
+.sym 9475 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 9476 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 9477 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 9478 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 9481 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[2]
+.sym 9482 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[3]
+.sym 9483 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[0]
+.sym 9484 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[0]
+.sym 9487 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[0]
+.sym 9488 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[0]
+.sym 9489 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[3]
+.sym 9490 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[2]
+.sym 9493 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 9496 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0]
+.sym 9506 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[3]
+.sym 9507 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[2]
+.sym 9508 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[0]
+.sym 9510 r_counter[0]_$glb_clk
+.sym 9511 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 9512 w_rx_09_fifo_push
+.sym 9518 lvds_rx_09_inst.r_push_SB_DFFNESR_Q_E
+.sym 9526 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 9528 w_rx_24_fifo_empty
+.sym 9530 rx_24_fifo.rd_addr_gray[4]
+.sym 9532 sys_ctrl_ins.reset_cmd
+.sym 9536 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 9542 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 9543 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 9554 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[1]
+.sym 9557 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[3]
+.sym 9560 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[0]
+.sym 9561 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 9562 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1]
+.sym 9563 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[2]
+.sym 9564 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1_SB_DFFNESR_Q_E
+.sym 9565 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[0]
+.sym 9571 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[0]
+.sym 9573 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[1]
+.sym 9575 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[3]
+.sym 9579 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[0]
+.sym 9582 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 9586 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[0]
+.sym 9588 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1]
+.sym 9592 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[2]
+.sym 9593 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[3]
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-.sym 10881 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]_$glb_sr
-.sym 10882 w_rx_09_fifo_push
-.sym 10883 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[2]
-.sym 10884 rx_09_fifo.full_o_SB_LUT4_I3_O[2]
-.sym 10885 lvds_rx_09_inst.r_push_SB_LUT4_I2_O[2]
-.sym 10886 lvds_rx_09_inst.r_push_SB_LUT4_I3_O
-.sym 10887 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
-.sym 10888 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[0]
-.sym 10889 lvds_rx_09_inst.r_push_SB_LUT4_I2_I1[1]
-.sym 10904 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 10941 lvds_rx_09_inst.r_push_SB_LUT4_I3_O
-.sym 10942 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O[3]
-.sym 10943 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O[4]
-.sym 10944 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O[5]
-.sym 10949 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O[2]
-.sym 10958 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O[4]
-.sym 10974 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O[2]
-.sym 10988 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O[5]
-.sym 11000 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O[3]
-.sym 11002 lvds_rx_09_inst.r_push_SB_LUT4_I3_O
-.sym 11003 lvds_clock_buf
-.sym 11004 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]_$glb_sr
-.sym 11006 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O[1]
-.sym 11007 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O[2]
-.sym 11008 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O[3]
-.sym 11009 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O[4]
-.sym 11010 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O[5]
-.sym 11011 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O[6]
-.sym 11012 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O[7]
-.sym 11018 lvds_rx_09_inst.r_push_SB_DFFNESR_Q_E_SB_LUT4_O_I1[1]
-.sym 11029 sys_ctrl_ins.reset_cmd
-.sym 11030 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
-.sym 11036 sys_ctrl_ins.reset_cmd
-.sym 11037 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 11050 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I3[0]
-.sym 11053 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I3[2]
-.sym 11072 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I3[1]
-.sym 11115 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I3[0]
-.sym 11116 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I3[2]
-.sym 11118 rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I3[1]
-.sym 11126 r_counter[0]_$glb_clk
-.sym 11127 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]_$glb_sr
-.sym 11148 w_rx_09_fifo_full
-.sym 11171 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
-.sym 11172 sys_ctrl_ins.reset_count[3]
-.sym 11183 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
-.sym 11184 sys_ctrl_ins.reset_count[1]
-.sym 11187 sys_ctrl_ins.reset_count[2]
-.sym 11189 sys_ctrl_ins.reset_cmd
-.sym 11191 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
-.sym 11196 sys_ctrl_ins.reset_cmd
-.sym 11197 sys_ctrl_ins.reset_count[0]
-.sym 11201 $nextpnr_ICESTORM_LC_12$O
-.sym 11203 sys_ctrl_ins.reset_count[0]
-.sym 11207 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
-.sym 11209 sys_ctrl_ins.reset_count[1]
-.sym 11213 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
-.sym 11214 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
-.sym 11216 sys_ctrl_ins.reset_count[2]
-.sym 11217 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
-.sym 11220 sys_ctrl_ins.reset_count[3]
-.sym 11222 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
-.sym 11223 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
-.sym 11227 sys_ctrl_ins.reset_count[0]
-.sym 11232 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
-.sym 11235 sys_ctrl_ins.reset_cmd
-.sym 11238 sys_ctrl_ins.reset_count[2]
-.sym 11239 sys_ctrl_ins.reset_count[0]
-.sym 11240 sys_ctrl_ins.reset_count[1]
-.sym 11241 sys_ctrl_ins.reset_count[3]
-.sym 11245 sys_ctrl_ins.reset_count[1]
-.sym 11246 sys_ctrl_ins.reset_count[0]
-.sym 11247 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
-.sym 11248 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
+.sym 10223 io_smi_data[2]$SB_IO_OUT
+.sym 10224 io_smi_data[1]$SB_IO_OUT
+.sym 10226 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 10227 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0]
+.sym 10228 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O_SB_LUT4_I3_O[0]
+.sym 10229 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0[0]
+.sym 10230 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
+.sym 10231 rx_09_fifo.rd_addr[2]
+.sym 10232 rx_09_fifo.rd_addr[4]
+.sym 10233 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3]
+.sym 10269 rx_09_fifo.rd_addr[3]
+.sym 10278 rx_09_fifo.rd_addr[5]
+.sym 10283 rx_09_fifo.rd_addr[1]
+.sym 10284 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 10285 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[1]
+.sym 10286 rx_09_fifo.rd_addr[0]
+.sym 10297 rx_09_fifo.rd_addr[2]
+.sym 10298 rx_09_fifo.rd_addr[4]
+.sym 10300 $nextpnr_ICESTORM_LC_10$O
+.sym 10303 rx_09_fifo.rd_addr[0]
+.sym 10306 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[2]
+.sym 10308 rx_09_fifo.rd_addr[1]
+.sym 10310 rx_09_fifo.rd_addr[0]
+.sym 10312 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[3]
+.sym 10315 rx_09_fifo.rd_addr[2]
+.sym 10316 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[2]
+.sym 10318 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[4]
+.sym 10321 rx_09_fifo.rd_addr[3]
+.sym 10322 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[3]
+.sym 10324 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[5]
+.sym 10326 rx_09_fifo.rd_addr[4]
+.sym 10328 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[4]
+.sym 10330 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[6]
+.sym 10333 rx_09_fifo.rd_addr[5]
+.sym 10334 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[5]
+.sym 10336 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[7]
+.sym 10338 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[1]
+.sym 10340 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[6]
+.sym 10344 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 10346 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[7]
+.sym 10354 lvds_rx_09_inst.r_push_SB_LUT4_I3_1_O
+.sym 10355 rx_09_fifo.wr_addr_gray_rd_r[1]
+.sym 10356 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[2]
+.sym 10357 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[2]
+.sym 10358 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[0]
+.sym 10359 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
+.sym 10360 rx_09_fifo.wr_addr_gray_rd[5]
+.sym 10361 rx_09_fifo.wr_addr_gray_rd[1]
+.sym 10367 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
+.sym 10368 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[5]
+.sym 10370 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 10371 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3]
+.sym 10373 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 10385 io_smi_data[7]$SB_IO_OUT
+.sym 10392 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 10396 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1]
+.sym 10405 rx_09_fifo.wr_addr[0]
+.sym 10413 io_smi_data[0]$SB_IO_OUT
+.sym 10417 rx_09_fifo.rd_addr[4]
+.sym 10424 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 10425 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[1]
+.sym 10432 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 10433 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 10436 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[5]
+.sym 10437 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 10441 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 10442 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 10445 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[6]
+.sym 10446 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[7]
+.sym 10451 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[0]
+.sym 10452 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[3]
+.sym 10453 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_O[0]
+.sym 10455 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_O[1]
+.sym 10456 rx_09_fifo.wr_addr_gray_rd_r[1]
+.sym 10460 i_smi_a1_SB_LUT4_I3_O[1]
+.sym 10464 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[0]
+.sym 10465 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[6]
+.sym 10466 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[7]
+.sym 10467 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[3]
+.sym 10471 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 10477 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[5]
+.sym 10483 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_O[0]
+.sym 10484 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_O[1]
+.sym 10488 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 10490 i_smi_a1_SB_LUT4_I3_O[1]
+.sym 10500 i_smi_a1_SB_LUT4_I3_O[1]
+.sym 10501 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 10502 rx_09_fifo.wr_addr_gray_rd_r[1]
+.sym 10503 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 10508 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 10510 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 10511 r_counter[0]_$glb_clk
+.sym 10512 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 10514 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1]
+.sym 10515 rx_09_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 10516 rx_09_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 10517 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4]
+.sym 10518 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5]
+.sym 10519 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6]
+.sym 10520 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7]
+.sym 10523 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 10526 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 10528 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 10529 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 10533 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
+.sym 10535 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 10537 rx_09_fifo.wr_addr[0]
+.sym 10538 rx_09_fifo.wr_addr_gray_rd[7]
+.sym 10539 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 10540 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1[3]
+.sym 10542 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 10543 w_rx_09_fifo_push
+.sym 10545 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 10548 $PACKER_VCC_NET
+.sym 10554 w_smi_data_output[1]
+.sym 10556 rx_09_fifo.rd_addr[5]
+.sym 10557 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 10558 rx_09_fifo.wr_addr[0]
+.sym 10559 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 10560 w_rx_09_fifo_pulled_data[16]
+.sym 10561 w_rx_09_fifo_pulled_data[26]
+.sym 10563 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1]
+.sym 10566 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[0]
+.sym 10567 w_rx_09_fifo_pulled_data[10]
+.sym 10568 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O[3]
+.sym 10569 io_pmod[2]$SB_IO_IN
+.sym 10571 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1]
+.sym 10572 i_smi_a3$SB_IO_IN
+.sym 10575 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 10576 i_smi_a1_SB_LUT4_I3_O[1]
+.sym 10578 w_rx_09_fifo_pulled_data[0]
+.sym 10579 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 10581 lvds_rx_09_inst.r_push_SB_LUT4_I3_1_O
+.sym 10582 rx_09_fifo.rd_addr[4]
+.sym 10583 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 10587 rx_09_fifo.wr_addr[0]
+.sym 10590 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1]
+.sym 10593 rx_09_fifo.rd_addr[4]
+.sym 10594 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1]
+.sym 10595 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O[3]
+.sym 10596 rx_09_fifo.rd_addr[5]
+.sym 10599 w_rx_09_fifo_pulled_data[10]
+.sym 10600 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 10601 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 10602 w_rx_09_fifo_pulled_data[26]
+.sym 10606 w_smi_data_output[1]
+.sym 10608 i_smi_a3$SB_IO_IN
+.sym 10613 rx_09_fifo.wr_addr[0]
+.sym 10623 io_pmod[2]$SB_IO_IN
+.sym 10624 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[0]
+.sym 10625 i_smi_a1_SB_LUT4_I3_O[1]
+.sym 10626 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 10629 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 10630 w_rx_09_fifo_pulled_data[16]
+.sym 10631 w_rx_09_fifo_pulled_data[0]
+.sym 10632 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 10633 lvds_rx_09_inst.r_push_SB_LUT4_I3_1_O
+.sym 10634 lvds_clock_buf
+.sym 10635 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 10636 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1[1]
+.sym 10637 w_rx_09_fifo_full
+.sym 10638 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[2]
+.sym 10639 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
+.sym 10640 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2[2]
+.sym 10641 rx_09_fifo.full_o_SB_LUT4_I3_O[3]
+.sym 10642 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 10643 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3]
+.sym 10647 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 10652 rx_09_fifo.wr_addr[4]
+.sym 10654 rx_09_fifo.wr_addr[6]
+.sym 10657 io_pmod[2]$SB_IO_IN
+.sym 10667 lvds_rx_09_inst.r_push_SB_LUT4_I3_1_O
+.sym 10679 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 10680 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 10681 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1[3]
+.sym 10683 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_2_D_SB_LUT4_O_I1[3]
+.sym 10684 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
+.sym 10686 i_smi_a3$SB_IO_IN
+.sym 10687 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1[1]
+.sym 10689 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1[3]
+.sym 10690 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1[1]
+.sym 10692 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[3]
+.sym 10693 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1[1]
+.sym 10695 i_smi_a2_SB_LUT4_I2_O_SB_LUT4_I0_O
+.sym 10696 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[1]
+.sym 10700 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1[3]
+.sym 10703 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_2_D_SB_LUT4_O_I1[1]
+.sym 10704 w_smi_data_output[2]
+.sym 10706 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2]
+.sym 10707 i_smi_a1_SB_LUT4_I2_O[2]
+.sym 10708 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
+.sym 10710 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 10711 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1[3]
+.sym 10712 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1[1]
+.sym 10713 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 10722 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
+.sym 10723 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
+.sym 10724 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2]
+.sym 10725 i_smi_a1_SB_LUT4_I2_O[2]
+.sym 10728 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 10729 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 10730 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1[1]
+.sym 10731 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1[3]
+.sym 10734 w_smi_data_output[2]
+.sym 10736 i_smi_a3$SB_IO_IN
+.sym 10740 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_2_D_SB_LUT4_O_I1[1]
+.sym 10741 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 10742 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 10743 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_2_D_SB_LUT4_O_I1[3]
+.sym 10746 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1[1]
+.sym 10747 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 10748 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 10749 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1[3]
+.sym 10752 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 10753 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 10754 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[1]
+.sym 10755 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[3]
+.sym 10756 i_smi_a2_SB_LUT4_I2_O_SB_LUT4_I0_O
+.sym 10757 i_glob_clock$SB_IO_IN_$glb_clk
+.sym 10760 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[2]
+.sym 10761 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E_SB_LUT4_O_I1[1]
+.sym 10762 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2[1]
+.sym 10763 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1[2]
+.sym 10764 rx_09_fifo.rd_addr_gray_wr_r[7]
+.sym 10765 i_smi_a2_SB_LUT4_I2_O_SB_LUT4_I0_O
+.sym 10766 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
+.sym 10771 w_rx_09_fifo_push
+.sym 10773 w_smi_data_output[5]
+.sym 10780 w_rx_09_fifo_full
+.sym 10784 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 10789 i_smi_a2$SB_IO_IN
+.sym 10792 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2]
+.sym 10803 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 10804 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1[3]
+.sym 10805 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
+.sym 10809 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_4_D_SB_LUT4_O_I1[3]
+.sym 10810 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
+.sym 10811 i_smi_a2_SB_LUT4_I2_O_SB_LUT4_I0_O
+.sym 10813 smi_ctrl_ins.int_cnt_09[4]
+.sym 10814 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 10815 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E_SB_LUT4_O_I1[0]
+.sym 10817 io_pmod[2]$SB_IO_IN
+.sym 10818 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 10819 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 10821 smi_ctrl_ins.int_cnt_09[5]
+.sym 10826 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E_SB_LUT4_O_I1[1]
+.sym 10829 smi_ctrl_ins.int_cnt_09[5]
+.sym 10839 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
+.sym 10840 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1[3]
+.sym 10841 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 10842 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 10846 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 10847 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E_SB_LUT4_O_I1[0]
+.sym 10848 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E_SB_LUT4_O_I1[1]
+.sym 10851 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 10853 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E_SB_LUT4_O_I1[1]
+.sym 10858 smi_ctrl_ins.int_cnt_09[5]
+.sym 10863 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 10864 smi_ctrl_ins.int_cnt_09[5]
+.sym 10865 io_pmod[2]$SB_IO_IN
+.sym 10866 smi_ctrl_ins.int_cnt_09[4]
+.sym 10871 smi_ctrl_ins.int_cnt_09[4]
+.sym 10875 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 10876 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_4_D_SB_LUT4_O_I1[3]
+.sym 10877 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
+.sym 10878 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 10879 i_smi_a2_SB_LUT4_I2_O_SB_LUT4_I0_O
+.sym 10880 i_glob_clock$SB_IO_IN_$glb_clk
+.sym 10885 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2_SB_LUT4_O_I1[2]
+.sym 10886 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2[2]
+.sym 10887 spi_if_ins.r_tx_data_valid
+.sym 10888 i_smi_a1_SB_LUT4_I3_O[3]
+.sym 10894 io_smi_data[4]$SB_IO_OUT
+.sym 10898 w_smi_data_output[4]
+.sym 10902 i_smi_a1_SB_LUT4_I3_O[1]
+.sym 10912 $PACKER_VCC_NET
+.sym 10915 w_tx_data_smi[1]
+.sym 10916 rx_24_fifo.wr_addr[7]
+.sym 10925 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 10926 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_O_I1[2]
+.sym 10927 i_smi_a1_SB_LUT4_I3_I0_SB_CARRY_CO_I1[5]
+.sym 10928 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 10937 i_smi_a1_SB_LUT4_I3_I0_SB_CARRY_CO_I1[4]
+.sym 10941 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_O_I1[5]
+.sym 10942 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2_SB_LUT4_O_I1[2]
+.sym 10943 i_smi_a2$SB_IO_IN
+.sym 10944 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 10945 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 10950 smi_ctrl_ins.int_cnt_24_SB_DFFESR_Q_E
+.sym 10952 w_rx_24_fifo_pull
+.sym 10953 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 10955 $nextpnr_ICESTORM_LC_19$O
+.sym 10957 i_smi_a1_SB_LUT4_I3_I0_SB_CARRY_CO_I1[4]
+.sym 10961 $nextpnr_ICESTORM_LC_20$I3
+.sym 10963 i_smi_a1_SB_LUT4_I3_I0_SB_CARRY_CO_I1[5]
+.sym 10971 $nextpnr_ICESTORM_LC_20$I3
+.sym 10977 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 10980 i_smi_a2$SB_IO_IN
+.sym 10981 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 10982 w_rx_24_fifo_pull
+.sym 10983 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_O_I1[2]
+.sym 10986 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 10987 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 10988 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 10993 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 10994 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 10995 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 10998 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2_SB_LUT4_O_I1[2]
+.sym 10999 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_O_I1[5]
+.sym 11000 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 11001 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 11002 smi_ctrl_ins.int_cnt_24_SB_DFFESR_Q_E
+.sym 11003 i_glob_clock$SB_IO_IN_$glb_clk
+.sym 11004 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 11006 rx_24_fifo.wr_addr_gray_rd_r[7]
+.sym 11007 w_tx_data_smi[3]
+.sym 11008 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
+.sym 11009 rx_24_fifo.wr_addr_gray_rd[7]
+.sym 11011 i_smi_a1_SB_LUT4_I2_O[2]
+.sym 11018 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
+.sym 11020 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2_SB_LUT4_O_I1[2]
+.sym 11025 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 11034 w_rx_09_fifo_push
+.sym 11035 rx_24_fifo.rd_addr[6]
+.sym 11037 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
+.sym 11040 rx_24_fifo.wr_addr_gray_rd_r[7]
+.sym 11046 i_smi_a2$SB_IO_IN
+.sym 11050 i_button_SB_LUT4_I3_I2[0]
+.sym 11052 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[0]
+.sym 11053 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 11054 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 11056 w_rx_09_fifo_full
+.sym 11058 io_pmod[2]$SB_IO_IN
+.sym 11060 smi_ctrl_ins.int_cnt_24[4]
+.sym 11064 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.sym 11065 i_smi_a3$SB_IO_IN
+.sym 11066 i_smi_a1$SB_IO_IN
+.sym 11068 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[1]
+.sym 11069 w_rx_24_fifo_full
+.sym 11073 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 11074 i_smi_a1_SB_LUT4_I1_O[2]
+.sym 11077 i_smi_a1_SB_LUT4_I1_O[3]
+.sym 11085 smi_ctrl_ins.int_cnt_24[4]
+.sym 11092 w_rx_09_fifo_full
+.sym 11099 io_pmod[2]$SB_IO_IN
+.sym 11104 w_rx_24_fifo_full
+.sym 11109 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 11110 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[0]
+.sym 11112 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[1]
+.sym 11115 i_smi_a1_SB_LUT4_I1_O[3]
+.sym 11116 i_smi_a1_SB_LUT4_I1_O[2]
+.sym 11117 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 11118 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 11121 i_smi_a3$SB_IO_IN
+.sym 11122 i_smi_a2$SB_IO_IN
+.sym 11124 i_smi_a1$SB_IO_IN
+.sym 11125 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.sym 11126 i_glob_clock$SB_IO_IN_$glb_clk
+.sym 11127 i_button_SB_LUT4_I3_I2[0]
+.sym 11128 sys_ctrl_ins.o_data_out_SB_LUT4_I0_I2[1]
+.sym 11129 w_tx_data_smi[0]
+.sym 11131 w_cs[2]
+.sym 11132 w_cs[3]
+.sym 11134 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.sym 11135 w_cs[1]
+.sym 11146 io_pmod[2]$SB_IO_IN
+.sym 11147 i_smi_soe_se$rename$0
+.sym 11149 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 11152 rx_24_fifo.rd_addr[6]
+.sym 11154 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
+.sym 11156 w_fetch
+.sym 11159 smi_ctrl_ins.int_cnt_24_SB_DFFESR_Q_E
+.sym 11161 rx_24_fifo.wr_addr_gray_rd[6]
+.sym 11163 lvds_rx_24_inst.r_push_SB_LUT4_I3_1_O
+.sym 11169 rx_24_fifo.empty_o_SB_LUT4_I2_I3[2]
+.sym 11170 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 11172 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
+.sym 11175 rx_24_fifo.rd_addr[7]
+.sym 11178 rx_24_fifo.wr_addr_gray_rd_r[7]
+.sym 11179 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 11180 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 11182 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 11183 w_rx_24_fifo_pull
+.sym 11184 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[7]
+.sym 11186 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
+.sym 11187 rx_24_fifo.rd_addr[0]
+.sym 11191 w_rx_24_fifo_empty
+.sym 11195 rx_24_fifo.rd_addr[6]
+.sym 11196 smi_ctrl_ins.r_fifo_24_pull_SB_LUT4_I3_1_O
+.sym 11202 rx_24_fifo.wr_addr_gray_rd_r[7]
+.sym 11203 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
+.sym 11204 rx_24_fifo.rd_addr[7]
+.sym 11205 rx_24_fifo.rd_addr[6]
+.sym 11208 w_rx_24_fifo_pull
+.sym 11209 rx_24_fifo.empty_o_SB_LUT4_I2_I3[2]
+.sym 11211 w_rx_24_fifo_empty
+.sym 11214 rx_24_fifo.rd_addr[0]
+.sym 11220 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 11222 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
+.sym 11223 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 11228 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 11233 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 11240 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[7]
+.sym 11246 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 11248 smi_ctrl_ins.r_fifo_24_pull_SB_LUT4_I3_1_O
 .sym 11249 r_counter[0]_$glb_clk
-.sym 11250 sys_ctrl_ins.reset_cmd
-.sym 11253 spi_if_ins.w_rx_data[6]
-.sym 11255 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-.sym 11265 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
-.sym 11271 $PACKER_VCC_NET
-.sym 11278 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 11282 i_smi_a2_SB_LUT4_I1_O[2]
-.sym 11284 io_pmod[2]$SB_IO_IN
-.sym 11286 io_ctrl_ins.o_data_out_SB_DFFESR_Q_E
-.sym 11294 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E
-.sym 11297 $PACKER_GND_NET
-.sym 11319 sys_ctrl_ins.reset_cmd
-.sym 11321 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
-.sym 11350 $PACKER_GND_NET
-.sym 11358 sys_ctrl_ins.reset_cmd
-.sym 11371 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E
-.sym 11372 r_counter[0]_$glb_clk
-.sym 11373 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
-.sym 11376 w_ioc[3]
-.sym 11377 w_ioc[4]
-.sym 11378 w_ioc[2]
-.sym 11385 spi_if_ins.state_if_SB_DFFE_Q_E
-.sym 11388 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E
-.sym 11389 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D_SB_LUT4_I3_O
-.sym 11396 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 11397 spi_if_ins.w_rx_data[6]
-.sym 11402 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-.sym 11416 w_rx_24_fifo_empty
-.sym 11418 w_rx_09_fifo_full
-.sym 11419 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 11430 w_fetch
-.sym 11432 w_rx_24_fifo_full
-.sym 11435 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
-.sym 11436 w_cs[2]
-.sym 11442 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
-.sym 11443 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1]
-.sym 11444 io_pmod[2]$SB_IO_IN
-.sym 11449 w_rx_24_fifo_empty
-.sym 11456 w_rx_24_fifo_full
-.sym 11462 io_pmod[2]$SB_IO_IN
-.sym 11466 w_cs[2]
-.sym 11467 w_fetch
-.sym 11468 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[1]
-.sym 11469 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 11478 w_rx_09_fifo_full
-.sym 11494 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
-.sym 11495 i_glob_clock$SB_IO_IN_$glb_clk
-.sym 11496 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
-.sym 11497 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E
-.sym 11498 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2[0]
-.sym 11499 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[3]
-.sym 11500 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2]
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+.sym 11398 $PACKER_VCC_NET
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+.sym 12552 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[0]
+.sym 12558 rx_09_fifo.wr_addr_gray[5]
+.sym 12559 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 12561 rx_09_fifo.wr_addr_gray_rd[7]
+.sym 12565 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O_SB_LUT4_I3_O[1]
+.sym 12566 w_rx_09_fifo_push
+.sym 12567 rx_09_fifo.wr_addr_gray[1]
+.sym 12571 rx_09_fifo.wr_addr_gray_rd[1]
+.sym 12574 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 12576 w_rx_09_fifo_push
+.sym 12582 rx_09_fifo.wr_addr_gray_rd[1]
+.sym 12585 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 12586 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[2]
+.sym 12587 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[3]
+.sym 12588 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[0]
+.sym 12593 rx_09_fifo.rd_addr[5]
+.sym 12594 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[2]
+.sym 12598 rx_09_fifo.wr_addr_gray_rd[7]
+.sym 12603 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 12604 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O_SB_LUT4_I3_O[1]
+.sym 12606 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O_SB_LUT4_I3_O[0]
+.sym 12609 rx_09_fifo.wr_addr_gray[5]
+.sym 12616 rx_09_fifo.wr_addr_gray[1]
+.sym 12620 r_counter[0]_$glb_clk
+.sym 12622 rx_09_fifo.wr_addr_gray[4]
+.sym 12623 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2[0]
+.sym 12624 rx_09_fifo.wr_addr_gray[5]
+.sym 12625 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1[0]
+.sym 12626 rx_09_fifo.wr_addr[5]
+.sym 12627 rx_09_fifo.wr_addr[4]
+.sym 12628 rx_09_fifo.wr_addr[6]
+.sym 12629 lvds_rx_09_inst.r_push_SB_LUT4_I3_O[2]
+.sym 12634 lvds_rx_09_inst.r_push_SB_LUT4_I3_1_O
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+.sym 12640 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[2]
+.sym 12641 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[1]
+.sym 12642 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[2]
+.sym 12644 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 12646 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[2]
+.sym 12647 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 12649 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3]
+.sym 12650 rx_09_fifo.wr_addr[7]
+.sym 12651 rx_09_fifo.wr_addr[6]
+.sym 12652 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2[1]
+.sym 12656 rx_09_fifo.rd_addr_gray_wr_r[7]
+.sym 12657 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2[0]
+.sym 12664 rx_09_fifo.wr_addr[3]
+.sym 12667 rx_09_fifo.wr_addr[0]
+.sym 12675 rx_09_fifo.wr_addr[7]
+.sym 12678 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
+.sym 12680 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2[0]
+.sym 12684 rx_09_fifo.wr_addr[4]
+.sym 12691 rx_09_fifo.wr_addr[5]
+.sym 12693 rx_09_fifo.wr_addr[6]
+.sym 12695 $nextpnr_ICESTORM_LC_11$O
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+.sym 12701 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2]
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+.sym 12705 rx_09_fifo.wr_addr[0]
+.sym 12707 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3]
+.sym 12710 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
+.sym 12711 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2]
+.sym 12713 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4]
+.sym 12716 rx_09_fifo.wr_addr[3]
+.sym 12717 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3]
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+.sym 12725 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6]
+.sym 12728 rx_09_fifo.wr_addr[5]
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+.sym 12731 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7]
+.sym 12733 rx_09_fifo.wr_addr[6]
+.sym 12735 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6]
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+.sym 12745 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1]
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+.sym 12756 $PACKER_VCC_NET
+.sym 12758 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1]
+.sym 12763 io_pmod[5]$SB_IO_IN
+.sym 12771 r_tx_data[6]
+.sym 12772 $PACKER_VCC_NET
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+.sym 12787 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1]
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+.sym 12790 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1[2]
+.sym 12791 rx_09_fifo.rd_addr_gray_wr_r[7]
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+.sym 12796 rx_09_fifo.full_o_SB_LUT4_I3_O[1]
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-.sym 13219 rx_09_fifo.wr_addr[5]
-.sym 13221 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3[5]
-.sym 13223 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3[7]
-.sym 13226 rx_09_fifo.wr_addr[6]
-.sym 13227 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3[6]
-.sym 13230 rx_09_fifo.wr_addr[7]
-.sym 13233 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3[7]
-.sym 13244 spi_if_ins.w_rx_data[1]
-.sym 13259 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 13270 spi_if_ins.w_rx_data[6]
-.sym 13361 spi_if_ins.spi.r_rx_byte[1]
-.sym 13365 spi_if_ins.spi.r_rx_byte[7]
-.sym 13366 spi_if_ins.spi.r_rx_byte[6]
-.sym 13370 i_smi_a2_SB_LUT4_I1_O[2]
-.sym 13386 i_smi_a2_SB_LUT4_I1_O[0]
-.sym 13387 i_smi_a2_SB_LUT4_I1_O[2]
-.sym 13388 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 13390 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2]
-.sym 13394 spi_if_ins.spi.SCKr[2]
-.sym 13419 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 13422 spi_if_ins.spi.r_rx_byte[7]
-.sym 13431 spi_if_ins.spi.r_rx_byte[6]
-.sym 13447 spi_if_ins.spi.r_rx_byte[6]
-.sym 13459 spi_if_ins.spi.r_rx_byte[7]
-.sym 13480 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 12867 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 12868 i_smi_a1_SB_LUT4_I3_O[2]
+.sym 12869 io_smi_data[3]$SB_IO_OUT
+.sym 12870 spi_if_ins.r_tx_byte[3]
+.sym 12871 spi_if_ins.r_tx_byte[7]
+.sym 12872 io_smi_data[4]$SB_IO_OUT
+.sym 12874 spi_if_ins.r_tx_byte[5]
+.sym 12875 spi_if_ins.r_tx_byte[6]
+.sym 12881 rx_09_fifo.rd_addr_gray_wr[2]
+.sym 12889 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 12890 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[1]
+.sym 12891 $io_pmod[4]$iobuf_i
+.sym 12893 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 12896 w_fetch
+.sym 12903 i_smi_a1$SB_IO_IN
+.sym 12910 rx_09_fifo.wr_addr[0]
+.sym 12911 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[2]
+.sym 12912 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
+.sym 12913 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2[2]
+.sym 12914 rx_09_fifo.rd_addr_gray_wr_r[0]
+.sym 12915 i_smi_a1_SB_LUT4_I3_O[3]
+.sym 12916 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1[0]
+.sym 12918 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 12919 rx_09_fifo.rd_addr_gray_wr[7]
+.sym 12920 i_smi_a1_SB_LUT4_I3_O[1]
+.sym 12921 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[3]
+.sym 12922 rx_09_fifo.rd_addr_gray_wr_r[0]
+.sym 12923 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 12924 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3]
+.sym 12925 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 12927 rx_09_fifo.rd_addr_gray_wr_r[5]
+.sym 12930 i_smi_a1_SB_LUT4_I2_O[2]
+.sym 12933 i_smi_a1_SB_LUT4_I3_O[2]
+.sym 12934 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[2]
+.sym 12935 rx_09_fifo.rd_addr_gray_wr_r[3]
+.sym 12937 i_smi_a1_SB_LUT4_I3_O[0]
+.sym 12939 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 12940 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
+.sym 12948 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 12949 rx_09_fifo.rd_addr_gray_wr_r[5]
+.sym 12950 rx_09_fifo.rd_addr_gray_wr_r[3]
+.sym 12951 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[2]
+.sym 12954 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2[2]
+.sym 12955 i_smi_a1_SB_LUT4_I2_O[2]
+.sym 12956 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 12957 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 12960 rx_09_fifo.wr_addr[0]
+.sym 12961 rx_09_fifo.rd_addr_gray_wr_r[0]
+.sym 12966 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[2]
+.sym 12967 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[3]
+.sym 12968 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
+.sym 12969 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
+.sym 12974 rx_09_fifo.rd_addr_gray_wr[7]
+.sym 12978 i_smi_a1_SB_LUT4_I3_O[1]
+.sym 12979 i_smi_a1_SB_LUT4_I3_O[2]
+.sym 12980 i_smi_a1_SB_LUT4_I3_O[3]
+.sym 12981 i_smi_a1_SB_LUT4_I3_O[0]
+.sym 12984 rx_09_fifo.rd_addr_gray_wr_r[0]
+.sym 12985 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 12986 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1[0]
+.sym 12987 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3]
+.sym 12989 lvds_clock_buf
+.sym 12991 w_fetch
+.sym 12994 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 13004 spi_if_ins.r_tx_byte[5]
+.sym 13016 i_smi_a1_SB_LUT4_I2_O[2]
+.sym 13017 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+.sym 13019 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 13020 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[1]
+.sym 13022 r_tx_data[7]
+.sym 13024 i_smi_a2_SB_LUT4_I2_O_SB_LUT4_I0_O
+.sym 13034 i_smi_a2$SB_IO_IN
+.sym 13035 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[0]
+.sym 13036 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
+.sym 13037 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 13044 i_smi_a1_SB_LUT4_I3_O[0]
+.sym 13045 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 13050 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
+.sym 13051 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2_SB_LUT4_O_I1[2]
+.sym 13052 i_smi_a1_SB_LUT4_I3_I0_SB_CARRY_CO_I1[5]
+.sym 13054 i_smi_a1_SB_LUT4_I3_I0_SB_CARRY_CO_I1[4]
+.sym 13059 $PACKER_VCC_NET
+.sym 13061 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2_SB_LUT4_O_I1[0]
+.sym 13063 i_smi_a1$SB_IO_IN
+.sym 13064 $nextpnr_ICESTORM_LC_3$O
+.sym 13066 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[0]
+.sym 13070 i_smi_a1_SB_LUT4_I3_I0[4]
+.sym 13072 i_smi_a1_SB_LUT4_I3_I0_SB_CARRY_CO_I1[4]
+.sym 13076 $nextpnr_ICESTORM_LC_4$I3
+.sym 13079 i_smi_a1_SB_LUT4_I3_I0_SB_CARRY_CO_I1[5]
+.sym 13082 $nextpnr_ICESTORM_LC_4$COUT
+.sym 13084 $PACKER_VCC_NET
+.sym 13086 $nextpnr_ICESTORM_LC_4$I3
+.sym 13090 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 13091 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2_SB_LUT4_O_I1[0]
+.sym 13092 $nextpnr_ICESTORM_LC_4$COUT
+.sym 13096 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
+.sym 13101 i_smi_a2$SB_IO_IN
+.sym 13102 i_smi_a1_SB_LUT4_I3_O[0]
+.sym 13103 i_smi_a1$SB_IO_IN
+.sym 13104 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2_SB_LUT4_O_I1[2]
+.sym 13111 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
+.sym 13112 r_counter[0]_$glb_clk
+.sym 13113 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 13115 spi_if_ins.spi.r_rx_byte[6]
+.sym 13116 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E
+.sym 13117 spi_if_ins.spi.r_rx_byte[7]
+.sym 13118 spi_if_ins.state_if_SB_DFFESR_Q_1_R
+.sym 13120 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
+.sym 13121 spi_if_ins.spi.r_rx_byte[5]
+.sym 13128 spi_if_ins.r_tx_data_valid
+.sym 13133 w_fetch
+.sym 13140 r_tx_data[3]
+.sym 13147 i_smi_a1$SB_IO_IN
+.sym 13149 sys_ctrl_ins.reset_cmd
+.sym 13158 i_smi_a1$SB_IO_IN
+.sym 13166 i_smi_a2$SB_IO_IN
+.sym 13167 w_tx_data_smi[3]
+.sym 13169 rx_24_fifo.wr_addr[7]
+.sym 13176 rx_24_fifo.wr_addr_gray_rd[6]
+.sym 13177 i_smi_a3$SB_IO_IN
+.sym 13183 rx_24_fifo.wr_addr_gray_rd[7]
+.sym 13196 rx_24_fifo.wr_addr_gray_rd[7]
+.sym 13203 w_tx_data_smi[3]
+.sym 13206 rx_24_fifo.wr_addr_gray_rd[6]
+.sym 13213 rx_24_fifo.wr_addr[7]
+.sym 13224 i_smi_a3$SB_IO_IN
+.sym 13226 i_smi_a2$SB_IO_IN
+.sym 13227 i_smi_a1$SB_IO_IN
+.sym 13235 r_counter[0]_$glb_clk
+.sym 13237 r_tx_data[5]
+.sym 13238 r_tx_data[2]
+.sym 13239 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 13240 r_tx_data[7]
+.sym 13241 r_tx_data[6]
+.sym 13242 r_tx_data[1]
+.sym 13243 r_tx_data[4]
+.sym 13244 r_tx_data[3]
+.sym 13250 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 13258 i_smi_a2$SB_IO_IN
+.sym 13262 r_tx_data[6]
+.sym 13263 spi_if_ins.spi.r_rx_byte[7]
+.sym 13264 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 13269 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
+.sym 13271 $PACKER_VCC_NET
+.sym 13280 w_tx_data_smi[2]
+.sym 13282 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
+.sym 13283 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
+.sym 13284 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 13287 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_1_O[1]
+.sym 13290 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[1]
+.sym 13297 w_tx_data_smi[0]
+.sym 13303 spi_if_ins.w_rx_data[5]
+.sym 13305 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O[2]
+.sym 13306 w_tx_data_io[2]
+.sym 13307 spi_if_ins.w_rx_data[6]
+.sym 13311 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 13312 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
+.sym 13313 w_tx_data_smi[2]
+.sym 13314 w_tx_data_io[2]
+.sym 13317 w_tx_data_smi[0]
+.sym 13330 spi_if_ins.w_rx_data[6]
+.sym 13332 spi_if_ins.w_rx_data[5]
+.sym 13335 spi_if_ins.w_rx_data[6]
+.sym 13337 spi_if_ins.w_rx_data[5]
+.sym 13348 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[1]
+.sym 13349 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_1_O[1]
+.sym 13354 spi_if_ins.w_rx_data[5]
+.sym 13356 spi_if_ins.w_rx_data[6]
+.sym 13357 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O[2]
+.sym 13358 r_counter[0]_$glb_clk
+.sym 13359 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
+.sym 13360 spi_if_ins.o_cs_SB_LUT4_I2_2_O[2]
+.sym 13361 spi_if_ins.w_rx_data[5]
+.sym 13362 spi_if_ins.o_cs_SB_LUT4_I2_2_O[3]
+.sym 13363 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
+.sym 13364 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
+.sym 13365 spi_if_ins.w_rx_data[6]
+.sym 13366 spi_if_ins.state_if_SB_DFFESR_Q_1_D[1]
+.sym 13367 r_tx_data_SB_DFFE_Q_E
+.sym 13376 w_tx_data_smi[1]
+.sym 13380 w_tx_data_io[4]
+.sym 13382 w_tx_data_io[3]
+.sym 13384 w_cs[0]
+.sym 13385 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 13386 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O[2]
+.sym 13387 w_ioc[1]
+.sym 13388 w_fetch
+.sym 13389 w_tx_data_io[0]
+.sym 13391 r_tx_data_SB_DFFE_Q_E
+.sym 13393 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.sym 13394 w_tx_data_io[1]
+.sym 13395 i_smi_a1$SB_IO_IN
+.sym 13401 w_fetch
+.sym 13403 w_ioc[1]
+.sym 13404 w_cs[2]
+.sym 13405 w_cs[3]
+.sym 13407 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 13408 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[7]
+.sym 13411 rx_24_fifo.wr_addr_gray_rd_r[7]
+.sym 13412 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O[2]
+.sym 13413 w_cs[3]
+.sym 13414 w_rx_24_fifo_pull
+.sym 13416 w_cs[1]
+.sym 13421 w_cs[0]
+.sym 13422 spi_if_ins.w_rx_data[6]
+.sym 13424 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 13426 spi_if_ins.w_rx_data[5]
+.sym 13427 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
+.sym 13428 smi_ctrl_ins.r_fifo_24_pull_SB_LUT4_I3_I0[0]
+.sym 13429 w_cs[0]
+.sym 13440 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 13441 w_fetch
+.sym 13442 w_cs[2]
+.sym 13443 w_ioc[1]
+.sym 13447 spi_if_ins.w_rx_data[6]
+.sym 13448 spi_if_ins.w_rx_data[5]
+.sym 13452 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[7]
+.sym 13455 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 13461 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
+.sym 13464 w_cs[0]
+.sym 13465 w_cs[1]
+.sym 13466 w_cs[2]
+.sym 13467 w_cs[3]
+.sym 13470 w_cs[0]
+.sym 13471 w_cs[2]
+.sym 13472 w_cs[1]
+.sym 13473 w_cs[3]
+.sym 13476 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[7]
+.sym 13477 w_rx_24_fifo_pull
+.sym 13478 rx_24_fifo.wr_addr_gray_rd_r[7]
+.sym 13479 smi_ctrl_ins.r_fifo_24_pull_SB_LUT4_I3_I0[0]
+.sym 13480 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O[2]
 .sym 13481 r_counter[0]_$glb_clk
-.sym 13485 spi_if_ins.spi.SCKr[0]
-.sym 13486 spi_if_ins.spi.SCKr[2]
-.sym 13488 spi_if_ins.spi.SCKr[1]
-.sym 13490 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
-.sym 13505 spi_if_ins.state_if_SB_DFFESR_Q_D[1]
-.sym 13510 spi_if_ins.spi.SCKr[1]
-.sym 13512 io_ctrl_ins.pmod_dir_state[2]
-.sym 13513 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
-.sym 13524 spi_if_ins.w_rx_data[4]
-.sym 13532 spi_if_ins.w_rx_data[3]
-.sym 13534 spi_if_ins.w_rx_data[2]
-.sym 13551 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O
-.sym 13572 spi_if_ins.w_rx_data[3]
-.sym 13576 spi_if_ins.w_rx_data[4]
-.sym 13582 spi_if_ins.w_rx_data[2]
-.sym 13603 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O
+.sym 13483 rx_24_fifo.rd_addr_gray[4]
+.sym 13484 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
+.sym 13485 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E
+.sym 13487 rx_24_fifo.rd_addr_gray[6]
+.sym 13490 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O[2]
+.sym 13496 spi_if_ins.state_if_SB_DFFESR_Q_1_D[1]
+.sym 13500 r_tx_data_SB_DFFE_Q_E
+.sym 13501 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
+.sym 13502 $io_pmod[5]$iobuf_i
+.sym 13507 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[1]
+.sym 13511 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 13512 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1]
+.sym 13514 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O[2]
+.sym 13528 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 13529 rx_24_fifo.wr_addr_gray[1]
+.sym 13532 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 13533 rx_24_fifo.wr_addr_gray[6]
+.sym 13537 w_fetch
+.sym 13538 w_cs[1]
+.sym 13539 w_load
+.sym 13563 rx_24_fifo.wr_addr_gray[1]
+.sym 13569 w_fetch
+.sym 13570 w_cs[1]
+.sym 13571 w_load
+.sym 13581 rx_24_fifo.wr_addr_gray[6]
+.sym 13587 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 13588 w_fetch
+.sym 13589 w_cs[1]
+.sym 13593 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
 .sym 13604 r_counter[0]_$glb_clk
-.sym 13606 w_rx_data[2]
-.sym 13607 w_rx_data[0]
-.sym 13608 w_rx_data[4]
-.sym 13609 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
-.sym 13610 w_rx_data[3]
-.sym 13611 w_rx_data[1]
-.sym 13612 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 13613 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R
-.sym 13618 spi_if_ins.w_rx_data[4]
-.sym 13620 spi_if_ins.w_rx_data[2]
-.sym 13623 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
-.sym 13628 spi_if_ins.w_rx_data[3]
-.sym 13630 io_ctrl_ins.rf_mode[0]
-.sym 13632 spi_if_ins.w_rx_data[1]
-.sym 13633 w_ioc[4]
-.sym 13634 o_shdn_tx_lna$SB_IO_OUT
-.sym 13635 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
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-.sym 13639 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O
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-.sym 13649 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E
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-.sym 13656 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[1]
-.sym 13657 w_ioc[3]
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-.sym 13677 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
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-.sym 13688 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
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-.sym 13693 w_ioc[3]
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-.sym 13695 w_ioc[1]
-.sym 13698 w_ioc[3]
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-.sym 13701 w_ioc[2]
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-.sym 13718 w_ioc[2]
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+.sym 13636 sys_ctrl_ins.reset_cmd
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+.sym 13652 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2]
+.sym 13656 w_cs[0]
+.sym 13660 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R
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+.sym 13676 $PACKER_VCC_NET
+.sym 13682 w_cs[0]
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+.sym 13723 $PACKER_VCC_NET
+.sym 13726 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E
 .sym 13727 r_counter[0]_$glb_clk
-.sym 13728 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R
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-.sym 13736 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[1]
-.sym 13748 w_rx_data[2]
-.sym 13751 io_pmod[2]$SB_IO_IN
-.sym 13753 w_rx_data[4]
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-.sym 13758 spi_if_ins.w_rx_data[6]
-.sym 13760 spi_if_ins.o_data_in_SB_DFFE_Q_E
-.sym 13770 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[2]
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-.sym 13775 o_led1$SB_IO_OUT
-.sym 13776 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 13777 i_config[0]$SB_IO_IN
-.sym 13778 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[0]
-.sym 13779 i_config[1]$SB_IO_IN
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-.sym 13793 io_ctrl_ins.led0_state_SB_LUT4_I3_O[3]
-.sym 13794 o_shdn_tx_lna$SB_IO_OUT
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-.sym 13811 o_shdn_tx_lna$SB_IO_OUT
-.sym 13812 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
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-.sym 13830 i_config[0]$SB_IO_IN
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-.sym 13852 io_ctrl_ins.led0_state_SB_LUT4_I3_O[2]
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-.sym 13877 spi_if_ins.state_if_SB_DFFESR_Q_1_R
-.sym 13878 i_smi_a2_SB_LUT4_I1_O[0]
-.sym 13879 o_shdn_rx_lna$SB_IO_OUT
-.sym 13882 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O
-.sym 13883 w_rx_data[2]
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-.sym 13886 i_smi_a2_SB_LUT4_I1_O[2]
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-.sym 13959 o_shdn_rx_lna$SB_IO_OUT
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+.sym 13728 sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R
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+.sym 13758 i_button_SB_LUT4_I3_O[1]
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+.sym 13762 $PACKER_VCC_NET
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+.sym 13842 rx_24_fifo.rd_addr_gray[1]
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+.sym 13850 lvds_clock_buf
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+.sym 13968 w_rx_data[1]
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-.sym 13982 io_ctrl_ins.rf_mode[2]
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-.sym 13993 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
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-.sym 14025 w_rx_data[4]
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-.sym 14028 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O
-.sym 14029 w_rx_data[3]
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-.sym 14067 w_rx_data[2]
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-.sym 14095 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O
+.sym 13977 io_ctrl_ins.led1_state_SB_LUT4_I3_O[2]
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+.sym 13997 w_rx_data[2]
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+.sym 14020 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R
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+.sym 14026 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[2]
+.sym 14027 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E
+.sym 14028 i_button_SB_LUT4_I3_O[1]
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+.sym 14035 o_shdn_tx_lna$SB_IO_OUT
+.sym 14045 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[3]
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+.sym 14080 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 14081 io_ctrl_ins.o_pmod[2]
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-.sym 14103 o_shdn_tx_lna$SB_IO_OUT
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-.sym 14126 io_ctrl_ins.rf_mode[0]
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-.sym 14557 w_smi_data_output[3]
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+.sym 14457 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 14459 r_tx_data[5]
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+.sym 14526 rx_09_fifo.wr_addr_gray_rd[5]
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+.sym 14532 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[5]
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+.sym 14579 $io_pmod[2]$iobuf_i
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-.sym 15470 spi_if_ins.spi.r_temp_rx_byte[5]
-.sym 15471 spi_if_ins.spi.r_temp_rx_byte[2]
-.sym 15472 spi_if_ins.spi.r_temp_rx_byte[0]
-.sym 15473 spi_if_ins.spi.r_temp_rx_byte[6]
-.sym 15474 spi_if_ins.spi.r_temp_rx_byte[4]
-.sym 15476 spi_if_ins.spi.r_temp_rx_byte[1]
-.sym 15485 $PACKER_VCC_NET
-.sym 15493 w_rx_data[2]
-.sym 15495 w_rx_data[0]
-.sym 15496 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[0]
-.sym 15500 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 15503 i_sck$SB_IO_IN
-.sym 15504 spi_if_ins.w_rx_data[1]
-.sym 15529 spi_if_ins.spi.r_temp_rx_byte[0]
-.sym 15530 spi_if_ins.spi.r_temp_rx_byte[6]
-.sym 15535 spi_if_ins.spi.r_temp_rx_byte[5]
-.sym 15537 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D_SB_LUT4_I3_O
-.sym 15549 spi_if_ins.spi.r_temp_rx_byte[0]
-.sym 15574 spi_if_ins.spi.r_temp_rx_byte[6]
-.sym 15579 spi_if_ins.spi.r_temp_rx_byte[5]
-.sym 15589 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D_SB_LUT4_I3_O
-.sym 15590 i_sck$SB_IO_IN_$glb_clk
-.sym 15592 spi_if_ins.w_rx_data[3]
-.sym 15593 spi_if_ins.w_rx_data[2]
-.sym 15596 spi_if_ins.w_rx_data[4]
-.sym 15597 spi_if_ins.w_rx_data[0]
-.sym 15598 spi_if_ins.w_rx_data[5]
-.sym 15613 i_mosi$SB_IO_IN
-.sym 15619 spi_if_ins.w_rx_data[0]
-.sym 15621 o_tr_vc2$SB_IO_OUT
-.sym 15623 w_rx_data[0]
-.sym 15635 spi_if_ins.spi.SCKr[0]
-.sym 15641 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 15646 spi_if_ins.spi.SCKr[1]
-.sym 15663 i_sck$SB_IO_IN
-.sym 15679 i_sck$SB_IO_IN
-.sym 15687 spi_if_ins.spi.SCKr[1]
-.sym 15699 spi_if_ins.spi.SCKr[0]
-.sym 15708 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 14868 lvds_rx_09_inst.r_push_SB_LUT4_I3_1_O
+.sym 14871 io_pmod[6]$SB_IO_IN
+.sym 14876 rx_09_fifo.wr_addr[5]
+.sym 14878 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
+.sym 14886 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 14895 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1]
+.sym 14899 rx_09_fifo.rd_addr_gray_wr[2]
+.sym 14902 lvds_rx_09_inst.r_push_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
+.sym 14903 rx_09_fifo.rd_addr_gray_wr_r[6]
+.sym 14905 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 14909 rx_09_fifo.rd_addr_gray_wr[0]
+.sym 14912 rx_09_fifo.full_o_SB_LUT4_I3_O[0]
+.sym 14915 lvds_rx_09_inst.r_push_SB_LUT4_I3_I1[2]
+.sym 14917 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[2]
+.sym 14921 rx_09_fifo.rd_addr_gray_wr[1]
+.sym 14923 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4]
+.sym 14924 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5]
+.sym 14925 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6]
+.sym 14926 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7]
+.sym 14928 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5]
+.sym 14929 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4]
+.sym 14937 rx_09_fifo.rd_addr_gray_wr[2]
+.sym 14941 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 14946 rx_09_fifo.full_o_SB_LUT4_I3_O[0]
+.sym 14947 lvds_rx_09_inst.r_push_SB_LUT4_I3_I1[2]
+.sym 14952 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1]
+.sym 14953 lvds_rx_09_inst.r_push_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
+.sym 14954 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[2]
+.sym 14955 rx_09_fifo.rd_addr_gray_wr_r[6]
+.sym 14960 rx_09_fifo.rd_addr_gray_wr[0]
+.sym 14965 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6]
+.sym 14966 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7]
+.sym 14970 rx_09_fifo.rd_addr_gray_wr[1]
+.sym 14975 lvds_clock_buf
+.sym 14977 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
+.sym 14979 spi_if_ins.spi.r_tx_byte[1]
+.sym 14980 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1]
+.sym 14981 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
+.sym 14982 spi_if_ins.spi.r_tx_byte[2]
+.sym 14983 spi_if_ins.spi.r_tx_byte[6]
+.sym 14984 spi_if_ins.spi.r_tx_byte[3]
+.sym 15007 rx_09_fifo.rd_addr_gray_wr[1]
+.sym 15010 sys_ctrl_ins.reset_cmd
+.sym 15011 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 15012 i_ss$SB_IO_IN
+.sym 15018 i_smi_a3$SB_IO_IN
+.sym 15026 r_tx_data[3]
+.sym 15029 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 15032 r_tx_data[6]
+.sym 15033 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 15037 r_tx_data[7]
+.sym 15039 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 15044 w_smi_data_output[4]
+.sym 15046 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 15048 w_smi_data_output[3]
+.sym 15049 r_tx_data[5]
+.sym 15051 i_smi_a3$SB_IO_IN
+.sym 15052 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 15053 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 15054 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 15057 w_smi_data_output[3]
+.sym 15058 i_smi_a3$SB_IO_IN
+.sym 15064 r_tx_data[3]
+.sym 15069 r_tx_data[7]
+.sym 15075 i_smi_a3$SB_IO_IN
+.sym 15078 w_smi_data_output[4]
+.sym 15087 r_tx_data[5]
+.sym 15093 r_tx_data[6]
+.sym 15097 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 15098 r_counter[0]_$glb_clk
+.sym 15101 spi_if_ins.r_tx_byte[2]
+.sym 15102 spi_if_ins.r_tx_byte[4]
+.sym 15103 spi_if_ins.r_tx_byte[1]
+.sym 15104 o_miso_$_TBUF__Y_E
+.sym 15105 spi_if_ins.r_tx_byte[0]
+.sym 15107 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 15111 i_smi_a1$SB_IO_IN
+.sym 15117 sys_ctrl_ins.reset_cmd
+.sym 15120 spi_if_ins.r_tx_byte[7]
+.sym 15121 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 15122 r_tx_data[3]
+.sym 15125 o_miso_$_TBUF__Y_E
+.sym 15126 r_tx_data[2]
+.sym 15132 i_ss$SB_IO_IN
+.sym 15133 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
+.sym 15134 r_tx_data[1]
+.sym 15143 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
+.sym 15145 spi_if_ins.state_if_SB_DFFESR_Q_1_R
+.sym 15146 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 15150 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
+.sym 15157 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
+.sym 15171 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 15176 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
+.sym 15177 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 15192 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 15195 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
+.sym 15220 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
+.sym 15221 r_counter[0]_$glb_clk
+.sym 15222 spi_if_ins.state_if_SB_DFFESR_Q_1_R
+.sym 15226 spi_if_ins.spi.r_temp_rx_byte[5]
+.sym 15228 spi_if_ins.spi.r_temp_rx_byte[6]
+.sym 15230 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 15238 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 15239 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E
+.sym 15240 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 15242 io_pmod[7]$SB_IO_IN
+.sym 15248 r_tx_data[4]
+.sym 15255 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 15256 spi_if_ins.state_if[1]
+.sym 15257 spi_if_ins.spi.r_rx_byte[6]
+.sym 15258 r_tx_data[0]
+.sym 15266 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 15275 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O[2]
+.sym 15277 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 15278 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+.sym 15282 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D_SB_LUT4_I3_O
+.sym 15291 spi_if_ins.spi.r_temp_rx_byte[5]
+.sym 15293 spi_if_ins.spi.r_temp_rx_byte[6]
+.sym 15295 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 15304 spi_if_ins.spi.r_temp_rx_byte[5]
+.sym 15309 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 15310 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+.sym 15311 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O[2]
+.sym 15316 spi_if_ins.spi.r_temp_rx_byte[6]
+.sym 15323 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 15333 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 15334 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+.sym 15335 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 15342 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 15343 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D_SB_LUT4_I3_O
+.sym 15344 i_sck$SB_IO_IN_$glb_clk
+.sym 15346 w_load
+.sym 15348 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D_SB_LUT4_I3_O
+.sym 15350 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
+.sym 15353 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
+.sym 15358 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 15362 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D[1]
+.sym 15363 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O[2]
+.sym 15365 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 15368 spi_if_ins.state_if_SB_DFFESR_Q_1_R
+.sym 15370 w_tx_data_io[7]
+.sym 15374 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
+.sym 15379 w_load
+.sym 15381 spi_if_ins.spi.r_rx_byte[5]
+.sym 15387 spi_if_ins.o_cs_SB_LUT4_I2_2_O[2]
+.sym 15388 w_tx_data_io[7]
+.sym 15390 w_tx_data_io[4]
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+.sym 15393 w_tx_data_io[6]
+.sym 15395 sys_ctrl_ins.o_data_out_SB_LUT4_I0_I2[1]
+.sym 15397 w_tx_data_io[5]
+.sym 15400 w_tx_data_io[3]
+.sym 15401 spi_if_ins.state_if_SB_DFFESR_Q_1_D[1]
+.sym 15402 w_tx_data_smi[1]
+.sym 15403 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
+.sym 15405 w_tx_data_smi[3]
+.sym 15408 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
+.sym 15409 w_tx_data_io[1]
+.sym 15414 r_tx_data_SB_DFFE_Q_E
+.sym 15415 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 15416 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 15417 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 15420 spi_if_ins.o_cs_SB_LUT4_I2_2_O[2]
+.sym 15421 w_tx_data_io[5]
+.sym 15423 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
+.sym 15426 sys_ctrl_ins.o_data_out_SB_LUT4_I0_I2[1]
+.sym 15427 spi_if_ins.o_cs_SB_LUT4_I2_2_O[2]
+.sym 15432 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 15433 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 15434 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
+.sym 15435 spi_if_ins.state_if_SB_DFFESR_Q_1_D[1]
+.sym 15438 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
+.sym 15439 spi_if_ins.o_cs_SB_LUT4_I2_2_O[2]
+.sym 15440 w_tx_data_io[7]
+.sym 15445 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
+.sym 15446 w_tx_data_io[6]
+.sym 15450 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
+.sym 15451 w_tx_data_io[1]
+.sym 15452 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 15453 w_tx_data_smi[1]
+.sym 15457 w_tx_data_io[4]
+.sym 15459 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
+.sym 15462 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
+.sym 15463 w_tx_data_smi[3]
+.sym 15464 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 15465 w_tx_data_io[3]
+.sym 15466 r_tx_data_SB_DFFE_Q_E
+.sym 15467 i_glob_clock$SB_IO_IN_$glb_clk
+.sym 15468 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
+.sym 15469 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
+.sym 15474 r_tx_data[0]
+.sym 15479 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
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+.sym 15485 w_tx_data_io[5]
+.sym 15486 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+.sym 15489 w_tx_data_io[6]
+.sym 15494 sys_ctrl_ins.reset_cmd
+.sym 15495 spi_if_ins.w_rx_data[6]
+.sym 15497 spi_if_ins.state_if_SB_DFFESR_Q_1_D[1]
+.sym 15498 rx_24_fifo.rd_addr_gray[4]
+.sym 15499 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 15504 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 15516 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 15517 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
+.sym 15521 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 15522 w_cs[0]
+.sym 15523 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
+.sym 15524 spi_if_ins.spi.r_rx_byte[7]
+.sym 15527 w_tx_data_smi[0]
+.sym 15529 spi_if_ins.spi.r_rx_byte[6]
+.sym 15530 w_cs[3]
+.sym 15533 w_cs[1]
+.sym 15537 w_cs[2]
+.sym 15538 w_tx_data_io[0]
+.sym 15541 spi_if_ins.spi.r_rx_byte[5]
+.sym 15543 w_cs[3]
+.sym 15544 w_cs[1]
+.sym 15545 w_cs[2]
+.sym 15546 w_cs[0]
+.sym 15552 spi_if_ins.spi.r_rx_byte[5]
+.sym 15555 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
+.sym 15556 w_tx_data_io[0]
+.sym 15557 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
+.sym 15558 w_tx_data_smi[0]
+.sym 15563 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
+.sym 15567 w_cs[2]
+.sym 15568 w_cs[0]
+.sym 15569 w_cs[3]
+.sym 15570 w_cs[1]
+.sym 15573 spi_if_ins.spi.r_rx_byte[6]
+.sym 15582 spi_if_ins.spi.r_rx_byte[7]
+.sym 15585 w_cs[0]
+.sym 15586 w_cs[2]
+.sym 15587 w_cs[1]
+.sym 15588 w_cs[3]
+.sym 15589 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 15590 r_counter[0]_$glb_clk
+.sym 15592 spi_if_ins.w_rx_data[1]
+.sym 15594 spi_if_ins.w_rx_data[0]
+.sym 15595 spi_if_ins.w_rx_data[4]
+.sym 15596 spi_if_ins.w_rx_data[3]
+.sym 15598 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E
+.sym 15599 spi_if_ins.w_rx_data[2]
+.sym 15603 i_smi_a1$SB_IO_IN
+.sym 15607 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 15609 spi_if_ins.state_if[0]
+.sym 15614 w_tx_data_sys[0]
+.sym 15618 smi_ctrl_ins.r_fifo_24_pull_SB_LUT4_I3_1_O
+.sym 15622 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
+.sym 15633 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
+.sym 15639 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[1]
+.sym 15641 w_fetch
+.sym 15644 smi_ctrl_ins.r_fifo_24_pull_SB_LUT4_I3_1_O
+.sym 15647 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 15649 w_load
+.sym 15653 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1]
+.sym 15660 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
+.sym 15661 w_cs[0]
+.sym 15663 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3]
+.sym 15664 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 15669 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3]
+.sym 15672 w_fetch
+.sym 15674 w_cs[0]
+.sym 15675 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[1]
+.sym 15678 w_load
+.sym 15679 w_cs[0]
+.sym 15680 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1]
+.sym 15681 w_fetch
+.sym 15690 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
+.sym 15708 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 15709 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
+.sym 15711 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 15712 smi_ctrl_ins.r_fifo_24_pull_SB_LUT4_I3_1_O
 .sym 15713 r_counter[0]_$glb_clk
-.sym 15715 $PACKER_GND_NET
-.sym 15718 w_tx_data_io[6]
-.sym 15720 w_tx_data_io[5]
-.sym 15721 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[2]
-.sym 15722 w_tx_data_io[7]
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-.sym 15744 w_rx_data[6]
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-.sym 15748 $PACKER_GND_NET
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+.sym 15728 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E
+.sym 15730 spi_if_ins.state_if[1]
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+.sym 15835 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O[2]
 .sym 15836 r_counter[0]_$glb_clk
-.sym 15838 io_ctrl_ins.pmod_dir_state[5]
-.sym 15839 io_ctrl_ins.pmod_dir_state[3]
-.sym 15840 i_button_SB_LUT4_I3_O[1]
-.sym 15841 io_ctrl_ins.pmod_dir_state[2]
-.sym 15842 io_ctrl_ins.pmod_dir_state[4]
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-.sym 15844 io_ctrl_ins.pmod_dir_state[7]
-.sym 15845 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O[3]
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-.sym 15851 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2]
-.sym 15852 w_rx_data[1]
-.sym 15853 $PACKER_VCC_NET
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-.sym 15864 w_tx_data_io[6]
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-.sym 15871 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
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-.sym 15880 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
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-.sym 15906 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O
-.sym 15909 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I3[2]
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-.sym 15932 i_button$SB_IO_IN
-.sym 15933 io_ctrl_ins.o_pmod[7]
-.sym 15936 io_ctrl_ins.pmod_dir_state[3]
-.sym 15937 o_tr_vc2$SB_IO_OUT
-.sym 15938 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[1]
-.sym 15939 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 15942 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
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-.sym 15945 io_ctrl_ins.o_pmod[5]
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-.sym 15949 w_ioc[1]
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-.sym 15958 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O
+.sym 15838 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.sym 15839 spi_if_ins.o_load_cmd_SB_LUT4_I2_O_SB_LUT4_I2_O
+.sym 15840 io_ctrl_ins.led1_state_SB_DFFESR_Q_E
+.sym 15841 i_button_SB_LUT4_I3_I2[0]
+.sym 15842 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_I2_SB_LUT4_I2_O
+.sym 15843 o_led1$SB_IO_OUT
+.sym 15844 o_led0$SB_IO_OUT
+.sym 15845 i_button_SB_LUT4_I3_I2[2]
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+.sym 15866 i_button_SB_LUT4_I3_O[1]
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+.sym 15887 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0]
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+.sym 15890 smi_ctrl_ins.r_fifo_24_pull_SB_LUT4_I3_1_O
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+.sym 15937 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0]
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-.sym 15967 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
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-.sym 15976 io_ctrl_ins.pmod_dir_state[2]
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-.sym 16005 w_rx_data[5]
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-.sym 16036 io_ctrl_ins.debug_mode[0]
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-.sym 16060 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 16061 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[0]
-.sym 16068 w_rx_data[1]
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-.sym 16078 io_ctrl_ins.mixer_en_state
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-.sym 16080 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
-.sym 16081 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O
+.sym 15960 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
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+.sym 15974 o_led0$SB_IO_OUT
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+.sym 16030 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
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+.sym 16050 i_button_SB_LUT4_I3_I2[0]
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+.sym 16060 i_button_SB_LUT4_I3_I2[0]
+.sym 16061 io_ctrl_ins.debug_mode[1]
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+.sym 16080 io_ctrl_ins.debug_mode[1]
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-.sym 16115 o_shdn_rx_lna$SB_IO_OUT
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-.sym 16144 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
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-.sym 16204 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O
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+.sym 16088 io_ctrl_ins.led0_state_SB_LUT4_I3_O[0]
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+.sym 16142 io_ctrl_ins.led1_state_SB_LUT4_I3_O[0]
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+.sym 16155 io_ctrl_ins.led0_state_SB_LUT4_I3_O[2]
+.sym 16170 w_ioc[0]
+.sym 16171 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 16172 o_shdn_rx_lna$SB_IO_OUT
+.sym 16173 io_ctrl_ins.o_pmod[1]
+.sym 16194 io_ctrl_ins.led0_state_SB_LUT4_I3_O[3]
+.sym 16195 io_ctrl_ins.led0_state_SB_LUT4_I3_O[0]
+.sym 16196 i_button_SB_LUT4_I3_O[1]
+.sym 16197 io_ctrl_ins.led0_state_SB_LUT4_I3_O[2]
+.sym 16200 io_ctrl_ins.led1_state_SB_LUT4_I3_O[0]
+.sym 16201 i_button_SB_LUT4_I3_O[1]
+.sym 16202 io_ctrl_ins.led1_state_SB_LUT4_I3_O[3]
+.sym 16203 io_ctrl_ins.led1_state_SB_LUT4_I3_O[2]
+.sym 16204 io_ctrl_ins.led0_state_SB_LUT4_I3_I0[0]
 .sym 16205 r_counter[0]_$glb_clk
-.sym 16206 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]_$glb_sr
-.sym 16207 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 16212 o_rx_h_tx_l_b$SB_IO_OUT
-.sym 16213 o_tr_vc2$SB_IO_OUT
-.sym 16214 o_rx_h_tx_l$SB_IO_OUT
-.sym 16221 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 16227 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 16206 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.sym 16224 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
 .sym 16236 i_button$SB_IO_IN
-.sym 16249 io_ctrl_ins.rf_pin_state[0]
-.sym 16250 io_ctrl_ins.debug_mode_SB_LUT4_I0_O
-.sym 16255 io_ctrl_ins.rf_mode[2]
-.sym 16256 io_ctrl_ins.rf_pin_state[2]
-.sym 16258 io_ctrl_ins.rf_pin_state[1]
+.sym 16248 io_ctrl_ins.rf_pin_state[1]
+.sym 16254 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
 .sym 16259 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 16261 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 16287 io_ctrl_ins.rf_pin_state[1]
-.sym 16288 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 16290 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 16311 io_ctrl_ins.rf_pin_state[2]
-.sym 16312 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 16313 io_ctrl_ins.rf_mode[2]
-.sym 16314 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 16323 io_ctrl_ins.rf_mode[2]
-.sym 16324 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 16325 io_ctrl_ins.rf_pin_state[0]
-.sym 16326 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 16327 io_ctrl_ins.debug_mode_SB_LUT4_I0_O
+.sym 16266 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
+.sym 16274 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 16278 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 16299 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 16300 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 16301 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 16302 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
+.sym 16305 io_ctrl_ins.rf_pin_state[1]
+.sym 16306 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 16308 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 16327 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
 .sym 16328 r_counter[0]_$glb_clk
 .sym 16453 i_config[3]$SB_IO_IN
 .sym 16455 i_button$SB_IO_IN
+.sym 16497 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
+.sym 16517 w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
 .sym 16523 i_smi_a3$SB_IO_IN
-.sym 16553 i_ss_SB_LUT4_I3_O
-.sym 16595 w_smi_data_output[5]
-.sym 16606 i_smi_a3$SB_IO_IN
-.sym 16618 w_smi_data_output[4]
-.sym 16640 w_smi_data_output[5]
-.sym 16642 i_smi_a3$SB_IO_IN
-.sym 16659 i_smi_a3$SB_IO_IN
-.sym 16670 w_smi_data_output[4]
-.sym 16673 i_smi_a3$SB_IO_IN
-.sym 16700 i_ss_SB_LUT4_I3_O
-.sym 16736 io_smi_data[5]$SB_IO_OUT
-.sym 16989 $io_pmod[7]$iobuf_i
-.sym 16991 io_pmod[5]$SB_IO_IN
-.sym 17007 lvds_rx_09_inst.r_data_SB_LUT4_I3_I2[0]
-.sym 17012 io_pmod[4]$SB_IO_IN
-.sym 17017 io_pmod[5]$SB_IO_IN
-.sym 17031 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 17062 io_pmod[4]$SB_IO_IN
-.sym 17064 lvds_rx_09_inst.r_data_SB_LUT4_I3_I2[0]
-.sym 17067 lvds_rx_09_inst.r_data_SB_LUT4_I3_I2[0]
-.sym 17068 io_pmod[5]$SB_IO_IN
-.sym 17083 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O
-.sym 17084 lvds_clock_buf
-.sym 17085 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]_$glb_sr
-.sym 17087 $io_pmod[2]$iobuf_i
-.sym 17094 io_pmod[4]$SB_IO_IN
-.sym 17102 i_ss$SB_IO_IN
-.sym 17103 lvds_rx_09_inst.r_data_SB_LUT4_I3_I2[0]
-.sym 17109 $PACKER_VCC_NET
-.sym 17115 $io_pmod[6]$iobuf_i
-.sym 17128 rx_09_fifo.wr_addr_gray_rd[4]
-.sym 17131 rx_09_fifo.wr_addr_gray[5]
-.sym 17132 rx_09_fifo.wr_addr_gray[0]
-.sym 17135 rx_09_fifo.wr_addr_gray_rd[5]
-.sym 17136 rx_09_fifo.wr_addr_gray[2]
-.sym 17137 rx_09_fifo.wr_addr_gray_rd_r[3]
-.sym 17145 rx_09_fifo.wr_addr_gray_rd_r[4]
-.sym 17148 rx_09_fifo.wr_addr_gray_rd_r[5]
-.sym 17149 rx_09_fifo.wr_addr_gray_rd_r[2]
-.sym 17154 rx_09_fifo.wr_addr_gray_rd[2]
-.sym 17155 rx_09_fifo.wr_addr_gray_rd[0]
-.sym 17160 rx_09_fifo.wr_addr_gray[5]
-.sym 17166 rx_09_fifo.wr_addr_gray_rd_r[3]
-.sym 17167 rx_09_fifo.wr_addr_gray_rd_r[4]
-.sym 17168 rx_09_fifo.wr_addr_gray_rd_r[5]
-.sym 17169 rx_09_fifo.wr_addr_gray_rd_r[2]
-.sym 17173 rx_09_fifo.wr_addr_gray_rd[4]
-.sym 17181 rx_09_fifo.wr_addr_gray[2]
-.sym 17187 rx_09_fifo.wr_addr_gray[0]
-.sym 17190 rx_09_fifo.wr_addr_gray_rd[5]
-.sym 17196 rx_09_fifo.wr_addr_gray_rd[2]
-.sym 17202 rx_09_fifo.wr_addr_gray_rd[0]
+.sym 16553 rx_09_fifo.rd_addr_gray[3]
+.sym 16554 rx_09_fifo.rd_addr_gray[6]
+.sym 16555 rx_09_fifo.rd_addr_gray[5]
+.sym 16556 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 16557 rx_09_fifo.rd_addr_gray[2]
+.sym 16558 rx_09_fifo.rd_addr_gray[0]
+.sym 16559 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[1]
+.sym 16560 rx_09_fifo.rd_addr_gray[4]
+.sym 16583 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
+.sym 16596 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[2]
+.sym 16597 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[3]
+.sym 16598 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 16601 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0]
+.sym 16602 rx_09_fifo.wr_addr_gray_rd[3]
+.sym 16604 rx_09_fifo.rd_addr[0]
+.sym 16605 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
+.sym 16607 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1]
+.sym 16610 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2]
+.sym 16611 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 16613 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0]
+.sym 16614 rx_09_fifo.wr_addr_gray_rd[0]
+.sym 16615 rx_09_fifo.wr_addr[7]
+.sym 16616 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 16617 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3]
+.sym 16618 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 16619 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3]
+.sym 16625 rx_09_fifo.wr_addr_gray[0]
+.sym 16628 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0]
+.sym 16629 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[2]
+.sym 16630 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[3]
+.sym 16631 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 16634 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
+.sym 16635 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2]
+.sym 16636 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3]
+.sym 16637 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 16643 rx_09_fifo.wr_addr_gray_rd[3]
+.sym 16646 rx_09_fifo.wr_addr_gray[0]
+.sym 16652 rx_09_fifo.wr_addr[7]
+.sym 16659 rx_09_fifo.rd_addr[0]
+.sym 16660 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 16665 rx_09_fifo.wr_addr_gray_rd[0]
+.sym 16670 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1]
+.sym 16671 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0]
+.sym 16672 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 16673 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3]
+.sym 16675 r_counter[0]_$glb_clk
+.sym 16681 rx_09_fifo.rd_addr_gray_wr[6]
+.sym 16682 rx_09_fifo.rd_addr_gray_wr[3]
+.sym 16684 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[0]
+.sym 16685 rx_09_fifo.rd_addr_gray_wr[2]
+.sym 16686 rx_09_fifo.rd_addr_gray_wr[4]
+.sym 16688 rx_09_fifo.rd_addr_gray_wr[5]
+.sym 16698 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[7]
+.sym 16704 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[6]
+.sym 16720 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 16724 rx_09_fifo.rd_addr_gray[0]
+.sym 16726 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1]
+.sym 16736 w_rx_09_fifo_push
+.sym 16741 w_smi_data_output[5]
+.sym 16745 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 16749 io_smi_data[4]$SB_IO_OUT
+.sym 16759 rx_09_fifo.wr_addr[3]
+.sym 16762 rx_09_fifo.wr_addr[7]
+.sym 16767 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[3]
+.sym 16773 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
+.sym 16775 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2[0]
+.sym 16777 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
+.sym 16779 rx_09_fifo.wr_addr[4]
+.sym 16780 rx_09_fifo.wr_addr[6]
+.sym 16784 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
+.sym 16785 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[0]
+.sym 16786 rx_09_fifo.wr_addr[5]
+.sym 16790 $nextpnr_ICESTORM_LC_7$O
+.sym 16792 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2[0]
+.sym 16796 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3[2]
+.sym 16798 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
+.sym 16802 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3[3]
+.sym 16804 rx_09_fifo.wr_addr[3]
+.sym 16806 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3[2]
+.sym 16808 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3[4]
+.sym 16811 rx_09_fifo.wr_addr[4]
+.sym 16812 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3[3]
+.sym 16814 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3[5]
+.sym 16816 rx_09_fifo.wr_addr[5]
+.sym 16818 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3[4]
+.sym 16820 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3[6]
+.sym 16822 rx_09_fifo.wr_addr[6]
+.sym 16824 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3[5]
+.sym 16829 rx_09_fifo.wr_addr[7]
+.sym 16830 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3[6]
+.sym 16833 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[1]
+.sym 16834 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[0]
+.sym 16835 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[2]
+.sym 16836 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0[3]
+.sym 16838 r_counter[0]_$glb_clk
+.sym 16839 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 16841 rx_09_fifo.wr_addr_gray_rd[4]
+.sym 16842 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1]
+.sym 16843 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
+.sym 16845 io_smi_data[5]$SB_IO_OUT
+.sym 16846 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+.sym 16847 spi_if_ins.spi.SCKr[0]
+.sym 16871 io_smi_data[4]$SB_IO_OUT
+.sym 16875 $io_pmod[2]$iobuf_i
+.sym 16881 rx_09_fifo.rd_addr_gray_wr[6]
+.sym 16882 rx_09_fifo.rd_addr_gray_wr_r[5]
+.sym 16883 lvds_rx_09_inst.r_push_SB_LUT4_I3_I1[2]
+.sym 16885 lvds_rx_09_inst.r_push_SB_LUT4_I3_I1[4]
+.sym 16886 rx_09_fifo.rd_addr_gray_wr[4]
+.sym 16888 rx_09_fifo.rd_addr_gray_wr[5]
+.sym 16890 rx_09_fifo.rd_addr_gray_wr[3]
+.sym 16891 rx_09_fifo.rd_addr_gray[0]
+.sym 16892 lvds_rx_09_inst.r_push_SB_LUT4_I3_I1[3]
+.sym 16894 lvds_rx_09_inst.r_push_SB_LUT4_I3_I1[5]
+.sym 16902 w_rx_09_fifo_push
+.sym 16904 lvds_rx_09_inst.r_push_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
+.sym 16909 lvds_rx_09_inst.r_push_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
+.sym 16910 rx_09_fifo.rd_addr_gray_wr_r[3]
+.sym 16914 rx_09_fifo.rd_addr_gray_wr[6]
+.sym 16922 rx_09_fifo.rd_addr_gray_wr[5]
+.sym 16926 lvds_rx_09_inst.r_push_SB_LUT4_I3_I1[5]
+.sym 16927 rx_09_fifo.rd_addr_gray_wr_r[5]
+.sym 16928 lvds_rx_09_inst.r_push_SB_LUT4_I3_I1[4]
+.sym 16929 w_rx_09_fifo_push
+.sym 16932 lvds_rx_09_inst.r_push_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
+.sym 16933 lvds_rx_09_inst.r_push_SB_LUT4_I3_I1[3]
+.sym 16934 lvds_rx_09_inst.r_push_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
+.sym 16935 lvds_rx_09_inst.r_push_SB_LUT4_I3_I1[4]
+.sym 16938 lvds_rx_09_inst.r_push_SB_LUT4_I3_I1[2]
+.sym 16940 rx_09_fifo.rd_addr_gray_wr_r[3]
+.sym 16945 rx_09_fifo.rd_addr_gray_wr[3]
+.sym 16953 rx_09_fifo.rd_addr_gray[0]
+.sym 16956 rx_09_fifo.rd_addr_gray_wr[4]
+.sym 16961 lvds_clock_buf
+.sym 16965 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 16966 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 16967 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 16968 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R
+.sym 16969 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 16970 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1]
+.sym 16975 i_sck$SB_IO_IN
+.sym 16981 i_ss$SB_IO_IN
+.sym 16984 rx_09_fifo.rd_addr_gray_wr[1]
+.sym 16989 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 17007 sys_ctrl_ins.reset_count[3]
+.sym 17017 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 17018 sys_ctrl_ins.reset_count[0]
+.sym 17024 sys_ctrl_ins.reset_count[1]
+.sym 17026 sys_ctrl_ins.reset_count[0]
+.sym 17030 sys_ctrl_ins.reset_count[2]
+.sym 17031 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
+.sym 17033 sys_ctrl_ins.reset_cmd
+.sym 17036 $nextpnr_ICESTORM_LC_16$O
+.sym 17039 sys_ctrl_ins.reset_count[0]
+.sym 17042 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
+.sym 17044 sys_ctrl_ins.reset_count[1]
+.sym 17048 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
+.sym 17049 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 17050 sys_ctrl_ins.reset_count[2]
+.sym 17052 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
+.sym 17056 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 17057 sys_ctrl_ins.reset_count[3]
+.sym 17058 sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
+.sym 17061 sys_ctrl_ins.reset_count[1]
+.sym 17063 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 17064 sys_ctrl_ins.reset_count[0]
+.sym 17067 sys_ctrl_ins.reset_count[3]
+.sym 17068 sys_ctrl_ins.reset_count[1]
+.sym 17069 sys_ctrl_ins.reset_count[2]
+.sym 17070 sys_ctrl_ins.reset_count[0]
+.sym 17075 sys_ctrl_ins.reset_count[0]
+.sym 17083 sys_ctrl_ins.reset_count_SB_DFFESR_Q_E
+.sym 17084 r_counter[0]_$glb_clk
+.sym 17085 sys_ctrl_ins.reset_cmd
+.sym 17086 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1]
+.sym 17087 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 17088 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0]
+.sym 17089 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 17090 spi_if_ins.spi.r_tx_byte[5]
+.sym 17091 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1]
+.sym 17092 spi_if_ins.spi.r_tx_byte[7]
+.sym 17093 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2]
+.sym 17104 io_pmod[4]$SB_IO_IN
+.sym 17109 i_ss$SB_IO_IN
+.sym 17110 io_pmod[2]$SB_IO_IN
+.sym 17111 i_ss$SB_IO_IN
+.sym 17113 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 17129 spi_if_ins.r_tx_byte[3]
+.sym 17130 spi_if_ins.r_tx_byte[1]
+.sym 17132 spi_if_ins.r_tx_byte[0]
+.sym 17133 sys_ctrl_ins.reset_cmd
+.sym 17136 spi_if_ins.r_tx_byte[2]
+.sym 17137 spi_if_ins.r_tx_byte[4]
+.sym 17140 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 17142 spi_if_ins.r_tx_byte[6]
+.sym 17147 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 17154 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 17160 sys_ctrl_ins.reset_cmd
+.sym 17162 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 17173 spi_if_ins.r_tx_byte[1]
+.sym 17178 spi_if_ins.r_tx_byte[4]
+.sym 17187 spi_if_ins.r_tx_byte[0]
+.sym 17191 spi_if_ins.r_tx_byte[2]
+.sym 17198 spi_if_ins.r_tx_byte[6]
+.sym 17203 spi_if_ins.r_tx_byte[3]
+.sym 17206 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
 .sym 17207 r_counter[0]_$glb_clk
-.sym 17210 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I2[2]
-.sym 17213 rx_09_fifo.wr_addr_gray_rd_r[6]
-.sym 17214 rx_09_fifo.wr_addr_gray_rd_r[7]
-.sym 17216 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I2[1]
-.sym 17244 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_E
-.sym 17250 rx_09_fifo.wr_addr_gray[3]
-.sym 17252 rx_09_fifo.wr_addr_gray[6]
-.sym 17254 rx_09_fifo.wr_addr[7]
-.sym 17256 rx_09_fifo.wr_addr_gray_rd[3]
-.sym 17261 rx_09_fifo.wr_addr_gray[4]
-.sym 17265 rx_09_fifo.wr_addr_gray[1]
-.sym 17283 rx_09_fifo.wr_addr[7]
-.sym 17290 rx_09_fifo.wr_addr_gray[4]
-.sym 17297 rx_09_fifo.wr_addr_gray_rd[3]
-.sym 17307 rx_09_fifo.wr_addr_gray[6]
-.sym 17319 rx_09_fifo.wr_addr_gray[3]
-.sym 17328 rx_09_fifo.wr_addr_gray[1]
+.sym 17208 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 17211 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 17213 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 17214 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_E
+.sym 17233 o_miso_$_TBUF__Y_E
+.sym 17240 i_mosi$SB_IO_IN
+.sym 17257 i_ss$SB_IO_IN
+.sym 17261 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
+.sym 17269 r_tx_data[2]
+.sym 17271 r_tx_data[4]
+.sym 17276 spi_if_ins.r_tx_data_valid
+.sym 17277 r_tx_data[1]
+.sym 17281 r_tx_data[0]
+.sym 17291 r_tx_data[2]
+.sym 17298 r_tx_data[4]
+.sym 17304 r_tx_data[1]
+.sym 17308 i_ss$SB_IO_IN
+.sym 17314 r_tx_data[0]
+.sym 17325 i_ss$SB_IO_IN
+.sym 17327 spi_if_ins.r_tx_data_valid
+.sym 17329 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O
 .sym 17330 r_counter[0]_$glb_clk
-.sym 17363 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D_SB_LUT4_I3_O
-.sym 17379 spi_if_ins.spi.r3_rx_done
-.sym 17380 spi_if_ins.spi.r_rx_done
-.sym 17396 spi_if_ins.spi.r2_rx_done
-.sym 17406 spi_if_ins.spi.r3_rx_done
-.sym 17407 spi_if_ins.spi.r2_rx_done
-.sym 17445 spi_if_ins.spi.r2_rx_done
-.sym 17450 spi_if_ins.spi.r_rx_done
-.sym 17453 r_counter[0]_$glb_clk
-.sym 17457 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 17458 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 17460 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_E
-.sym 17461 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D[1]
-.sym 17462 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 17466 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
-.sym 17467 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 17474 i_sck$SB_IO_IN
-.sym 17504 i_ss$SB_IO_IN
-.sym 17509 i_ss$SB_IO_IN
-.sym 17514 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_E
-.sym 17518 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D[1]
-.sym 17537 i_ss$SB_IO_IN
-.sym 17538 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D[1]
-.sym 17574 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D[1]
-.sym 17575 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_E
-.sym 17576 i_sck$SB_IO_IN_$glb_clk
-.sym 17577 i_ss$SB_IO_IN
-.sym 17578 spi_if_ins.spi.r_rx_byte[2]
-.sym 17582 spi_if_ins.spi.r_rx_byte[5]
-.sym 17583 spi_if_ins.spi.r_rx_byte[4]
-.sym 17584 spi_if_ins.spi.r_rx_byte[0]
-.sym 17585 spi_if_ins.spi.r_rx_byte[3]
-.sym 17590 i_ss$SB_IO_IN
-.sym 17597 i_ss$SB_IO_IN
-.sym 17627 spi_if_ins.spi.r_temp_rx_byte[3]
-.sym 17629 i_mosi$SB_IO_IN
-.sym 17630 i_ss_SB_LUT4_I3_O
-.sym 17632 spi_if_ins.spi.r_temp_rx_byte[4]
-.sym 17637 spi_if_ins.spi.r_temp_rx_byte[2]
-.sym 17642 spi_if_ins.spi.r_temp_rx_byte[1]
-.sym 17644 spi_if_ins.spi.r_temp_rx_byte[5]
-.sym 17646 spi_if_ins.spi.r_temp_rx_byte[0]
-.sym 17652 spi_if_ins.spi.r_temp_rx_byte[2]
-.sym 17659 spi_if_ins.spi.r_temp_rx_byte[4]
-.sym 17665 spi_if_ins.spi.r_temp_rx_byte[1]
-.sym 17670 i_mosi$SB_IO_IN
-.sym 17678 spi_if_ins.spi.r_temp_rx_byte[5]
-.sym 17684 spi_if_ins.spi.r_temp_rx_byte[3]
-.sym 17697 spi_if_ins.spi.r_temp_rx_byte[0]
-.sym 17698 i_ss_SB_LUT4_I3_O
-.sym 17699 i_sck$SB_IO_IN_$glb_clk
-.sym 17712 i_config[3]$SB_IO_IN
-.sym 17722 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D_SB_LUT4_I3_O
-.sym 17726 $PACKER_VCC_NET
-.sym 17730 $PACKER_GND_NET
-.sym 17732 spi_if_ins.o_data_in_SB_DFFE_Q_E
-.sym 17746 spi_if_ins.spi.r_rx_byte[5]
-.sym 17747 spi_if_ins.spi.r_rx_byte[4]
-.sym 17748 spi_if_ins.spi.r_rx_byte[0]
-.sym 17750 spi_if_ins.spi.r_rx_byte[2]
-.sym 17753 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
-.sym 17757 spi_if_ins.spi.r_rx_byte[3]
-.sym 17775 spi_if_ins.spi.r_rx_byte[3]
-.sym 17781 spi_if_ins.spi.r_rx_byte[2]
-.sym 17802 spi_if_ins.spi.r_rx_byte[4]
-.sym 17808 spi_if_ins.spi.r_rx_byte[0]
-.sym 17811 spi_if_ins.spi.r_rx_byte[5]
+.sym 17334 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 17335 o_miso_$_TBUF__Y_E
+.sym 17337 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D[1]
+.sym 17338 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 17350 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 17360 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 17363 $io_pmod[2]$iobuf_i
+.sym 17376 spi_if_ins.spi.r_temp_rx_byte[5]
+.sym 17395 spi_if_ins.spi.r_temp_rx_byte[3]
+.sym 17400 o_miso_$_TBUF__Y_E
+.sym 17404 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 17427 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 17436 spi_if_ins.spi.r_temp_rx_byte[5]
+.sym 17451 spi_if_ins.spi.r_temp_rx_byte[3]
+.sym 17452 o_miso_$_TBUF__Y_E
+.sym 17453 i_sck$SB_IO_IN_$glb_clk
+.sym 17455 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 17458 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 17461 spi_if_ins.spi.r_temp_rx_byte[3]
+.sym 17462 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 17467 i_ss$SB_IO_IN
+.sym 17475 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 17478 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 17479 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
+.sym 17480 i_mosi$SB_IO_IN
+.sym 17481 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 17486 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 17487 w_load
+.sym 17499 spi_if_ins.state_if[0]
+.sym 17501 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D[1]
+.sym 17503 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 17504 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
+.sym 17505 i_ss$SB_IO_IN
+.sym 17507 spi_if_ins.state_if[0]
+.sym 17509 spi_if_ins.state_if[1]
+.sym 17516 spi_if_ins.state_if_SB_DFFESR_Q_1_R
+.sym 17520 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 17523 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
+.sym 17532 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[0]
+.sym 17541 i_ss$SB_IO_IN
+.sym 17544 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D[1]
+.sym 17553 spi_if_ins.state_if[1]
+.sym 17554 spi_if_ins.state_if[0]
+.sym 17556 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 17571 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 17572 spi_if_ins.state_if[1]
+.sym 17573 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 17574 spi_if_ins.state_if[0]
+.sym 17575 spi_if_ins.o_load_cmd_SB_DFFESR_Q_E
+.sym 17576 r_counter[0]_$glb_clk
+.sym 17577 spi_if_ins.state_if_SB_DFFESR_Q_1_R
+.sym 17578 spi_if_ins.spi.r_rx_byte[0]
+.sym 17579 spi_if_ins.spi.r_rx_byte[3]
+.sym 17580 spi_if_ins.spi.r_rx_byte[1]
+.sym 17582 spi_if_ins.spi.r_rx_byte[2]
+.sym 17584 spi_if_ins.spi.r_rx_byte[4]
+.sym 17590 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.sym 17593 spi_if_ins.state_if[0]
+.sym 17598 o_miso_$_TBUF__Y_E
+.sym 17606 spi_if_ins.o_data_in_SB_DFFE_Q_E
+.sym 17609 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 17610 sys_ctrl_ins.reset_cmd
+.sym 17613 io_pmod[2]$SB_IO_IN
+.sym 17619 spi_if_ins.o_cs_SB_LUT4_I2_2_O[2]
+.sym 17625 spi_if_ins.state_if[0]
+.sym 17629 spi_if_ins.o_cs_SB_LUT4_I2_2_O[3]
+.sym 17630 spi_if_ins.state_if[1]
+.sym 17631 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
+.sym 17632 w_tx_data_sys[0]
+.sym 17646 r_tx_data_SB_DFFE_Q_E
+.sym 17652 spi_if_ins.state_if[1]
+.sym 17654 spi_if_ins.state_if[0]
+.sym 17682 spi_if_ins.o_cs_SB_LUT4_I2_2_O[1]
+.sym 17683 spi_if_ins.o_cs_SB_LUT4_I2_2_O[2]
+.sym 17684 spi_if_ins.o_cs_SB_LUT4_I2_2_O[3]
+.sym 17685 w_tx_data_sys[0]
+.sym 17698 r_tx_data_SB_DFFE_Q_E
+.sym 17699 i_glob_clock$SB_IO_IN_$glb_clk
+.sym 17701 spi_if_ins.o_data_in_SB_DFFE_Q_E
+.sym 17702 i_button_SB_LUT4_I3_O[0]
+.sym 17703 io_ctrl_ins.pmod_dir_state[4]
+.sym 17704 io_ctrl_ins.pmod_dir_state[3]
+.sym 17705 io_ctrl_ins.pmod_dir_state[5]
+.sym 17708 io_ctrl_ins.pmod_dir_state[6]
+.sym 17718 spi_if_ins.state_if[1]
+.sym 17719 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 17728 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E
+.sym 17731 i_button_SB_LUT4_I3_I2[0]
+.sym 17744 spi_if_ins.spi.r_rx_byte[1]
+.sym 17746 spi_if_ins.spi.r_rx_byte[2]
+.sym 17750 spi_if_ins.spi.r_rx_byte[0]
+.sym 17751 spi_if_ins.spi.r_rx_byte[3]
+.sym 17756 spi_if_ins.spi.r_rx_byte[4]
+.sym 17769 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 17770 sys_ctrl_ins.reset_cmd
+.sym 17775 spi_if_ins.spi.r_rx_byte[1]
+.sym 17788 spi_if_ins.spi.r_rx_byte[0]
+.sym 17795 spi_if_ins.spi.r_rx_byte[4]
+.sym 17801 spi_if_ins.spi.r_rx_byte[3]
+.sym 17814 sys_ctrl_ins.reset_cmd
+.sym 17820 spi_if_ins.spi.r_rx_byte[2]
 .sym 17821 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
 .sym 17822 r_counter[0]_$glb_clk
-.sym 17826 w_rx_data[5]
-.sym 17848 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 17850 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
-.sym 17852 w_rx_data[7]
+.sym 17824 w_rx_data[7]
+.sym 17825 w_rx_data[5]
+.sym 17826 w_rx_data[1]
+.sym 17827 w_rx_data[6]
+.sym 17828 w_rx_data[4]
+.sym 17829 w_rx_data[2]
+.sym 17830 w_rx_data[3]
+.sym 17831 w_rx_data[0]
+.sym 17836 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 17837 w_tx_data_io[7]
+.sym 17842 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 17843 i_button_SB_LUT4_I3_O[1]
+.sym 17845 spi_if_ins.state_if[0]
+.sym 17848 i_config[3]$SB_IO_IN
+.sym 17849 w_rx_data[4]
+.sym 17850 io_ctrl_ins.o_pmod[4]
+.sym 17851 w_rx_data[2]
+.sym 17852 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 17853 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
 .sym 17854 i_config[2]$SB_IO_IN
-.sym 17869 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2]
-.sym 17870 io_ctrl_ins.pmod_dir_state[6]
-.sym 17871 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 17875 i_button_SB_LUT4_I3_O[1]
-.sym 17876 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
-.sym 17883 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[3]
-.sym 17885 i_config[3]$SB_IO_IN
-.sym 17886 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[0]
-.sym 17887 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[1]
-.sym 17890 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
-.sym 17892 i_button_SB_LUT4_I3_O[0]
-.sym 17895 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[2]
-.sym 17916 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[2]
-.sym 17917 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 17918 io_ctrl_ins.pmod_dir_state[6]
-.sym 17919 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O[3]
-.sym 17928 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[0]
-.sym 17929 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O[1]
-.sym 17934 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
-.sym 17936 i_config[3]$SB_IO_IN
-.sym 17940 i_button_SB_LUT4_I3_O[1]
-.sym 17943 i_button_SB_LUT4_I3_O[0]
-.sym 17944 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
+.sym 17855 spi_if_ins.o_load_cmd_SB_LUT4_I2_O_SB_LUT4_I2_O
+.sym 17856 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 17859 spi_if_ins.w_rx_data[5]
+.sym 17867 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
+.sym 17874 w_ioc[1]
+.sym 17875 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 17877 spi_if_ins.o_load_cmd_SB_LUT4_I2_O_SB_LUT4_I3_O[1]
+.sym 17879 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[1]
+.sym 17881 w_rx_data[7]
+.sym 17884 w_rx_data[6]
+.sym 17885 w_rx_data[4]
+.sym 17887 i_button_SB_LUT4_I3_O[1]
+.sym 17890 w_rx_data[5]
+.sym 17895 w_rx_data[3]
+.sym 17896 w_rx_data[0]
+.sym 17899 w_rx_data[6]
+.sym 17907 w_rx_data[7]
+.sym 17912 w_rx_data[5]
+.sym 17917 w_rx_data[0]
+.sym 17922 w_ioc[1]
+.sym 17923 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[1]
+.sym 17925 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 17929 w_rx_data[4]
+.sym 17937 w_rx_data[3]
+.sym 17940 spi_if_ins.o_load_cmd_SB_LUT4_I2_O_SB_LUT4_I3_O[1]
+.sym 17941 i_button_SB_LUT4_I3_O[1]
+.sym 17944 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
 .sym 17945 r_counter[0]_$glb_clk
-.sym 17946 spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O[2]
-.sym 17947 io_ctrl_ins.pmod_dir_state[1]
-.sym 17954 io_ctrl_ins.led0_state_SB_LUT4_I3_O[0]
-.sym 17970 w_rx_data[5]
-.sym 17971 w_rx_data[5]
-.sym 17972 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
-.sym 17974 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 17982 o_tr_vc1_b$SB_IO_OUT
-.sym 17988 o_rx_h_tx_l$SB_IO_OUT
-.sym 17989 w_rx_data[6]
-.sym 17990 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 17998 w_rx_data[5]
-.sym 18000 io_ctrl_ins.pmod_dir_state[4]
-.sym 18002 io_ctrl_ins.pmod_dir_state[7]
-.sym 18003 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[1]
-.sym 18004 w_rx_data[2]
-.sym 18006 o_tr_vc1_b$SB_IO_OUT
-.sym 18008 w_rx_data[3]
-.sym 18012 w_rx_data[7]
-.sym 18014 w_rx_data[4]
-.sym 18018 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 18022 w_rx_data[5]
-.sym 18030 w_rx_data[3]
-.sym 18033 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[1]
-.sym 18034 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 18035 o_rx_h_tx_l$SB_IO_OUT
-.sym 18036 io_ctrl_ins.pmod_dir_state[7]
-.sym 18042 w_rx_data[2]
-.sym 18048 w_rx_data[4]
-.sym 18053 w_rx_data[6]
-.sym 18060 w_rx_data[7]
-.sym 18063 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 18064 o_tr_vc1_b$SB_IO_OUT
-.sym 18065 io_ctrl_ins.pmod_dir_state[4]
-.sym 18066 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[1]
-.sym 18067 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 17947 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[2]
+.sym 17948 io_ctrl_ins.rf_pin_state[7]
+.sym 17949 io_ctrl_ins.rf_pin_state[3]
+.sym 17950 io_ctrl_ins.rf_pin_state[6]
+.sym 17951 io_ctrl_ins.rf_pin_state[5]
+.sym 17952 io_ctrl_ins.rf_pin_state[0]
+.sym 17953 io_ctrl_ins.rf_pin_state[4]
+.sym 17954 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[2]
+.sym 17960 i_button_SB_LUT4_I3_O[1]
+.sym 17961 w_rx_24_fifo_empty
+.sym 17962 spi_if_ins.state_if_SB_DFFESR_Q_1_D[1]
+.sym 17963 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 17964 spi_if_ins.w_rx_data[6]
+.sym 17966 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 17969 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[2]
+.sym 17970 w_rx_data[1]
+.sym 17971 w_rx_data[1]
+.sym 17972 io_ctrl_ins.rf_pin_state[5]
+.sym 17973 o_led1$SB_IO_OUT
+.sym 17974 spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1]
+.sym 17977 w_rx_data[2]
+.sym 17979 w_rx_data[3]
+.sym 17980 io_ctrl_ins.o_pmod[3]
+.sym 17981 w_rx_data[0]
+.sym 17982 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E
+.sym 17990 spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1]
+.sym 17992 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[2]
+.sym 17994 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_I2[2]
+.sym 17995 i_button_SB_LUT4_I3_I2[2]
+.sym 17998 w_rx_data[1]
+.sym 17999 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 18000 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 18003 w_rx_data[0]
+.sym 18006 io_ctrl_ins.led1_state_SB_DFFESR_Q_E
+.sym 18009 w_ioc[0]
+.sym 18010 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[1]
+.sym 18013 w_ioc[1]
+.sym 18015 i_button_SB_LUT4_I3_I2[0]
+.sym 18016 spi_if_ins.o_load_cmd_SB_LUT4_I2_O_SB_LUT4_I3_O[1]
+.sym 18021 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[2]
+.sym 18022 w_ioc[0]
+.sym 18023 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[1]
+.sym 18028 i_button_SB_LUT4_I3_I2[0]
+.sym 18029 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 18030 spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1]
+.sym 18033 spi_if_ins.o_load_cmd_SB_LUT4_I2_O[1]
+.sym 18035 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 18036 i_button_SB_LUT4_I3_I2[2]
+.sym 18040 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[1]
+.sym 18041 w_ioc[0]
+.sym 18042 w_ioc[1]
+.sym 18047 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_I2[2]
+.sym 18048 spi_if_ins.o_load_cmd_SB_LUT4_I2_O_SB_LUT4_I3_O[1]
+.sym 18053 w_rx_data[1]
+.sym 18057 w_rx_data[0]
+.sym 18064 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[1]
+.sym 18065 w_ioc[0]
+.sym 18066 w_ioc[1]
+.sym 18067 io_ctrl_ins.led1_state_SB_DFFESR_Q_E
 .sym 18068 r_counter[0]_$glb_clk
-.sym 18077 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
-.sym 18082 w_rx_data[0]
-.sym 18089 $PACKER_VCC_NET
-.sym 18092 o_rx_h_tx_l$SB_IO_OUT
-.sym 18100 w_rx_data[1]
-.sym 18102 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[3]
-.sym 18104 o_rx_h_tx_l_b$SB_IO_OUT
-.sym 18113 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[3]
-.sym 18116 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 18117 io_ctrl_ins.o_pmod[6]
-.sym 18120 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 18122 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
-.sym 18126 i_config[2]$SB_IO_IN
-.sym 18127 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 18128 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
-.sym 18130 o_rx_h_tx_l_b$SB_IO_OUT
-.sym 18132 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
-.sym 18134 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[1]
-.sym 18137 w_ioc[0]
-.sym 18138 o_tr_vc1$SB_IO_OUT
-.sym 18139 w_rx_data[6]
-.sym 18141 w_rx_data[7]
-.sym 18144 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 18147 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
-.sym 18150 w_rx_data[7]
-.sym 18157 w_rx_data[6]
-.sym 18162 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
-.sym 18163 i_config[2]$SB_IO_IN
-.sym 18164 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[1]
-.sym 18165 o_tr_vc1$SB_IO_OUT
-.sym 18174 w_ioc[0]
-.sym 18175 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3[3]
-.sym 18176 o_rx_h_tx_l_b$SB_IO_OUT
-.sym 18177 io_ctrl_ins.o_pmod[6]
-.sym 18182 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 18183 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I2_O[1]
-.sym 18187 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
-.sym 18188 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 18190 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
+.sym 18069 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 18070 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 18071 i_button_SB_LUT4_I3_O[2]
+.sym 18072 w_tx_data_io[3]
+.sym 18073 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3]
+.sym 18074 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2]
+.sym 18075 w_tx_data_io[4]
+.sym 18076 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2]
+.sym 18077 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
+.sym 18078 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_I2_SB_LUT4_I2_O
+.sym 18084 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
+.sym 18090 i_button_SB_LUT4_I3_I2[0]
+.sym 18094 io_ctrl_ins.rf_pin_state[3]
+.sym 18097 io_ctrl_ins.led0_state_SB_LUT4_I3_I0[0]
+.sym 18100 o_tr_vc1$SB_IO_OUT
+.sym 18111 i_button_SB_LUT4_I3_I2[1]
+.sym 18114 i_button_SB_LUT4_I3_I2[0]
+.sym 18119 w_rx_data[4]
+.sym 18121 w_rx_data[2]
+.sym 18125 o_led0$SB_IO_OUT
+.sym 18126 i_button_SB_LUT4_I3_I2[2]
+.sym 18130 io_ctrl_ins.debug_mode[1]
+.sym 18131 w_rx_data[1]
+.sym 18135 i_button_SB_LUT4_I3_I2[1]
+.sym 18138 spi_if_ins.o_load_cmd_SB_LUT4_I2_O_SB_LUT4_I2_O
+.sym 18139 w_rx_data[3]
+.sym 18141 w_rx_data[0]
+.sym 18145 w_rx_data[0]
+.sym 18156 i_button_SB_LUT4_I3_I2[1]
+.sym 18157 i_button_SB_LUT4_I3_I2[0]
+.sym 18158 i_button_SB_LUT4_I3_I2[2]
+.sym 18159 o_led0$SB_IO_OUT
+.sym 18165 w_rx_data[1]
+.sym 18171 w_rx_data[4]
+.sym 18176 w_rx_data[3]
+.sym 18181 w_rx_data[2]
+.sym 18186 io_ctrl_ins.debug_mode[1]
+.sym 18188 i_button_SB_LUT4_I3_I2[1]
+.sym 18190 spi_if_ins.o_load_cmd_SB_LUT4_I2_O_SB_LUT4_I2_O
 .sym 18191 r_counter[0]_$glb_clk
-.sym 18196 o_tr_vc1$SB_IO_OUT
-.sym 18198 o_tr_vc1_b$SB_IO_OUT
-.sym 18214 o_led0$SB_IO_OUT
-.sym 18218 io_ctrl_ins.rf_pin_state[6]
-.sym 18237 w_rx_data[0]
-.sym 18238 w_rx_data[3]
-.sym 18242 w_rx_data[4]
-.sym 18243 w_rx_data[2]
-.sym 18246 io_ctrl_ins.rf_mode[0]
-.sym 18248 w_rx_data[1]
-.sym 18249 io_ctrl_ins.rf_mode[2]
-.sym 18261 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
-.sym 18269 w_rx_data[2]
-.sym 18275 w_rx_data[0]
-.sym 18280 w_rx_data[1]
-.sym 18291 w_rx_data[3]
-.sym 18304 w_rx_data[4]
-.sym 18310 io_ctrl_ins.rf_mode[2]
-.sym 18311 io_ctrl_ins.rf_mode[0]
-.sym 18313 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
+.sym 18192 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 18194 o_tr_vc1$SB_IO_OUT
+.sym 18195 o_tr_vc1_b$SB_IO_OUT
+.sym 18196 o_tr_vc2$SB_IO_OUT
+.sym 18197 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0]
+.sym 18198 io_ctrl_ins.mixer_en_state
+.sym 18206 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 18211 i_button$SB_IO_IN
+.sym 18212 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 18216 w_ioc[0]
+.sym 18238 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 18242 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 18243 w_rx_data[1]
+.sym 18245 io_ctrl_ins.o_pmod[0]
+.sym 18248 w_ioc[0]
+.sym 18249 w_rx_data[2]
+.sym 18252 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E
+.sym 18253 w_rx_data[0]
+.sym 18263 io_ctrl_ins.mixer_en_state
+.sym 18276 w_rx_data[1]
+.sym 18286 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 18292 w_rx_data[0]
+.sym 18298 w_rx_data[2]
+.sym 18303 io_ctrl_ins.mixer_en_state
+.sym 18304 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 18305 io_ctrl_ins.o_pmod[0]
+.sym 18306 w_ioc[0]
+.sym 18313 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E
 .sym 18314 r_counter[0]_$glb_clk
-.sym 18329 $PACKER_VCC_NET
-.sym 18335 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
+.sym 18340 i_config[3]$SB_IO_IN
 .sym 18345 i_config[2]$SB_IO_IN
-.sym 18346 o_rx_h_tx_l$SB_IO_OUT
-.sym 18367 io_ctrl_ins.rf_pin_state[7]
-.sym 18369 io_ctrl_ins.rf_pin_state[3]
-.sym 18373 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 18375 io_ctrl_ins.debug_mode_SB_LUT4_I0_O
-.sym 18376 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 18377 io_ctrl_ins.rf_mode[0]
-.sym 18378 io_ctrl_ins.rf_pin_state[6]
-.sym 18380 io_ctrl_ins.rf_mode[2]
-.sym 18384 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 18386 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 18390 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 18391 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 18392 io_ctrl_ins.rf_mode[0]
-.sym 18393 io_ctrl_ins.rf_mode[2]
-.sym 18421 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 18422 io_ctrl_ins.rf_pin_state[6]
-.sym 18423 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 18426 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 18427 io_ctrl_ins.rf_mode[2]
-.sym 18428 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 18429 io_ctrl_ins.rf_pin_state[3]
-.sym 18432 io_ctrl_ins.rf_pin_state[7]
-.sym 18433 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 18435 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
-.sym 18436 io_ctrl_ins.debug_mode_SB_LUT4_I0_O
-.sym 18437 r_counter[0]_$glb_clk
-.sym 18453 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 18470 o_led1$SB_IO_OUT
 .sym 18562 i_config[1]$SB_IO_IN
 .sym 18564 i_config[2]$SB_IO_IN
 .sym 18636 io_smi_data[4]$SB_IO_OUT
 .sym 18641 i_smi_a3$SB_IO_IN
-.sym 18658 i_smi_a3$SB_IO_IN
-.sym 18660 io_smi_data[4]$SB_IO_OUT
+.sym 18645 i_smi_a3$SB_IO_IN
+.sym 18651 io_smi_data[4]$SB_IO_OUT
 .sym 18693 $io_pmod[3]$iobuf_i
-.sym 18695 io_smi_data[5]$SB_IO_OUT
-.sym 18724 i_ss$SB_IO_IN
-.sym 18737 i_ss$SB_IO_IN
+.sym 18695 i_mosi$SB_IO_IN
+.sym 18696 o_miso_$_TBUF__Y_E
+.sym 18707 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[6]
+.sym 18709 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[7]
+.sym 18712 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 18716 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 18717 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3]
+.sym 18721 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 18723 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[3]
+.sym 18734 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0]
+.sym 18736 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 18743 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[7]
+.sym 18745 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[6]
+.sym 18750 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[3]
+.sym 18755 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[7]
+.sym 18763 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3]
+.sym 18767 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 18772 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[6]
+.sym 18781 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0]
+.sym 18782 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 18783 r_counter[0]_$glb_clk
+.sym 18784 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
 .sym 18785 $io_pmod[3]$iobuf_i
-.sym 18814 i_ss_SB_LUT4_I3_O
-.sym 18818 i_ss$SB_IO_IN
-.sym 19218 io_pmod[2]$SB_IO_IN
-.sym 19228 $io_pmod[2]$iobuf_i
-.sym 19236 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I2[2]
-.sym 19242 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I2[0]
-.sym 19244 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I2[3]
-.sym 19250 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I2[1]
-.sym 19274 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I2[0]
-.sym 19275 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I2[1]
-.sym 19276 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I2[2]
-.sym 19277 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I2[3]
+.sym 18799 io_ctrl_ins.pmod_dir_state[3]
+.sym 18802 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 18809 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[3]
+.sym 18815 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 18818 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[1]
+.sym 18842 io_smi_data[5]$SB_IO_OUT
+.sym 18843 rx_09_fifo.rd_addr_gray_wr[2]
+.sym 18846 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 18853 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[1]
+.sym 18866 rx_09_fifo.rd_addr_gray[3]
+.sym 18870 rx_09_fifo.rd_addr_gray[2]
+.sym 18873 rx_09_fifo.rd_addr_gray[4]
+.sym 18875 rx_09_fifo.rd_addr_gray[6]
+.sym 18876 rx_09_fifo.rd_addr_gray[5]
+.sym 18880 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[1]
+.sym 18885 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[2]
+.sym 18891 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[2]
+.sym 18901 rx_09_fifo.rd_addr_gray[6]
+.sym 18906 rx_09_fifo.rd_addr_gray[3]
+.sym 18917 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[1]
+.sym 18919 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[2]
+.sym 18920 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[2]
+.sym 18925 rx_09_fifo.rd_addr_gray[2]
+.sym 18931 rx_09_fifo.rd_addr_gray[4]
+.sym 18943 rx_09_fifo.rd_addr_gray[5]
+.sym 18946 lvds_clock_buf
+.sym 18963 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 18966 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 18972 $PACKER_VCC_NET
+.sym 18975 $PACKER_VCC_NET
+.sym 18990 w_smi_data_output[5]
+.sym 18998 rx_09_fifo.wr_addr_gray_rd[4]
+.sym 19002 i_sck$SB_IO_IN
+.sym 19011 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+.sym 19013 rx_09_fifo.wr_addr_gray[4]
+.sym 19014 i_smi_a3$SB_IO_IN
+.sym 19020 spi_if_ins.spi.SCKr[0]
+.sym 19028 rx_09_fifo.wr_addr_gray[4]
+.sym 19034 rx_09_fifo.wr_addr_gray_rd[4]
+.sym 19041 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+.sym 19053 i_smi_a3$SB_IO_IN
+.sym 19054 w_smi_data_output[5]
+.sym 19060 spi_if_ins.spi.SCKr[0]
+.sym 19067 i_sck$SB_IO_IN
+.sym 19069 r_counter[0]_$glb_clk
+.sym 19083 i_ss$SB_IO_IN
+.sym 19114 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 19118 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 19123 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
+.sym 19125 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R
+.sym 19126 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+.sym 19132 $PACKER_VCC_NET
+.sym 19135 $PACKER_VCC_NET
+.sym 19138 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 19139 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 19143 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 19144 $nextpnr_ICESTORM_LC_15$O
+.sym 19147 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 19150 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
+.sym 19152 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 19153 $PACKER_VCC_NET
+.sym 19158 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 19159 $PACKER_VCC_NET
+.sym 19160 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
+.sym 19164 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 19165 $PACKER_VCC_NET
+.sym 19166 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 19169 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 19170 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+.sym 19171 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
+.sym 19178 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 19183 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 19187 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+.sym 19188 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 19189 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 19190 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
+.sym 19191 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 19192 r_counter[0]_$glb_clk
+.sym 19193 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R
+.sym 19206 i_mosi$SB_IO_IN
+.sym 19210 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 19214 o_miso_$_TBUF__Y_E
+.sym 19216 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 19237 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 19238 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 19239 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 19240 spi_if_ins.spi.r_tx_byte[2]
+.sym 19241 spi_if_ins.spi.r_tx_byte[6]
+.sym 19242 spi_if_ins.spi.r_tx_byte[3]
+.sym 19245 spi_if_ins.spi.r_tx_byte[1]
+.sym 19246 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1]
+.sym 19247 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
+.sym 19249 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 19250 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1]
+.sym 19251 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1]
+.sym 19253 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0]
+.sym 19255 spi_if_ins.spi.r_tx_byte[5]
+.sym 19257 spi_if_ins.spi.r_tx_byte[7]
+.sym 19258 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2]
+.sym 19260 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 19262 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
+.sym 19263 spi_if_ins.r_tx_byte[5]
+.sym 19265 spi_if_ins.r_tx_byte[7]
+.sym 19266 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 19268 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 19269 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 19270 spi_if_ins.spi.r_tx_byte[6]
+.sym 19271 spi_if_ins.spi.r_tx_byte[2]
+.sym 19274 spi_if_ins.spi.r_tx_byte[1]
+.sym 19275 spi_if_ins.spi.r_tx_byte[5]
+.sym 19276 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 19277 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 19280 spi_if_ins.spi.r_tx_byte[7]
+.sym 19281 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 19282 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 19283 spi_if_ins.spi.r_tx_byte[3]
+.sym 19287 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1]
+.sym 19288 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 19289 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 19293 spi_if_ins.r_tx_byte[5]
+.sym 19298 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 19299 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1]
+.sym 19300 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2]
+.sym 19301 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0]
+.sym 19307 spi_if_ins.r_tx_byte[7]
+.sym 19310 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 19311 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 19312 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
+.sym 19313 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1]
+.sym 19314 spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E
 .sym 19315 r_counter[0]_$glb_clk
-.sym 19316 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]_$glb_sr
-.sym 19358 rx_09_fifo.wr_addr_gray_rd[7]
-.sym 19362 rx_09_fifo.wr_addr_gray_rd[6]
-.sym 19365 rx_09_fifo.wr_addr_gray_rd[1]
-.sym 19370 rx_09_fifo.wr_addr_gray_rd_r[6]
-.sym 19371 rx_09_fifo.wr_addr_gray_rd_r[7]
-.sym 19378 io_pmod[2]$SB_IO_IN
-.sym 19398 rx_09_fifo.wr_addr_gray_rd_r[7]
-.sym 19399 rx_09_fifo.wr_addr_gray_rd_r[6]
-.sym 19400 io_pmod[2]$SB_IO_IN
-.sym 19415 rx_09_fifo.wr_addr_gray_rd[6]
-.sym 19422 rx_09_fifo.wr_addr_gray_rd[7]
-.sym 19435 rx_09_fifo.wr_addr_gray_rd[1]
-.sym 19438 r_counter[0]_$glb_clk
-.sym 19459 io_pmod[5]$SB_IO_IN
-.sym 19463 $io_pmod[7]$iobuf_i
-.sym 19581 $io_pmod[6]$iobuf_i
-.sym 19607 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 19617 i_ss$SB_IO_IN
-.sym 19619 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 19622 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 19636 $nextpnr_ICESTORM_LC_10$O
-.sym 19639 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 19642 spi_if_ins.spi.r_rx_bit_count_SB_DFFR_Q_D_SB_LUT4_O_I3[2]
-.sym 19645 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 19649 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 19652 spi_if_ins.spi.r_rx_bit_count_SB_DFFR_Q_D_SB_LUT4_O_I3[2]
-.sym 19655 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 19658 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 19667 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 19668 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 19670 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 19673 spi_if_ins.spi.r_rx_bit_count[2]
-.sym 19674 spi_if_ins.spi.r_rx_bit_count[1]
-.sym 19675 spi_if_ins.spi.r_rx_bit_count[0]
-.sym 19680 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 19316 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 19331 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1]
+.sym 19365 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 19368 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 19371 i_ss$SB_IO_IN
+.sym 19372 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 19376 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 19390 $nextpnr_ICESTORM_LC_14$O
+.sym 19392 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 19396 spi_if_ins.spi.r_rx_bit_count_SB_DFFR_Q_D_SB_LUT4_O_I3[2]
+.sym 19399 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 19403 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 19406 spi_if_ins.spi.r_rx_bit_count_SB_DFFR_Q_D_SB_LUT4_O_I3[2]
+.sym 19418 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 19421 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 19422 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 19423 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 19438 i_sck$SB_IO_IN_$glb_clk
+.sym 19439 i_ss$SB_IO_IN
+.sym 19452 i_mosi$SB_IO_IN
+.sym 19454 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_E
+.sym 19471 $PACKER_VCC_NET
+.sym 19475 $PACKER_VCC_NET
+.sym 19483 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 19487 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 19491 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 19494 i_ss$SB_IO_IN
+.sym 19501 o_miso_$_TBUF__Y_E
+.sym 19526 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 19535 o_miso_$_TBUF__Y_E
+.sym 19544 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 19545 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 19547 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 19550 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 19552 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 19561 i_sck$SB_IO_IN_$glb_clk
+.sym 19562 i_ss$SB_IO_IN
+.sym 19575 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 19582 i_smi_soe_se$rename$0
+.sym 19615 o_miso_$_TBUF__Y_E
+.sym 19618 i_mosi$SB_IO_IN
+.sym 19619 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 19620 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 19631 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 19637 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 19655 i_mosi$SB_IO_IN
+.sym 19673 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 19680 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 19683 o_miso_$_TBUF__Y_E
 .sym 19684 i_sck$SB_IO_IN_$glb_clk
-.sym 19685 i_ss$SB_IO_IN
-.sym 19716 $io_pmod[2]$iobuf_i
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-.sym 19732 spi_if_ins.spi.r_temp_rx_byte[4]
-.sym 19735 spi_if_ins.spi.r_temp_rx_byte[3]
-.sym 19737 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 19698 i_button_SB_LUT4_I3_I2[0]
+.sym 19713 io_ctrl_ins.pmod_dir_state[6]
+.sym 19730 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 19732 i_mosi$SB_IO_IN
+.sym 19735 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 19741 spi_if_ins.spi.r_temp_rx_byte[3]
 .sym 19742 spi_if_ins.spi.r_temp_rx_byte[1]
-.sym 19758 i_mosi$SB_IO_IN
-.sym 19762 spi_if_ins.spi.r_temp_rx_byte[1]
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-.sym 19790 spi_if_ins.spi.r_temp_rx_byte[3]
-.sym 19798 i_mosi$SB_IO_IN
-.sym 19804 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 19745 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D_SB_LUT4_I3_O
+.sym 19763 i_mosi$SB_IO_IN
+.sym 19768 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 19773 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 19786 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 19797 spi_if_ins.spi.r_temp_rx_byte[3]
 .sym 19806 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D_SB_LUT4_I3_O
 .sym 19807 i_sck$SB_IO_IN_$glb_clk
-.sym 19824 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 19961 io_ctrl_ins.pmod_dir_state[1]
-.sym 19967 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
+.sym 19820 i_config[1]$SB_IO_IN
+.sym 19828 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 19829 $io_pmod[2]$iobuf_i
+.sym 19840 w_tx_data_io[4]
+.sym 19842 w_tx_data_io[3]
+.sym 19850 w_rx_data[7]
+.sym 19851 w_rx_data[5]
+.sym 19854 w_rx_data[4]
+.sym 19856 w_rx_data[3]
+.sym 19859 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 19860 spi_if_ins.state_if[0]
+.sym 19861 w_rx_data[6]
+.sym 19868 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E
+.sym 19874 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 19877 spi_if_ins.state_if[1]
+.sym 19883 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 19884 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 19885 spi_if_ins.state_if[1]
+.sym 19886 spi_if_ins.state_if[0]
+.sym 19890 w_rx_data[7]
+.sym 19897 w_rx_data[4]
+.sym 19904 w_rx_data[3]
+.sym 19908 w_rx_data[5]
+.sym 19926 w_rx_data[6]
+.sym 19929 io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E
+.sym 19930 r_counter[0]_$glb_clk
+.sym 19945 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 19948 i_button_SB_LUT4_I3_O[0]
+.sym 19955 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 19957 io_ctrl_ins.pmod_dir_state[4]
+.sym 19958 w_rx_data[2]
+.sym 19967 $PACKER_VCC_NET
+.sym 19979 spi_if_ins.w_rx_data[6]
 .sym 19984 spi_if_ins.o_data_in_SB_DFFE_Q_E
-.sym 19995 spi_if_ins.w_rx_data[5]
-.sym 20018 spi_if_ins.w_rx_data[5]
+.sym 19987 spi_if_ins.state_if_SB_DFFESR_Q_1_D[1]
+.sym 19991 spi_if_ins.w_rx_data[5]
+.sym 19992 spi_if_ins.w_rx_data[4]
+.sym 19993 spi_if_ins.w_rx_data[3]
+.sym 19997 spi_if_ins.w_rx_data[1]
+.sym 19999 spi_if_ins.w_rx_data[0]
+.sym 20004 spi_if_ins.w_rx_data[2]
+.sym 20009 spi_if_ins.state_if_SB_DFFESR_Q_1_D[1]
+.sym 20013 spi_if_ins.w_rx_data[5]
+.sym 20021 spi_if_ins.w_rx_data[1]
+.sym 20025 spi_if_ins.w_rx_data[6]
+.sym 20031 spi_if_ins.w_rx_data[4]
+.sym 20037 spi_if_ins.w_rx_data[2]
+.sym 20044 spi_if_ins.w_rx_data[3]
+.sym 20050 spi_if_ins.w_rx_data[0]
 .sym 20052 spi_if_ins.o_data_in_SB_DFFE_Q_E
 .sym 20053 r_counter[0]_$glb_clk
-.sym 20081 io_ctrl_ins.debug_mode_SB_LUT4_I0_O
-.sym 20109 w_rx_data[0]
-.sym 20114 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O
-.sym 20122 w_rx_data[1]
-.sym 20130 w_rx_data[1]
-.sym 20172 w_rx_data[0]
-.sym 20175 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 20070 spi_if_ins.o_data_in_SB_DFFE_Q_E
+.sym 20074 io_pmod[2]$SB_IO_IN
+.sym 20076 o_tr_vc1$SB_IO_OUT
+.sym 20079 i_config[0]$SB_IO_IN
+.sym 20081 io_ctrl_ins.rf_pin_state[0]
+.sym 20083 io_ctrl_ins.rf_pin_state[4]
+.sym 20085 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[2]
+.sym 20086 i_button_SB_LUT4_I3_O[2]
+.sym 20087 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[2]
+.sym 20096 w_rx_data[7]
+.sym 20099 w_rx_data[6]
+.sym 20100 i_config[3]$SB_IO_IN
+.sym 20103 i_button_SB_LUT4_I3_I2[2]
+.sym 20105 w_rx_data[5]
+.sym 20106 i_config[2]$SB_IO_IN
+.sym 20107 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_I2_SB_LUT4_I2_O
+.sym 20108 w_rx_data[4]
+.sym 20110 w_rx_data[3]
+.sym 20111 w_rx_data[0]
+.sym 20131 i_config[3]$SB_IO_IN
+.sym 20132 i_button_SB_LUT4_I3_I2[2]
+.sym 20136 w_rx_data[7]
+.sym 20144 w_rx_data[3]
+.sym 20147 w_rx_data[6]
+.sym 20153 w_rx_data[5]
+.sym 20160 w_rx_data[0]
+.sym 20166 w_rx_data[4]
+.sym 20171 i_config[2]$SB_IO_IN
+.sym 20173 i_button_SB_LUT4_I3_I2[2]
+.sym 20175 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_I2_SB_LUT4_I2_O
 .sym 20176 r_counter[0]_$glb_clk
-.sym 20190 $PACKER_VCC_NET
-.sym 20196 $PACKER_GND_NET
-.sym 20223 w_rx_data[5]
-.sym 20237 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
-.sym 20297 w_rx_data[5]
-.sym 20298 spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O
+.sym 20194 io_ctrl_ins.rf_pin_state[7]
+.sym 20198 io_ctrl_ins.rf_pin_state[6]
+.sym 20210 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 20211 o_tr_vc1_b$SB_IO_OUT
+.sym 20220 i_button$SB_IO_IN
+.sym 20221 o_tr_vc1_b$SB_IO_OUT
+.sym 20222 o_tr_vc2$SB_IO_OUT
+.sym 20223 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.sym 20224 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 20225 io_ctrl_ins.rf_mode[0]
+.sym 20226 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 20227 io_ctrl_ins.pmod_dir_state[4]
+.sym 20228 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 20230 io_ctrl_ins.o_pmod[4]
+.sym 20231 w_ioc[0]
+.sym 20232 io_ctrl_ins.o_pmod[3]
+.sym 20234 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
+.sym 20235 w_ioc[0]
+.sym 20236 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 20237 io_ctrl_ins.led0_state_SB_LUT4_I3_I0[0]
+.sym 20238 i_button_SB_LUT4_I3_I2[0]
+.sym 20239 i_config[0]$SB_IO_IN
+.sym 20241 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2]
+.sym 20242 i_button_SB_LUT4_I3_O[1]
+.sym 20243 i_config[1]$SB_IO_IN
+.sym 20244 io_ctrl_ins.pmod_dir_state[3]
+.sym 20246 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3]
+.sym 20247 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2]
+.sym 20250 i_button_SB_LUT4_I3_I2[2]
+.sym 20252 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 20253 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 20254 io_ctrl_ins.rf_mode[0]
+.sym 20255 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 20258 i_button$SB_IO_IN
+.sym 20259 i_button_SB_LUT4_I3_I2[2]
+.sym 20264 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
+.sym 20265 i_button_SB_LUT4_I3_O[1]
+.sym 20266 io_ctrl_ins.pmod_dir_state[3]
+.sym 20267 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2]
+.sym 20270 i_config[1]$SB_IO_IN
+.sym 20271 i_button_SB_LUT4_I3_I2[2]
+.sym 20272 i_button_SB_LUT4_I3_I2[0]
+.sym 20273 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 20276 w_ioc[0]
+.sym 20277 o_tr_vc2$SB_IO_OUT
+.sym 20278 io_ctrl_ins.o_pmod[3]
+.sym 20279 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 20282 io_ctrl_ins.pmod_dir_state[4]
+.sym 20283 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3]
+.sym 20284 i_button_SB_LUT4_I3_O[1]
+.sym 20285 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2]
+.sym 20288 io_ctrl_ins.o_pmod[4]
+.sym 20289 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 20290 o_tr_vc1_b$SB_IO_OUT
+.sym 20291 w_ioc[0]
+.sym 20294 i_button_SB_LUT4_I3_I2[0]
+.sym 20295 i_button_SB_LUT4_I3_I2[2]
+.sym 20296 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 20297 i_config[0]$SB_IO_IN
+.sym 20298 io_ctrl_ins.led0_state_SB_LUT4_I3_I0[0]
 .sym 20299 r_counter[0]_$glb_clk
-.sym 20313 o_rx_h_tx_l$SB_IO_OUT
-.sym 20322 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 20348 io_ctrl_ins.rf_pin_state[4]
-.sym 20349 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
-.sym 20353 io_ctrl_ins.debug_mode_SB_LUT4_I0_O
-.sym 20357 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
-.sym 20360 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 20364 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 20368 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 20372 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 20393 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 20394 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[2]
-.sym 20395 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
-.sym 20396 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 20405 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
-.sym 20406 io_ctrl_ins.rf_pin_state[4]
-.sym 20407 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 20300 io_ctrl_ins.o_data_out_SB_DFFESR_Q_R
+.sym 20326 w_tx_data_io[3]
+.sym 20332 w_tx_data_io[4]
+.sym 20346 io_ctrl_ins.rf_pin_state[3]
+.sym 20350 io_ctrl_ins.rf_pin_state[5]
+.sym 20353 io_ctrl_ins.rf_pin_state[0]
+.sym 20354 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0]
+.sym 20355 io_ctrl_ins.rf_pin_state[4]
+.sym 20363 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 20369 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
+.sym 20370 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 20371 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 20372 io_ctrl_ins.rf_mode[0]
+.sym 20373 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 20381 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0]
+.sym 20382 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 20383 io_ctrl_ins.rf_pin_state[5]
+.sym 20384 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 20387 io_ctrl_ins.rf_pin_state[4]
+.sym 20388 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 20389 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 20390 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0]
+.sym 20393 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 20394 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 20395 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 20396 io_ctrl_ins.rf_pin_state[3]
+.sym 20400 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 20402 io_ctrl_ins.rf_mode[0]
+.sym 20405 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 20406 io_ctrl_ins.rf_pin_state[0]
+.sym 20407 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
 .sym 20408 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 20421 io_ctrl_ins.debug_mode_SB_LUT4_I0_O
+.sym 20421 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
 .sym 20422 r_counter[0]_$glb_clk
-.sym 20438 o_tr_vc1_b$SB_IO_OUT
-.sym 20444 o_tr_vc1$SB_IO_OUT
-.sym 20453 i_config[0]$SB_IO_IN
-.sym 20456 o_led1$SB_IO_OUT
+.sym 20440 o_tr_vc1$SB_IO_OUT
+.sym 20444 o_tr_vc2$SB_IO_OUT
+.sym 20571 i_config[0]$SB_IO_IN
 .sym 20672 i_config[0]$SB_IO_IN
+.sym 20743 o_led1$SB_IO_OUT
 .sym 20748 io_smi_data[5]$SB_IO_OUT
-.sym 20768 io_smi_data[5]$SB_IO_OUT
-.sym 20802 i_ss_SB_LUT4_I3_O
+.sym 20757 io_smi_data[5]$SB_IO_OUT
+.sym 20771 r_counter[0]
+.sym 20802 i_sck$SB_IO_IN
 .sym 20804 i_ss$SB_IO_IN
 .sym 20844 i_mosi$SB_IO_IN
-.sym 20904 int_miso
-.sym 21129 i_smi_soe_se$rename$0
-.sym 21151 int_miso
-.sym 21241 $io_pmod[4]$iobuf_i
-.sym 21438 $io_pmod[5]$iobuf_i
-.sym 21449 i_mosi$SB_IO_IN
-.sym 21537 io_pmod[2]$SB_IO_IN
-.sym 21761 $PACKER_VCC_NET
-.sym 21906 $PACKER_VCC_NET
-.sym 21945 $io_pmod[2]$iobuf_i
-.sym 21954 io_pmod[2]$SB_IO_IN
-.sym 22005 io_ctrl_ins.led0_state_SB_DFFESR_Q_E
-.sym 22009 o_led0$SB_IO_OUT
-.sym 22011 o_led1$SB_IO_OUT
-.sym 22061 w_rx_data[0]
-.sym 22062 $PACKER_VCC_NET
-.sym 22069 w_rx_data[1]
-.sym 22153 o_led1$SB_IO_OUT
-.sym 22157 io_ctrl_ins.led0_state_SB_DFFESR_Q_E
-.sym 22163 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
-.sym 22361 o_tr_vc2$SB_IO_OUT
+.sym 20850 rx_09_fifo.rd_addr_gray[1]
+.sym 20944 int_miso
+.sym 20989 rx_09_fifo.rd_addr_gray_wr[1]
+.sym 21029 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 21049 int_miso
+.sym 21129 io_pmod[5]$SB_IO_IN
+.sym 21142 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 21193 int_miso
+.sym 21230 $io_pmod[4]$iobuf_i
+.sym 21245 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D[1]
+.sym 21297 spi_if_ins.spi.r_rx_done
+.sym 21392 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 21396 spi_if_ins.spi.r2_rx_done
+.sym 21397 spi_if_ins.spi.r3_rx_done
+.sym 21448 spi_if_ins.state_if[0]
+.sym 21455 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 21494 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+.sym 21498 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
+.sym 21501 spi_if_ins.state_if[0]
+.sym 21543 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 21554 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E
+.sym 21558 spi_if_ins.state_if[1]
+.sym 21598 spi_if_ins.state_if_SB_DFFE_Q_E
+.sym 21599 spi_if_ins.state_if[1]
+.sym 21650 spi_if_ins.state_if_SB_DFFESR_Q_1_R
+.sym 21658 io_ctrl_ins.o_pmod[5]
+.sym 21660 io_ctrl_ins.o_pmod[6]
+.sym 21700 w_tx_data_io[7]
+.sym 21703 w_tx_data_io[5]
+.sym 21705 w_tx_data_io[6]
+.sym 21741 $io_pmod[5]$iobuf_i
+.sym 21742 $PACKER_VCC_NET
+.sym 21746 spi_if_ins.state_if_SB_DFFESR_Q_1_D[1]
+.sym 21755 w_tx_data_io[5]
+.sym 21757 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1]
+.sym 21759 w_tx_data_io[6]
+.sym 21762 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_I2[2]
+.sym 21800 i_button_SB_LUT4_I3_O[3]
+.sym 21802 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[3]
+.sym 21803 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_I2[2]
+.sym 21805 w_tx_data_sys[0]
+.sym 21806 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
+.sym 21807 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[3]
+.sym 21842 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[2]
+.sym 21850 i_button_SB_LUT4_I3_O[2]
+.sym 21853 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[2]
+.sym 21856 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 21857 w_tx_data_sys[0]
+.sym 21905 o_rx_h_tx_l$SB_IO_OUT
+.sym 21908 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 21950 io_ctrl_ins.led0_state_SB_LUT4_I3_I0[0]
+.sym 21954 io_ctrl_ins.pmod_dir_state[6]
+.sym 21957 io_ctrl_ins.pmod_dir_state[5]
+.sym 21962 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
+.sym 21964 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
+.sym 22167 o_led0$SB_IO_OUT
+.sym 22356 o_tr_vc1_b$SB_IO_OUT
 .sym 22487 o_led1$SB_IO_OUT
-.sym 22505 o_led1$SB_IO_OUT
+.sym 22511 o_led1$SB_IO_OUT
 .sym 22517 int_miso
-.sym 22519 i_ss_SB_LUT4_I3_O
-.sym 22530 int_miso
-.sym 22538 i_ss_SB_LUT4_I3_O
-.sym 22563 i_mosi$SB_IO_IN
-.sym 22574 i_sck$SB_IO_IN
+.sym 22519 o_miso_$_TBUF__Y_E
+.sym 22529 o_miso_$_TBUF__Y_E
+.sym 22532 int_miso
+.sym 22576 i_mosi$SB_IO_IN
+.sym 22585 r_counter[0]
+.sym 22623 r_counter[0]
+.sym 22664 i_glob_clock$SB_IO_IN_$glb_clk
 .sym 22666 i_sck$SB_IO_IN
 .sym 22668 i_ss$SB_IO_IN
+.sym 22686 r_counter[0]
+.sym 22707 i_ss$SB_IO_IN
 .sym 22711 i_sck$SB_IO_IN
+.sym 22715 i_ss$SB_IO_IN
+.sym 22720 w_smi_read_req
 .sym 22733 i_ss$SB_IO_IN
-.sym 22970 i_smi_a3$SB_IO_IN
-.sym 23100 i_sck$SB_IO_IN
-.sym 23223 i_ss$SB_IO_IN
-.sym 23226 i_ss$SB_IO_IN
-.sym 23230 $PACKER_VCC_NET
-.sym 23331 o_led0$SB_IO_OUT
-.sym 23722 $PACKER_VCC_NET
-.sym 23960 $PACKER_VCC_NET
-.sym 23964 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
-.sym 24081 $PACKER_VCC_NET
-.sym 24102 io_ctrl_ins.led0_state_SB_DFFESR_Q_E
-.sym 24118 w_rx_data[0]
-.sym 24123 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
-.sym 24124 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
-.sym 24126 w_rx_data[1]
-.sym 24131 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 24139 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
-.sym 24140 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 24141 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
-.sym 24166 w_rx_data[0]
-.sym 24175 w_rx_data[1]
-.sym 24179 io_ctrl_ins.led0_state_SB_DFFESR_Q_E
-.sym 24180 r_counter[0]_$glb_clk
-.sym 24181 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]_$glb_sr
-.sym 24182 o_tr_vc1_b$SB_IO_OUT
+.sym 22761 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 22767 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 22774 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 22804 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 22805 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 22826 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 22827 r_counter[0]_$glb_clk
+.sym 22828 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
+.sym 22882 rx_09_fifo.rd_addr_gray[1]
+.sym 22933 rx_09_fifo.rd_addr_gray[1]
+.sym 22950 lvds_clock_buf
+.sym 22955 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 22964 io_pmod[6]$SB_IO_IN
+.sym 22965 i_smi_a3$SB_IO_IN
+.sym 22980 i_ss$SB_IO_IN
+.sym 23105 i_ss$SB_IO_IN
+.sym 23122 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 23127 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 23130 spi_if_ins.r_tx_byte[7]
+.sym 23134 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1]
+.sym 23179 spi_if_ins.r_tx_byte[7]
+.sym 23180 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 23182 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1]
+.sym 23195 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 23196 r_counter[0]_$glb_clk
+.sym 23203 $io_pmod[7]$iobuf_i
+.sym 23218 spi_if_ins.r_tx_byte[7]
+.sym 23225 io_pmod[4]$SB_IO_IN
+.sym 23252 i_ss$SB_IO_IN
+.sym 23254 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D[1]
+.sym 23257 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_E
+.sym 23315 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D[1]
+.sym 23318 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_E
+.sym 23319 i_sck$SB_IO_IN_$glb_clk
+.sym 23320 i_ss$SB_IO_IN
+.sym 23322 $io_pmod[6]$iobuf_i
+.sym 23336 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 23344 io_pmod[7]$SB_IO_IN
+.sym 23366 spi_if_ins.spi.r2_rx_done
+.sym 23375 spi_if_ins.spi.r3_rx_done
+.sym 23377 spi_if_ins.spi.r_rx_done
+.sym 23395 spi_if_ins.spi.r2_rx_done
+.sym 23397 spi_if_ins.spi.r3_rx_done
+.sym 23421 spi_if_ins.spi.r_rx_done
+.sym 23428 spi_if_ins.spi.r2_rx_done
+.sym 23442 r_counter[0]_$glb_clk
+.sym 23447 w_tx_data_smi[2]
+.sym 23456 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 23461 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 23469 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 23473 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 23474 spi_if_ins.state_if[0]
+.sym 23479 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 23487 spi_if_ins.state_if_SB_DFFE_Q_E
+.sym 23496 spi_if_ins.state_if[1]
+.sym 23497 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
+.sym 23500 spi_if_ins.state_if[0]
+.sym 23505 spi_if_ins.state_if_SB_DFFESR_Q_1_R
+.sym 23513 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 23518 spi_if_ins.state_if[1]
+.sym 23520 spi_if_ins.state_if[0]
+.sym 23521 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 23542 spi_if_ins.state_if[1]
+.sym 23544 spi_if_ins.state_if[0]
+.sym 23545 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 23562 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
+.sym 23564 spi_if_ins.state_if_SB_DFFE_Q_E
+.sym 23565 r_counter[0]_$glb_clk
+.sym 23566 spi_if_ins.state_if_SB_DFFESR_Q_1_R
+.sym 23569 w_smi_read_req
+.sym 23571 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 23579 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+.sym 23592 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 23599 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 23600 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[2]
+.sym 23602 w_rx_24_fifo_empty
+.sym 23608 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+.sym 23609 spi_if_ins.state_if_SB_DFFESR_Q_1_D[1]
+.sym 23610 spi_if_ins.state_if_SB_DFFE_Q_E
+.sym 23615 spi_if_ins.state_if[0]
+.sym 23620 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
+.sym 23627 spi_if_ins.state_if[1]
+.sym 23628 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 23639 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 23653 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 23654 spi_if_ins.state_if[0]
+.sym 23655 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 23656 spi_if_ins.state_if[1]
+.sym 23659 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
+.sym 23660 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+.sym 23661 spi_if_ins.state_if_SB_DFFESR_Q_1_D[1]
+.sym 23662 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 23687 spi_if_ins.state_if_SB_DFFE_Q_E
+.sym 23688 r_counter[0]_$glb_clk
+.sym 23692 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 23694 $PACKER_GND_NET
+.sym 23712 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
+.sym 23714 w_smi_read_req
+.sym 23715 $PACKER_GND_NET
+.sym 23721 i_button_SB_LUT4_I3_I2[0]
+.sym 23725 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
+.sym 23733 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
+.sym 23734 i_button_SB_LUT4_I3_O[2]
+.sym 23735 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[2]
+.sym 23738 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[3]
+.sym 23739 i_button_SB_LUT4_I3_O[3]
+.sym 23741 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[3]
+.sym 23743 io_ctrl_ins.o_pmod[5]
+.sym 23744 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[2]
+.sym 23745 io_ctrl_ins.o_pmod[6]
+.sym 23747 i_button_SB_LUT4_I3_O[1]
+.sym 23749 i_button_SB_LUT4_I3_O[0]
+.sym 23751 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1]
+.sym 23760 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[2]
+.sym 23776 i_button_SB_LUT4_I3_O[0]
+.sym 23777 i_button_SB_LUT4_I3_O[3]
+.sym 23778 i_button_SB_LUT4_I3_O[1]
+.sym 23779 i_button_SB_LUT4_I3_O[2]
+.sym 23794 io_ctrl_ins.o_pmod[5]
+.sym 23795 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[2]
+.sym 23796 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[3]
+.sym 23797 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1]
+.sym 23806 io_ctrl_ins.o_pmod[6]
+.sym 23807 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[2]
+.sym 23808 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[3]
+.sym 23809 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1]
+.sym 23810 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
+.sym 23811 r_counter[0]_$glb_clk
+.sym 23812 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[2]
+.sym 23829 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E
+.sym 23834 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E
+.sym 23836 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 23837 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 23847 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 23848 o_rx_h_tx_l$SB_IO_OUT
+.sym 23855 io_ctrl_ins.led0_state_SB_LUT4_I3_I0[0]
+.sym 23857 o_rx_h_tx_l$SB_IO_OUT
+.sym 23860 w_ioc[0]
+.sym 23864 io_ctrl_ins.o_pmod[7]
+.sym 23867 io_ctrl_ins.pmod_dir_state[6]
+.sym 23868 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 23869 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 23872 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
+.sym 23873 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_I2[2]
+.sym 23874 i_button_SB_LUT4_I3_O[1]
+.sym 23877 o_tr_vc1$SB_IO_OUT
+.sym 23881 i_button_SB_LUT4_I3_I2[0]
+.sym 23883 io_ctrl_ins.pmod_dir_state[5]
+.sym 23887 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 23888 io_ctrl_ins.o_pmod[7]
+.sym 23889 w_ioc[0]
+.sym 23890 o_rx_h_tx_l$SB_IO_OUT
+.sym 23899 i_button_SB_LUT4_I3_O[1]
+.sym 23900 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_I2[2]
+.sym 23901 io_ctrl_ins.pmod_dir_state[6]
+.sym 23902 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 23906 w_ioc[0]
+.sym 23908 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 23918 i_button_SB_LUT4_I3_O[1]
+.sym 23924 io_ctrl_ins.led0_state_SB_LUT4_I3_I0[0]
+.sym 23925 i_button_SB_LUT4_I3_I2[0]
+.sym 23929 o_tr_vc1$SB_IO_OUT
+.sym 23930 i_button_SB_LUT4_I3_O[1]
+.sym 23931 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_I2[2]
+.sym 23932 io_ctrl_ins.pmod_dir_state[5]
+.sym 23933 sys_ctrl_ins.o_data_out_SB_DFFE_Q_E
+.sym 23934 r_counter[0]_$glb_clk
+.sym 23950 io_ctrl_ins.o_pmod[7]
+.sym 23956 w_ioc[0]
+.sym 23957 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 23983 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 23995 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
+.sym 23999 io_ctrl_ins.rf_pin_state[6]
+.sym 24003 io_ctrl_ins.rf_pin_state[7]
+.sym 24007 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 24028 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 24029 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 24030 io_ctrl_ins.rf_pin_state[7]
+.sym 24046 io_ctrl_ins.rf_pin_state[6]
+.sym 24048 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 24049 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 24056 io_ctrl_ins.rx_h_state_SB_DFFE_Q_E
+.sym 24057 r_counter[0]_$glb_clk
+.sym 24092 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 24590 o_led0$SB_IO_OUT
 .sym 24596 o_led0$SB_IO_OUT
-.sym 24607 o_led0$SB_IO_OUT
+.sym 24616 o_led0$SB_IO_OUT
 .sym 24621 i_smi_a3$SB_IO_IN
-.sym 24664 i_ss$SB_IO_IN
+.sym 24664 w_smi_read_req
+.sym 24667 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
 .sym 25089 io_pmod[4]$SB_IO_IN
+.sym 25101 w_smi_read_req
+.sym 25183 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 25213 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 25262 io_pmod[4]$SB_IO_IN
 .sym 25399 io_pmod[5]$SB_IO_IN
+.sym 25401 io_pmod[7]$SB_IO_IN
+.sym 25486 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 25488 io_pmod[5]$SB_IO_IN
+.sym 25535 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 25536 io_pmod[5]$SB_IO_IN
+.sym 25551 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
+.sym 25552 lvds_clock_buf
+.sym 25553 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
 .sym 25554 i_smi_soe_se$rename$0
+.sym 25556 io_pmod[6]$SB_IO_IN
+.sym 25633 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 25634 io_pmod[4]$SB_IO_IN
+.sym 25666 io_pmod[4]$SB_IO_IN
+.sym 25669 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 25706 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O_$glb_ce
+.sym 25707 lvds_clock_buf
+.sym 25708 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]_$glb_sr
 .sym 25711 i_glob_clock$SB_IO_IN
+.sym 25793 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.sym 25805 w_rx_24_fifo_empty
+.sym 25811 i_button_SB_LUT4_I3_I2[0]
+.sym 25833 w_rx_24_fifo_empty
+.sym 25861 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
+.sym 25862 i_glob_clock$SB_IO_IN_$glb_clk
+.sym 25863 i_button_SB_LUT4_I3_I2[0]
+.sym 25877 smi_ctrl_ins.o_data_out_SB_DFFESS_Q_E
 .sym 25878 i_glob_clock$SB_IO_IN
+.sym 25939 spi_if_ins.state_if_SB_DFFE_Q_E
+.sym 25946 io_pmod[2]$SB_IO_IN
+.sym 25950 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 25961 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+.sym 25963 w_rx_24_fifo_empty
+.sym 25982 io_pmod[2]$SB_IO_IN
+.sym 25983 w_rx_24_fifo_empty
+.sym 25997 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+.sym 26016 spi_if_ins.state_if_SB_DFFE_Q_E
+.sym 26017 r_counter[0]_$glb_clk
+.sym 26018 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 26028 io_pmod[2]$SB_IO_IN
+.sym 26037 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 26094 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E
+.sym 26096 $PACKER_GND_NET
+.sym 26112 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
+.sym 26139 $PACKER_GND_NET
+.sym 26171 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E
+.sym 26172 r_counter[0]_$glb_clk
+.sym 26173 sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S
 .sym 26174 io_pmod[2]$SB_IO_IN
-.sym 26183 $PACKER_VCC_NET
-.sym 26735 o_tr_vc1_b$SB_IO_OUT
-.sym 26746 o_tr_vc1_b$SB_IO_OUT
-.sym 26958 o_rx_h_tx_l_b$SB_IO_OUT
-.sym 27275 $PACKER_VCC_NET
-.sym 27283 $PACKER_VCC_NET
+.sym 26500 $PACKER_GND_NET
+.sym 26501 w_smi_read_req
+.sym 26653 o_rx_h_tx_l$SB_IO_OUT
+.sym 26961 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 27277 i_mosi$SB_IO_IN
+.sym 27283 w_smi_read_req
 .sym 27285 i_smi_a3$SB_IO_IN
-.sym 27298 i_smi_a3$SB_IO_IN
-.sym 27301 $PACKER_VCC_NET
-.sym 27305 i_smi_soe_se$rename$0
+.sym 27293 i_smi_a3$SB_IO_IN
+.sym 27299 w_smi_read_req
+.sym 27305 io_pmod[5]$SB_IO_IN
+.sym 27307 io_pmod[6]$SB_IO_IN
 .sym 27310 $io_pmod[4]$iobuf_i
-.sym 27328 $io_pmod[4]$iobuf_i
+.sym 27319 $io_pmod[4]$iobuf_i
 .sym 27335 $io_pmod[3]$iobuf_i
+.sym 27365 $io_pmod[5]$iobuf_i
 .sym 27370 $io_pmod[5]$iobuf_i
 .sym 27373 $io_pmod[7]$iobuf_i
-.sym 27381 $io_pmod[5]$iobuf_i
-.sym 27391 $io_pmod[7]$iobuf_i
-.sym 27395 $PACKER_VCC_NET
+.sym 27383 $io_pmod[5]$iobuf_i
+.sym 27384 $io_pmod[7]$iobuf_i
 .sym 27400 $io_pmod[3]$iobuf_i
 .sym 27403 $io_pmod[6]$iobuf_i
 .sym 27410 $io_pmod[6]$iobuf_i
 .sym 27413 $io_pmod[3]$iobuf_i
-.sym 27425 io_pmod[2]$SB_IO_IN
 .sym 27429 i_glob_clock$SB_IO_IN
 .sym 27451 i_glob_clock$SB_IO_IN
-.sym 27457 $PACKER_VCC_NET
-.sym 27459 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
+.sym 27459 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
 .sym 27460 $PACKER_VCC_NET
-.sym 27475 $PACKER_VCC_NET
-.sym 27483 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
+.sym 27471 $PACKER_VCC_NET
+.sym 27479 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 27485 io_pmod[2]$SB_IO_IN
+.sym 27488 $io_pmod[2]$iobuf_i
 .sym 27514 i_smi_a3$SB_IO_IN
 .sym 27519 $io_pmod[2]$iobuf_i
 .sym 27524 i_smi_a3$SB_IO_IN
 .sym 27532 i_smi_a3$SB_IO_IN
-.sym 27537 $io_pmod[2]$iobuf_i
-.sym 27545 o_tr_vc2$SB_IO_OUT
-.sym 27549 $PACKER_VCC_NET
+.sym 27539 $io_pmod[2]$iobuf_i
+.sym 27549 w_smi_read_req
 .sym 27551 i_smi_a3$SB_IO_IN
 .sym 27552 $PACKER_GND_NET
-.sym 27559 $PACKER_GND_NET
 .sym 27566 i_smi_a3$SB_IO_IN
-.sym 27571 $PACKER_VCC_NET
+.sym 27572 $PACKER_GND_NET
+.sym 27573 w_smi_read_req
 .sym 27582 o_rx_h_tx_l$SB_IO_OUT
-.sym 27593 o_rx_h_tx_l$SB_IO_OUT
+.sym 27600 o_rx_h_tx_l$SB_IO_OUT
 .sym 27605 o_tr_vc1$SB_IO_OUT
 .sym 27608 o_tr_vc2$SB_IO_OUT
-.sym 27619 o_tr_vc2$SB_IO_OUT
-.sym 27625 o_tr_vc1$SB_IO_OUT
+.sym 27617 o_tr_vc2$SB_IO_OUT
+.sym 27629 o_tr_vc1$SB_IO_OUT
 .sym 27631 o_rx_h_tx_l_b$SB_IO_OUT
 .sym 27634 o_tr_vc1_b$SB_IO_OUT
-.sym 27648 o_tr_vc1_b$SB_IO_OUT
-.sym 27649 o_rx_h_tx_l_b$SB_IO_OUT
-.sym 27833 r_counter[0]
-.sym 27843 rx_24_fifo.wr_addr[0]
-.sym 27848 lvds_rx_24_inst.r_push_SB_LUT4_I2_I1_SB_LUT4_O_I3[1]
-.sym 27849 rx_24_fifo.wr_addr[0]
-.sym 27852 rx_24_fifo.wr_addr[2]
-.sym 27853 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_I3[2]
-.sym 27856 rx_24_fifo.wr_addr[3]
-.sym 27857 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_I3[3]
-.sym 27860 rx_24_fifo.wr_addr[4]
-.sym 27861 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_I3[4]
-.sym 27864 rx_24_fifo.wr_addr[5]
-.sym 27865 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_I3[5]
-.sym 27868 rx_24_fifo.wr_addr[6]
-.sym 27869 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_I3[6]
-.sym 27872 rx_24_fifo.wr_addr[7]
-.sym 27873 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_I3[7]
-.sym 27875 lvds_rx_24_inst.r_push_SB_LUT4_I2_I1_SB_LUT4_O_I3[1]
-.sym 27880 rx_24_fifo.wr_addr[2]
-.sym 27884 rx_24_fifo.wr_addr[3]
-.sym 27885 lvds_rx_24_inst.r_push_SB_LUT4_I2_I1_SB_LUT4_O_I3[2]
-.sym 27888 rx_24_fifo.wr_addr[4]
-.sym 27889 lvds_rx_24_inst.r_push_SB_LUT4_I2_I1_SB_LUT4_O_I3[3]
-.sym 27892 rx_24_fifo.wr_addr[5]
-.sym 27893 lvds_rx_24_inst.r_push_SB_LUT4_I2_I1_SB_LUT4_O_I3[4]
-.sym 27895 $PACKER_VCC_NET
-.sym 27897 $nextpnr_ICESTORM_LC_5$I3
-.sym 27900 rx_24_fifo.wr_addr[6]
-.sym 27904 rx_24_fifo.wr_addr[7]
-.sym 27905 lvds_rx_24_inst.r_push_SB_LUT4_I2_I1_SB_LUT4_O_I3[6]
-.sym 27914 rx_24_fifo.wr_addr[0]
-.sym 27915 lvds_rx_24_inst.r_push_SB_LUT4_I2_I0[2]
-.sym 27916 rx_24_fifo.wr_addr[2]
-.sym 27917 lvds_rx_24_inst.r_push_SB_LUT4_I2_I1_SB_LUT4_O_I3[1]
-.sym 27918 lvds_rx_24_inst.r_push_SB_LUT4_I2_I0[6]
-.sym 27919 lvds_rx_24_inst.r_push_SB_LUT4_I2_I1[1]
-.sym 27920 w_rx_24_fifo_push
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-.sym 27923 lvds_rx_24_inst.r_push_SB_LUT4_I2_O[0]
-.sym 27924 lvds_rx_24_inst.r_push_SB_LUT4_I2_O[1]
-.sym 27925 lvds_rx_24_inst.r_push_SB_LUT4_I2_O[2]
-.sym 27930 lvds_rx_24_inst.r_push_SB_LUT4_I2_I0[3]
-.sym 27931 lvds_rx_24_inst.r_push_SB_LUT4_I2_I0[4]
-.sym 27932 rx_24_fifo.wr_addr[6]
-.sym 27933 lvds_rx_24_inst.r_push_SB_LUT4_I2_I1_SB_LUT4_O_I3[5]
-.sym 27939 lvds_rx_24_inst.r_phase_count[0]
-.sym 27943 lvds_rx_24_inst.r_phase_count[1]
-.sym 27944 $PACKER_VCC_NET
-.sym 27945 lvds_rx_24_inst.r_phase_count[0]
-.sym 27946 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q[1]
-.sym 27948 $PACKER_VCC_NET
-.sym 27949 lvds_rx_24_inst.r_phase_count_SB_CARRY_CI_CO[2]
-.sym 27953 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q[2]
-.sym 27956 w_lvds_rx_24_d1_SB_LUT4_I2_O[2]
-.sym 27957 w_lvds_rx_24_d1_SB_LUT4_I2_O[3]
-.sym 27958 w_lvds_rx_24_d1_SB_LUT4_I2_O[1]
-.sym 27959 w_lvds_rx_24_d1_SB_LUT4_I2_O[3]
-.sym 27960 w_lvds_rx_24_d1_SB_LUT4_I2_O[2]
-.sym 27961 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 27964 w_rx_24_fifo_full
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-.sym 27969 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0]
-.sym 27970 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q[2]
-.sym 27971 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q[1]
-.sym 27972 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0]
-.sym 27973 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[2]
-.sym 27974 w_lvds_rx_24_d1_SB_LUT4_I2_O[1]
-.sym 27975 w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O[1]
-.sym 27976 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[1]
-.sym 27977 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3[1]
-.sym 27979 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0]
-.sym 27980 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q[1]
-.sym 27981 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q[2]
-.sym 27983 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 27984 w_lvds_rx_24_d1_SB_LUT4_I2_O[2]
-.sym 27985 w_lvds_rx_24_d1_SB_LUT4_I2_O[3]
-.sym 27986 w_lvds_rx_24_d1_SB_LUT4_I2_O[1]
-.sym 27987 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[2]
-.sym 27988 w_lvds_rx_24_d1_SB_LUT4_I2_O[2]
-.sym 27989 w_lvds_rx_24_d1_SB_LUT4_I2_O[3]
-.sym 27991 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q_SB_DFFNESR_Q_D_SB_LUT4_O_I1[0]
-.sym 27992 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q_SB_DFFNESR_Q_D_SB_LUT4_O_I1[1]
-.sym 27993 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q_SB_DFFNESR_Q_D_SB_LUT4_O_I1[2]
-.sym 27994 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0]
-.sym 27995 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q[2]
-.sym 27996 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q[1]
-.sym 27997 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_DFFNESR_D_Q_SB_DFFNESR_Q_D_SB_LUT4_O_I1[1]
-.sym 28000 lvds_rx_24_inst.r_state_if_SB_DFFNESR_Q_D[0]
-.sym 28001 lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O[0]
-.sym 28008 w_lvds_rx_24_d1_SB_LUT4_I2_O[2]
-.sym 28009 w_lvds_rx_24_d1_SB_LUT4_I2_O[3]
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+.sym 28260 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28261 lvds_rx_09_inst.o_fifo_data[6]
+.sym 28264 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28265 lvds_rx_09_inst.o_fifo_data[7]
+.sym 28268 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28269 io_pmod[7]$SB_IO_IN
+.sym 28272 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28273 lvds_rx_09_inst.o_fifo_data[9]
+.sym 28276 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28277 lvds_rx_09_inst.o_fifo_data[11]
+.sym 28280 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28281 io_pmod[6]$SB_IO_IN
+.sym 28284 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28285 lvds_rx_09_inst.o_fifo_data[8]
+.sym 28288 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28289 lvds_rx_09_inst.o_fifo_data[10]
+.sym 28290 w_rx_24_fifo_pulled_data[13]
+.sym 28291 w_rx_24_fifo_pulled_data[5]
+.sym 28292 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 28293 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28304 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28305 w_rx_09_fifo_data[0]
+.sym 28306 w_rx_24_fifo_pulled_data[10]
+.sym 28307 w_rx_24_fifo_pulled_data[2]
+.sym 28308 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 28309 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28310 w_rx_24_fifo_pulled_data[12]
+.sym 28311 w_rx_24_fifo_pulled_data[4]
+.sym 28312 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 28313 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28315 i_smi_a1_SB_LUT4_I2_O[0]
+.sym 28316 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 28317 i_smi_a1_SB_LUT4_I2_O[2]
+.sym 28323 smi_ctrl_ins.int_cnt_24[4]
+.sym 28324 $PACKER_VCC_NET
+.sym 28325 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28326 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 28327 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 28328 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 28329 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 28330 w_rx_24_fifo_pulled_data[11]
+.sym 28331 w_rx_24_fifo_pulled_data[3]
+.sym 28332 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 28333 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28336 lvds_rx_24_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28337 w_rx_24_fifo_data[4]
+.sym 28338 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 28339 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 28340 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 28341 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 28342 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 28343 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 28344 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 28345 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 28346 w_rx_24_fifo_pulled_data[9]
+.sym 28347 w_rx_24_fifo_pulled_data[1]
+.sym 28348 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 28349 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28350 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 28351 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 28352 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 28353 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 28356 lvds_rx_24_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28357 w_rx_24_fifo_data[16]
+.sym 28360 lvds_rx_24_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28361 w_rx_24_fifo_data[29]
+.sym 28362 w_rx_24_fifo_pulled_data[25]
+.sym 28363 w_rx_24_fifo_pulled_data[17]
+.sym 28364 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28365 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 28366 w_rx_24_fifo_pulled_data[29]
+.sym 28367 w_rx_24_fifo_pulled_data[21]
+.sym 28368 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28369 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 28370 w_rx_24_fifo_pulled_data[26]
+.sym 28371 w_rx_24_fifo_pulled_data[18]
+.sym 28372 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28373 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 28374 w_rx_24_fifo_pulled_data[30]
+.sym 28375 w_rx_24_fifo_pulled_data[22]
+.sym 28376 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28377 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 28378 i_smi_a1_SB_LUT4_I2_O[0]
+.sym 28379 w_rx_24_fifo_pulled_data[16]
+.sym 28380 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28381 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 28382 w_rx_24_fifo_pulled_data[27]
+.sym 28383 w_rx_24_fifo_pulled_data[19]
+.sym 28384 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28385 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 28389 w_rx_24_fifo_data[24]
+.sym 28390 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 28396 rx_24_fifo.wr_addr[0]
+.sym 28397 rx_24_fifo.rd_addr_gray_wr_r[0]
+.sym 28398 i_smi_soe_se$rename$0
+.sym 28402 w_rx_24_fifo_pulled_data[8]
+.sym 28403 w_rx_24_fifo_pulled_data[24]
+.sym 28404 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28405 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_7_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 28409 w_rx_24_fifo_data[25]
+.sym 28412 rx_24_fifo.rd_addr_gray_wr_r[4]
+.sym 28413 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[3]
+.sym 28418 rx_24_fifo.rd_addr_gray_wr[7]
+.sym 28422 rx_24_fifo.rd_addr[7]
+.sym 28427 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_O_I1[0]
+.sym 28428 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_O_I1[1]
+.sym 28429 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_O_I1[2]
+.sym 28431 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
+.sym 28432 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[1]
+.sym 28433 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[2]
+.sym 28434 rx_24_fifo.rd_addr_gray_wr[3]
+.sym 28438 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0[0]
+.sym 28439 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[4]
+.sym 28440 rx_24_fifo.rd_addr_gray_wr_r[5]
+.sym 28441 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[5]
+.sym 28442 rx_24_fifo.rd_addr_gray[3]
+.sym 28446 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I0[0]
+.sym 28447 rx_24_fifo.rd_addr_gray_wr_r[1]
+.sym 28448 lvds_rx_24_inst.r_push_SB_LUT4_I3_I1[1]
+.sym 28449 rx_24_fifo.wr_addr[1]
+.sym 28450 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
+.sym 28451 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 28452 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 28453 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
+.sym 28454 w_rx_24_fifo_push
+.sym 28455 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[7]
+.sym 28456 rx_24_fifo.rd_addr_gray_wr_r[7]
+.sym 28457 w_rx_24_fifo_full
+.sym 28460 rx_24_fifo.rd_addr_gray_wr_r[1]
+.sym 28461 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[1]
+.sym 28462 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0]
+.sym 28463 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
+.sym 28464 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 28465 rx_24_fifo.rd_addr_gray_wr_r[6]
+.sym 28466 rx_24_fifo.full_o_SB_LUT4_I3_O[0]
+.sym 28467 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 28468 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 28469 rx_24_fifo.full_o_SB_LUT4_I3_O[3]
+.sym 28474 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 28478 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[4]
+.sym 28482 rx_24_fifo.rd_addr_gray_wr_r[0]
+.sym 28483 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 28484 rx_24_fifo.rd_addr_gray_wr_r[5]
+.sym 28485 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3]
+.sym 28486 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
+.sym 28487 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
+.sym 28488 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[2]
+.sym 28489 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[3]
+.sym 28492 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[5]
+.sym 28493 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[6]
+.sym 28496 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 28497 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 28508 rx_24_fifo.wr_addr[0]
+.sym 28509 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[1]
+.sym 28510 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[0]
+.sym 28511 rx_24_fifo.rd_addr_gray_wr_r[4]
+.sym 28512 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[2]
+.sym 28513 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[3]
+.sym 28516 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 28517 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[5]
+.sym 28518 rx_24_fifo.rd_addr_gray_wr[0]
+.sym 28524 lvds_rx_24_inst.r_state_if[0]
+.sym 28525 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_E_SB_LUT4_O_I1_SB_LUT4_O_I2[1]
+.sym 28528 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[0]
+.sym 28529 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[3]
+.sym 28530 rx_24_fifo.rd_addr_gray_wr[2]
+.sym 28534 rx_24_fifo.rd_addr_gray_wr[6]
+.sym 28542 rx_24_fifo.rd_addr_gray_wr[5]
+.sym 28548 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_E_SB_LUT4_O_I1[3]
+.sym 28549 w_lvds_rx_24_d1
+.sym 28556 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[3]
+.sym 28557 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[0]
+.sym 28564 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 28565 w_lvds_rx_24_d1_SB_LUT4_I0_O[1]
+.sym 28572 lvds_rx_24_inst.r_push_SB_DFFNESR_Q_E_SB_LUT4_O_I1[3]
+.sym 28573 w_lvds_rx_24_d0
+.sym 28582 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[2]
+.sym 28590 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[0]
+.sym 28598 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 28606 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3]
+.sym 28614 rx_24_fifo.wr_addr_gray[5]
+.sym 28626 rx_24_fifo.wr_addr_gray[0]
+.sym 28638 rx_24_fifo.wr_addr_gray[4]
+.sym 28708 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28709 lvds_rx_09_inst.o_fifo_data[23]
+.sym 28716 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28717 lvds_rx_09_inst.o_fifo_data[21]
+.sym 28721 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_1_O
+.sym 28724 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28725 lvds_rx_09_inst.o_fifo_data[17]
+.sym 28728 i_smi_a3$SB_IO_IN
+.sym 28729 w_smi_data_output[6]
+.sym 28736 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28737 lvds_rx_09_inst.o_fifo_data[19]
+.sym 28738 w_rx_09_fifo_pulled_data[5]
+.sym 28739 w_rx_09_fifo_pulled_data[21]
+.sym 28740 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28741 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 28742 w_rx_09_fifo_pulled_data[7]
+.sym 28743 w_rx_09_fifo_pulled_data[23]
+.sym 28744 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28745 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 28749 rx_09_fifo.rd_addr[0]
+.sym 28750 w_rx_09_fifo_pulled_data[11]
+.sym 28751 w_rx_09_fifo_pulled_data[27]
+.sym 28752 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28753 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 28754 w_rx_09_fifo_pulled_data[3]
+.sym 28755 w_rx_09_fifo_pulled_data[19]
+.sym 28756 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28757 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 28760 i_smi_a3$SB_IO_IN
+.sym 28761 w_smi_data_output[7]
+.sym 28762 w_rx_09_fifo_pulled_data[15]
+.sym 28763 w_rx_09_fifo_pulled_data[31]
+.sym 28764 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28765 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 28766 w_rx_09_fifo_pulled_data[6]
+.sym 28767 w_rx_09_fifo_pulled_data[22]
+.sym 28768 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28769 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 28770 w_rx_09_fifo_pulled_data[9]
+.sym 28771 w_rx_09_fifo_pulled_data[25]
+.sym 28772 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28773 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 28774 w_rx_09_fifo_pulled_data[1]
+.sym 28775 w_rx_09_fifo_pulled_data[17]
+.sym 28776 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28777 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 28778 w_rx_09_fifo_pulled_data[13]
+.sym 28779 w_rx_09_fifo_pulled_data[29]
+.sym 28780 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28781 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_2_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 28782 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[0]
+.sym 28783 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[1]
+.sym 28784 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28785 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3[3]
+.sym 28786 w_rx_09_fifo_pulled_data[4]
+.sym 28787 w_rx_09_fifo_pulled_data[20]
+.sym 28788 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28789 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 28790 w_rx_09_fifo_pulled_data[2]
+.sym 28791 w_rx_09_fifo_pulled_data[18]
+.sym 28792 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28793 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 28794 w_rx_09_fifo_pulled_data[12]
+.sym 28795 w_rx_09_fifo_pulled_data[28]
+.sym 28796 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28797 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 28798 w_rx_09_fifo_pulled_data[8]
+.sym 28799 w_rx_09_fifo_pulled_data[24]
+.sym 28800 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28801 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 28803 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28807 smi_ctrl_ins.int_cnt_09[4]
+.sym 28808 $PACKER_VCC_NET
+.sym 28809 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28811 smi_ctrl_ins.int_cnt_09[5]
+.sym 28812 $PACKER_VCC_NET
+.sym 28813 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[2]
+.sym 28815 w_rx_09_fifo_pulled_data[0]
+.sym 28816 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 28817 i_smi_a1_SB_LUT4_I2_O[2]
+.sym 28818 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 28819 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 28820 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 28821 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 28822 w_rx_24_fifo_pulled_data[15]
+.sym 28823 w_rx_24_fifo_pulled_data[7]
+.sym 28824 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 28825 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28827 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 28828 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 28829 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2_SB_LUT4_O_I1[2]
+.sym 28830 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 28831 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[1]
+.sym 28832 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[2]
+.sym 28833 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 28835 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28839 smi_ctrl_ins.int_cnt_24[4]
+.sym 28840 $PACKER_VCC_NET
+.sym 28843 smi_ctrl_ins.int_cnt_24[5]
+.sym 28844 $PACKER_VCC_NET
+.sym 28845 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[2]
+.sym 28846 w_rx_24_fifo_pulled_data[14]
+.sym 28847 w_rx_24_fifo_pulled_data[6]
+.sym 28848 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 28849 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28850 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 28851 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[1]
+.sym 28852 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_1_I1[2]
+.sym 28853 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O[3]
+.sym 28855 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 28856 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 28857 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 28859 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 28860 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 28861 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 28867 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_CARRY_CO_CI[3]
+.sym 28872 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1[4]
+.sym 28876 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_CARRY_CO_CI[5]
+.sym 28879 $PACKER_VCC_NET
+.sym 28881 $nextpnr_ICESTORM_LC_1$I3
+.sym 28883 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_O_I1[0]
+.sym 28884 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 28885 $nextpnr_ICESTORM_LC_1$COUT
+.sym 28887 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 28888 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 28889 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 28893 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28894 w_rx_24_fifo_pulled_data[28]
+.sym 28895 w_rx_24_fifo_pulled_data[20]
+.sym 28896 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28897 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 28899 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1[4]
+.sym 28904 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_CARRY_CO_CI[5]
+.sym 28909 $nextpnr_ICESTORM_LC_18$I3
+.sym 28913 smi_ctrl_ins.int_cnt_24[5]
+.sym 28915 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 28916 i_smi_a1_SB_LUT4_I2_O[1]
+.sym 28917 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 28918 smi_ctrl_ins.int_cnt_24[5]
+.sym 28919 smi_ctrl_ins.int_cnt_24[4]
+.sym 28920 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28921 w_rx_24_fifo_empty
+.sym 28922 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 28923 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1[5]
+.sym 28924 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_O_I1[2]
+.sym 28925 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 28926 w_rx_24_fifo_pulled_data[31]
+.sym 28927 w_rx_24_fifo_pulled_data[23]
+.sym 28928 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 28929 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 28934 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0[0]
+.sym 28935 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0[1]
+.sym 28936 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0[2]
+.sym 28937 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0[3]
+.sym 28938 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0[0]
+.sym 28939 rx_24_fifo.rd_addr[1]
+.sym 28940 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0]
+.sym 28941 rx_24_fifo.rd_addr[2]
+.sym 28944 rx_24_fifo.rd_addr[0]
+.sym 28945 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 28946 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
+.sym 28947 rx_24_fifo.rd_addr[2]
+.sym 28948 rx_24_fifo.rd_addr[3]
+.sym 28949 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[3]
+.sym 28952 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 28953 w_rx_24_fifo_pull
+.sym 28955 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 28956 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 28957 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_O_I1[2]
+.sym 28960 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[1]
+.sym 28961 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 28962 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_I0[0]
+.sym 28963 rx_24_fifo.rd_addr[5]
+.sym 28964 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 28965 rx_24_fifo.rd_addr[6]
+.sym 28968 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2]
+.sym 28969 rx_24_fifo.rd_addr[4]
+.sym 28972 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[3]
+.sym 28973 w_lvds_rx_09_d0
+.sym 28975 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
+.sym 28976 rx_24_fifo.rd_addr[3]
+.sym 28977 rx_24_fifo.rd_addr[4]
+.sym 28980 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[3]
+.sym 28981 w_lvds_rx_09_d1
+.sym 28984 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 28985 w_rx_09_fifo_data[1]
+.sym 28988 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 28989 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[4]
+.sym 28994 rx_24_fifo.wr_addr_gray_rd[2]
+.sym 28998 rx_24_fifo.wr_addr_gray_rd[3]
+.sym 29003 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[0]
+.sym 29004 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 29005 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[2]
+.sym 29006 rx_24_fifo.wr_addr_gray_rd[1]
+.sym 29010 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
+.sym 29011 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 29012 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[2]
+.sym 29013 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3]
+.sym 29014 rx_24_fifo.wr_addr_gray_rd[4]
+.sym 29020 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 29021 w_rx_24_fifo_push
+.sym 29022 rx_24_fifo.wr_addr_gray[3]
+.sym 29030 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O[0]
+.sym 29031 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O[1]
+.sym 29032 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 29033 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O[3]
+.sym 29034 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[0]
+.sym 29035 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 29036 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 29037 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[3]
+.sym 29038 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[0]
+.sym 29039 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[0]
+.sym 29040 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[2]
+.sym 29041 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[3]
+.sym 29042 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[2]
+.sym 29043 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[0]
+.sym 29044 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[0]
+.sym 29045 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[3]
+.sym 29048 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0]
+.sym 29049 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 29055 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[0]
+.sym 29056 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[2]
+.sym 29057 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[3]
+.sym 29060 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[0]
+.sym 29061 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1]
+.sym 29062 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[0]
+.sym 29063 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[1]
+.sym 29064 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[2]
+.sym 29065 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[3]
+.sym 29066 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[0]
+.sym 29067 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[1]
+.sym 29068 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[1]
+.sym 29069 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[3]
+.sym 29076 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 29077 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[0]
+.sym 29081 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1[0]
+.sym 29083 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 29084 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[0]
+.sym 29085 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[3]
+.sym 29091 lvds_rx_09_inst.r_phase_count[0]
+.sym 29095 lvds_rx_09_inst.r_phase_count[1]
+.sym 29096 $PACKER_VCC_NET
+.sym 29097 lvds_rx_09_inst.r_phase_count[0]
+.sym 29098 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[1]
+.sym 29100 $PACKER_VCC_NET
+.sym 29101 lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO[2]
+.sym 29105 lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3[0]
+.sym 29106 rx_24_fifo.wr_addr_gray_rd[0]
+.sym 29110 rx_24_fifo.wr_addr_gray[2]
+.sym 29138 rx_24_fifo.wr_addr_gray_rd[5]
+.sym 29219 rx_09_fifo.rd_addr[0]
+.sym 29224 rx_09_fifo.rd_addr[1]
+.sym 29225 rx_09_fifo.rd_addr[0]
+.sym 29228 rx_09_fifo.rd_addr[2]
+.sym 29229 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[2]
+.sym 29232 rx_09_fifo.rd_addr[3]
+.sym 29233 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[3]
+.sym 29236 rx_09_fifo.rd_addr[4]
+.sym 29237 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[4]
+.sym 29240 rx_09_fifo.rd_addr[5]
+.sym 29241 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[5]
+.sym 29244 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[1]
+.sym 29245 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[6]
+.sym 29248 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 29249 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3[7]
+.sym 29250 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[3]
+.sym 29251 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[0]
+.sym 29252 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[7]
+.sym 29253 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[6]
+.sym 29254 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 29258 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[5]
+.sym 29264 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_O[0]
+.sym 29265 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I3_O[1]
+.sym 29268 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 29269 i_smi_a1_SB_LUT4_I3_O[1]
+.sym 29274 rx_09_fifo.wr_addr_gray_rd_r[1]
+.sym 29275 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 29276 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 29277 i_smi_a1_SB_LUT4_I3_O[1]
+.sym 29278 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 29284 rx_09_fifo.wr_addr[0]
+.sym 29285 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1]
+.sym 29286 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[1]
+.sym 29287 rx_09_fifo.rd_addr[4]
+.sym 29288 rx_09_fifo.rd_addr[5]
+.sym 29289 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O[3]
+.sym 29290 w_rx_09_fifo_pulled_data[10]
+.sym 29291 w_rx_09_fifo_pulled_data[26]
+.sym 29292 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 29293 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1_SB_LUT4_O_I3[3]
+.sym 29296 i_smi_a3$SB_IO_IN
+.sym 29297 w_smi_data_output[1]
+.sym 29301 rx_09_fifo.wr_addr[0]
+.sym 29306 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[0]
+.sym 29307 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 29308 i_smi_a1_SB_LUT4_I3_O[1]
+.sym 29309 io_pmod[2]$SB_IO_IN
+.sym 29310 w_rx_09_fifo_pulled_data[0]
+.sym 29311 w_rx_09_fifo_pulled_data[16]
+.sym 29312 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[1]
+.sym 29313 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 29314 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 29315 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1[1]
+.sym 29316 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 29317 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_6_D_SB_LUT4_O_I1[3]
+.sym 29322 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_7_D_SB_LUT4_O_I0[0]
+.sym 29323 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_7_D_SB_LUT4_O_I0[1]
+.sym 29324 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_7_D_SB_LUT4_O_I0[2]
+.sym 29325 i_smi_a1_SB_LUT4_I2_O[2]
+.sym 29326 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 29327 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1[1]
+.sym 29328 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 29329 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_5_D_SB_LUT4_O_I1[3]
+.sym 29332 i_smi_a3$SB_IO_IN
+.sym 29333 w_smi_data_output[2]
+.sym 29334 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 29335 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_2_D_SB_LUT4_O_I1[1]
+.sym 29336 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 29337 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_2_D_SB_LUT4_O_I1[3]
+.sym 29338 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 29339 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1[1]
+.sym 29340 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 29341 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_D_SB_LUT4_O_I1[3]
+.sym 29342 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 29343 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[1]
+.sym 29344 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 29345 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[3]
+.sym 29350 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 29351 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1[1]
+.sym 29352 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 29353 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_3_D_SB_LUT4_O_I1[3]
+.sym 29355 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E_SB_LUT4_O_I1[0]
+.sym 29356 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E_SB_LUT4_O_I1[1]
+.sym 29357 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 29360 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E_SB_LUT4_O_I1[1]
+.sym 29361 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 29365 smi_ctrl_ins.int_cnt_09[5]
+.sym 29366 smi_ctrl_ins.int_cnt_09[4]
+.sym 29367 smi_ctrl_ins.int_cnt_09[5]
+.sym 29368 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 29369 io_pmod[2]$SB_IO_IN
+.sym 29373 smi_ctrl_ins.int_cnt_09[4]
+.sym 29374 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[2]
+.sym 29375 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_4_D_SB_LUT4_O_I1[1]
+.sym 29376 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 29377 smi_ctrl_ins.o_smi_data_out_SB_DFFE_Q_4_D_SB_LUT4_O_I1[3]
+.sym 29379 i_smi_a1_SB_LUT4_I3_I0_SB_CARRY_CO_I1[4]
+.sym 29384 i_smi_a1_SB_LUT4_I3_I0_SB_CARRY_CO_I1[5]
+.sym 29389 $nextpnr_ICESTORM_LC_20$I3
+.sym 29393 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3[1]
+.sym 29394 w_rx_24_fifo_pull
+.sym 29395 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_O_I1[2]
+.sym 29396 i_smi_a2$SB_IO_IN
+.sym 29397 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 29399 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 29400 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3[1]
+.sym 29401 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 29403 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 29404 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 29405 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2[1]
+.sym 29406 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 29407 smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_E_SB_LUT4_O_I1_SB_LUT4_O_I1[5]
+.sym 29408 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2_SB_LUT4_O_I1[2]
+.sym 29409 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 29417 smi_ctrl_ins.int_cnt_24[4]
+.sym 29418 w_rx_09_fifo_full
+.sym 29422 io_pmod[2]$SB_IO_IN
+.sym 29426 w_rx_24_fifo_full
+.sym 29431 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[0]
+.sym 29432 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[1]
+.sym 29433 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 29434 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 29435 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 29436 i_smi_a1_SB_LUT4_I1_O[2]
+.sym 29437 i_smi_a1_SB_LUT4_I1_O[3]
+.sym 29439 i_smi_a1$SB_IO_IN
+.sym 29440 i_smi_a2$SB_IO_IN
+.sym 29441 i_smi_a3$SB_IO_IN
+.sym 29442 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
+.sym 29443 rx_24_fifo.rd_addr[7]
+.sym 29444 rx_24_fifo.wr_addr_gray_rd_r[7]
+.sym 29445 rx_24_fifo.rd_addr[6]
+.sym 29447 w_rx_24_fifo_pull
+.sym 29448 w_rx_24_fifo_empty
+.sym 29449 rx_24_fifo.empty_o_SB_LUT4_I2_I3[2]
+.sym 29453 rx_24_fifo.rd_addr[0]
+.sym 29455 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3[0]
+.sym 29456 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 29457 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 29458 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 29462 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 29466 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[7]
+.sym 29470 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 29475 rx_24_fifo.rd_addr[0]
+.sym 29480 rx_24_fifo.rd_addr[1]
+.sym 29481 rx_24_fifo.rd_addr[0]
+.sym 29484 rx_24_fifo.rd_addr[2]
+.sym 29485 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_I3[2]
+.sym 29488 rx_24_fifo.rd_addr[3]
+.sym 29489 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_I3[3]
+.sym 29492 rx_24_fifo.rd_addr[4]
+.sym 29493 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_I3[4]
+.sym 29496 rx_24_fifo.rd_addr[5]
+.sym 29497 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_I3[5]
+.sym 29500 rx_24_fifo.rd_addr[6]
+.sym 29501 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_I3[6]
+.sym 29504 rx_24_fifo.rd_addr[7]
+.sym 29505 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_I3[7]
+.sym 29508 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 29509 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 29510 rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 29515 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[0]
+.sym 29516 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[1]
+.sym 29517 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_1_D[2]
+.sym 29524 rx_24_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 29525 rx_24_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 29528 rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O[1]
+.sym 29529 rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3[2]
+.sym 29532 rx_24_fifo.rd_addr[0]
+.sym 29533 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 29536 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[4]
+.sym 29537 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 29542 rx_24_fifo.rd_addr_gray_wr[1]
+.sym 29550 rx_24_fifo.rd_addr_gray[4]
+.sym 29554 rx_24_fifo.rd_addr_gray[5]
+.sym 29562 rx_24_fifo.rd_addr_gray_wr[4]
+.sym 29566 rx_24_fifo.rd_addr_gray[2]
+.sym 29571 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[0]
+.sym 29572 w_rx_09_fifo_full
+.sym 29573 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[3]
+.sym 29595 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O[0]
+.sym 29596 w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2[0]
+.sym 29597 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 29608 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[1]
+.sym 29609 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 29610 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D[1]
+.sym 29614 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 29618 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 29624 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 29625 rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 29732 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 29733 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[4]
+.sym 29736 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[4]
+.sym 29737 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[5]
+.sym 29738 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0[0]
+.sym 29739 rx_09_fifo.rd_addr[2]
+.sym 29740 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[2]
+.sym 29741 rx_09_fifo.rd_addr[3]
+.sym 29744 rx_09_fifo.wr_addr_gray_rd_r[1]
+.sym 29745 rx_09_fifo.rd_addr[1]
+.sym 29747 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[0]
+.sym 29748 rx_09_fifo.rd_addr[3]
+.sym 29749 rx_09_fifo.rd_addr[4]
+.sym 29750 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 29754 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[4]
+.sym 29760 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 29761 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[3]
+.sym 29764 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 29765 w_rx_09_fifo_push
+.sym 29766 rx_09_fifo.wr_addr_gray_rd[1]
+.sym 29770 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[0]
+.sym 29771 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 29772 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[2]
+.sym 29773 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[3]
+.sym 29776 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[2]
+.sym 29777 rx_09_fifo.rd_addr[5]
+.sym 29778 rx_09_fifo.wr_addr_gray_rd[7]
+.sym 29783 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O_SB_LUT4_I3_O[0]
+.sym 29784 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O_SB_LUT4_I3_O[1]
+.sym 29785 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O_SB_LUT4_I3_O[2]
+.sym 29786 rx_09_fifo.wr_addr_gray[5]
+.sym 29790 rx_09_fifo.wr_addr_gray[1]
+.sym 29795 rx_09_fifo.wr_addr[0]
+.sym 29800 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2[0]
+.sym 29801 rx_09_fifo.wr_addr[0]
+.sym 29804 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
+.sym 29805 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[2]
+.sym 29808 rx_09_fifo.wr_addr[3]
+.sym 29809 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[3]
+.sym 29812 rx_09_fifo.wr_addr[4]
+.sym 29813 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[4]
+.sym 29816 rx_09_fifo.wr_addr[5]
+.sym 29817 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[5]
+.sym 29820 rx_09_fifo.wr_addr[6]
+.sym 29821 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[6]
+.sym 29824 rx_09_fifo.wr_addr[7]
+.sym 29825 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_I3[7]
+.sym 29827 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2[0]
+.sym 29828 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2[1]
+.sym 29829 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2[2]
+.sym 29831 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1[0]
+.sym 29832 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1[1]
+.sym 29833 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1[2]
+.sym 29836 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5]
+.sym 29837 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6]
+.sym 29838 rx_09_fifo.full_o_SB_LUT4_I3_O[0]
+.sym 29839 rx_09_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 29840 rx_09_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 29841 rx_09_fifo.full_o_SB_LUT4_I3_O[3]
+.sym 29842 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1[0]
+.sym 29843 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1[1]
+.sym 29844 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1[2]
+.sym 29845 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2[0]
+.sym 29846 w_rx_09_fifo_push
+.sym 29847 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7]
+.sym 29848 rx_09_fifo.rd_addr_gray_wr_r[7]
+.sym 29849 w_rx_09_fifo_full
+.sym 29852 rx_09_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 29853 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4]
+.sym 29856 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1]
+.sym 29857 rx_09_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 29862 rx_09_fifo.rd_addr_gray_wr_r[3]
+.sym 29863 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 29864 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[2]
+.sym 29865 rx_09_fifo.rd_addr_gray_wr_r[5]
+.sym 29866 i_smi_a1_SB_LUT4_I1_O[0]
+.sym 29867 i_smi_a1_SB_LUT4_I1_O[1]
+.sym 29868 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2[2]
+.sym 29869 i_smi_a1_SB_LUT4_I2_O[2]
+.sym 29872 rx_09_fifo.wr_addr[0]
+.sym 29873 rx_09_fifo.rd_addr_gray_wr_r[0]
+.sym 29874 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[0]
+.sym 29875 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[1]
+.sym 29876 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[2]
+.sym 29877 rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O[3]
+.sym 29878 rx_09_fifo.rd_addr_gray_wr[7]
+.sym 29882 i_smi_a1_SB_LUT4_I3_O[0]
+.sym 29883 i_smi_a1_SB_LUT4_I3_O[1]
+.sym 29884 i_smi_a1_SB_LUT4_I3_O[2]
+.sym 29885 i_smi_a1_SB_LUT4_I3_O[3]
+.sym 29886 rx_09_fifo.rd_addr_gray_wr_r[0]
+.sym 29887 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 29888 rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1[0]
+.sym 29889 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3]
+.sym 29891 i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2[0]
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+.sym 29903 $PACKER_VCC_NET
+.sym 29905 $nextpnr_ICESTORM_LC_4$I3
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+.sym 29909 $nextpnr_ICESTORM_LC_4$COUT
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+.sym 29917 i_smi_a1$SB_IO_IN
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+.sym 29949 i_smi_a3$SB_IO_IN
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+.sym 30001 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O[2]
+.sym 30002 spi_if_ins.o_cs_SB_DFFESR_Q_R[0]
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+.sym 30017 w_rx_24_fifo_pull
+.sym 30022 rx_24_fifo.wr_addr_gray[1]
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+.sym 30039 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
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+.sym 30042 spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O
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+.sym 30060 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[1]
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+.sym 30078 $PACKER_VCC_NET
+.sym 30082 rx_24_fifo.rd_addr_gray[6]
+.sym 30091 w_ioc[0]
+.sym 30092 w_ioc[1]
+.sym 30093 io_ctrl_ins.led0_state_SB_LUT4_I3_I0[0]
+.sym 30097 io_ctrl_ins.pmod_state_SB_DFFE_Q_E
+.sym 30098 rx_24_fifo.rd_addr_gray[0]
+.sym 30106 rx_24_fifo.rd_addr_gray[1]
+.sym 30111 w_ioc[0]
+.sym 30112 io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R[1]
+.sym 30113 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 30118 w_rx_data[2]
+.sym 30129 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E
+.sym 30133 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R
+.sym 30142 w_rx_data[1]
+.sym 30166 io_ctrl_ins.o_pmod[2]
+.sym 30167 o_shdn_tx_lna$SB_IO_OUT
+.sym 30168 w_ioc[0]
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+.sym 30170 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[0]
+.sym 30171 i_button_SB_LUT4_I3_O[1]
+.sym 30172 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[2]
+.sym 30173 io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2[3]
+.sym 30242 rx_09_fifo.wr_addr_gray_rd[6]
+.sym 30246 rx_09_fifo.wr_addr_gray_rd[5]
+.sym 30252 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[5]
+.sym 30253 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[6]
+.sym 30254 rx_09_fifo.wr_addr_gray_rd[2]
+.sym 30258 rx_09_fifo.wr_addr_gray[6]
+.sym 30262 smi_ctrl_ins.r_fifo_09_pull_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_1_I0[0]
+.sym 30263 rx_09_fifo.rd_addr[0]
+.sym 30264 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[0]
+.sym 30265 rx_09_fifo.rd_addr[1]
+.sym 30266 rx_09_fifo.wr_addr_gray[2]
+.sym 30270 rx_09_fifo.wr_addr_gray[3]
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+.sym 30277 rx_09_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 30278 rx_09_fifo.full_o_SB_LUT4_I3_O[2]
+.sym 30282 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[2]
+.sym 30286 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[3]
+.sym 30290 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[7]
+.sym 30294 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[1]
+.sym 30298 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 30302 rx_09_fifo.full_o_SB_LUT4_I3_O[1]
+.sym 30306 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[1]
+.sym 30310 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[1]
+.sym 30314 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D[2]
+.sym 30319 lvds_rx_09_inst.r_push_SB_LUT4_I3_O[0]
+.sym 30320 lvds_rx_09_inst.r_push_SB_LUT4_I3_O[1]
+.sym 30321 lvds_rx_09_inst.r_push_SB_LUT4_I3_O[2]
+.sym 30322 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5]
+.sym 30326 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4]
+.sym 30330 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6]
+.sym 30334 rx_09_fifo.rd_addr_gray_wr_r[6]
+.sym 30335 rx_09_fifo.rd_addr_gray_wr_r[7]
+.sym 30336 lvds_rx_09_inst.r_push_SB_LUT4_I3_I1[6]
+.sym 30337 lvds_rx_09_inst.r_push_SB_LUT4_I3_I1[5]
+.sym 30340 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[4]
+.sym 30341 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[5]
+.sym 30342 rx_09_fifo.rd_addr_gray_wr[2]
+.sym 30346 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[1]
+.sym 30352 rx_09_fifo.full_o_SB_LUT4_I3_O[0]
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+.sym 30354 lvds_rx_09_inst.r_push_SB_LUT4_I3_O_SB_LUT4_O_1_I0[2]
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+.sym 30356 rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_3_D[2]
+.sym 30357 rx_09_fifo.rd_addr_gray_wr_r[6]
+.sym 30358 rx_09_fifo.rd_addr_gray_wr[0]
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+.sym 30365 rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O[6]
+.sym 30366 rx_09_fifo.rd_addr_gray_wr[1]
+.sym 30370 i_smi_a1_SB_LUT4_I1_O[0]
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+.sym 30372 i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O[2]
+.sym 30373 i_smi_a3$SB_IO_IN
+.sym 30376 i_smi_a3$SB_IO_IN
+.sym 30377 w_smi_data_output[3]
+.sym 30378 r_tx_data[3]
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+.sym 30388 i_smi_a3$SB_IO_IN
+.sym 30389 w_smi_data_output[4]
+.sym 30394 r_tx_data[5]
+.sym 30398 r_tx_data[6]
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+.sym 30417 spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D[1]
+.sym 30438 spi_if_ins.spi.r_temp_rx_byte[5]
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+.sym 30444 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+.sym 30445 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O[2]
+.sym 30446 spi_if_ins.spi.r_temp_rx_byte[6]
+.sym 30453 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 30459 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 30460 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+.sym 30461 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[2]
+.sym 30462 spi_if_ins.spi.r_temp_rx_byte[4]
+.sym 30467 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
+.sym 30468 w_tx_data_io[5]
+.sym 30469 spi_if_ins.o_cs_SB_LUT4_I2_2_O[2]
+.sym 30472 spi_if_ins.o_cs_SB_LUT4_I2_2_O[2]
+.sym 30473 sys_ctrl_ins.o_data_out_SB_LUT4_I0_I2[1]
+.sym 30474 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 30475 spi_if_ins.state_if_SB_DFFESR_Q_1_D[1]
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+.sym 30477 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
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+.sym 30481 spi_if_ins.o_cs_SB_LUT4_I2_2_O[2]
+.sym 30484 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
+.sym 30485 w_tx_data_io[6]
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+.sym 30492 spi_if_ins.o_cs_SB_LUT4_I2_O[2]
+.sym 30493 w_tx_data_io[4]
+.sym 30494 w_tx_data_smi[3]
+.sym 30495 spi_if_ins.o_cs_SB_LUT4_I2_O[1]
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+.sym 30499 w_cs[1]
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+.sym 30501 w_cs[3]
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+.sym 30514 w_cs[1]
+.sym 30515 w_cs[2]
+.sym 30516 w_cs[3]
+.sym 30517 w_cs[0]
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+.sym 30522 spi_if_ins.spi.r_rx_byte[7]
+.sym 30526 w_cs[0]
+.sym 30527 w_cs[1]
+.sym 30528 w_cs[2]
+.sym 30529 w_cs[3]
+.sym 30530 rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D[3]
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+.sym 30536 w_cs[0]
+.sym 30537 w_fetch
+.sym 30538 w_fetch
+.sym 30539 w_load
+.sym 30540 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1]
+.sym 30541 w_cs[0]
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-.sym 30586 w_ioc[4]
-.sym 30587 w_ioc[1]
-.sym 30588 w_ioc[0]
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-.sym 30592 io_ctrl_ins.led0_state_SB_LUT4_I3_O[1]
-.sym 30593 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[2]
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-.sym 30609 i_button$SB_IO_IN
-.sym 30610 o_tr_vc2$SB_IO_OUT
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-.sym 30626 io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I3_O[0]
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-.sym 30638 w_rx_data[7]
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-.sym 30646 w_rx_data[1]
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-.sym 30657 o_led0$SB_IO_OUT
-.sym 30658 w_rx_data[1]
-.sym 30662 w_rx_data[0]
-.sym 30666 io_ctrl_ins.debug_mode[0]
-.sym 30667 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
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-.sym 30764 i_smi_a3$SB_IO_IN
-.sym 30765 w_smi_data_output[5]
-.sym 30777 i_smi_a3$SB_IO_IN
-.sym 30784 i_smi_a3$SB_IO_IN
-.sym 30785 w_smi_data_output[4]
-.sym 30868 lvds_rx_09_inst.r_data_SB_LUT4_I3_I2[0]
-.sym 30869 io_pmod[4]$SB_IO_IN
-.sym 30872 lvds_rx_09_inst.r_data_SB_LUT4_I3_I2[0]
-.sym 30873 io_pmod[5]$SB_IO_IN
-.sym 30882 rx_09_fifo.wr_addr_gray[5]
-.sym 30886 rx_09_fifo.wr_addr_gray_rd_r[2]
-.sym 30887 rx_09_fifo.wr_addr_gray_rd_r[3]
-.sym 30888 rx_09_fifo.wr_addr_gray_rd_r[4]
-.sym 30889 rx_09_fifo.wr_addr_gray_rd_r[5]
-.sym 30890 rx_09_fifo.wr_addr_gray_rd[4]
-.sym 30894 rx_09_fifo.wr_addr_gray[2]
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-.sym 30906 rx_09_fifo.wr_addr_gray_rd[2]
-.sym 30910 rx_09_fifo.wr_addr_gray_rd[0]
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-.sym 30922 rx_09_fifo.wr_addr_gray_rd[3]
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-.sym 30938 rx_09_fifo.wr_addr_gray[3]
-.sym 30942 rx_09_fifo.wr_addr_gray[1]
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+.sym 31286 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D[1]
+.sym 31290 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[6]
+.sym 31294 rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D[0]
+.sym 31298 rx_09_fifo.rd_addr_gray[6]
+.sym 31302 rx_09_fifo.rd_addr_gray[3]
+.sym 31311 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1[2]
+.sym 31312 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[1]
+.sym 31313 io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3[2]
+.sym 31314 rx_09_fifo.rd_addr_gray[2]
+.sym 31318 rx_09_fifo.rd_addr_gray[4]
+.sym 31326 rx_09_fifo.rd_addr_gray[5]
+.sym 31334 rx_09_fifo.wr_addr_gray[4]
+.sym 31338 rx_09_fifo.wr_addr_gray_rd[4]
+.sym 31342 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+.sym 31352 i_smi_a3$SB_IO_IN
+.sym 31353 w_smi_data_output[5]
+.sym 31354 spi_if_ins.spi.SCKr[0]
+.sym 31358 i_sck$SB_IO_IN
+.sym 31363 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 31367 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 31368 $PACKER_VCC_NET
+.sym 31371 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 31372 $PACKER_VCC_NET
+.sym 31373 spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
+.sym 31375 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 31376 $PACKER_VCC_NET
+.sym 31377 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 31379 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
+.sym 31380 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+.sym 31381 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 31385 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 31389 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 31390 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[0]
+.sym 31391 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 31392 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 31393 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[1]
+.sym 31394 spi_if_ins.spi.r_tx_byte[2]
+.sym 31395 spi_if_ins.spi.r_tx_byte[6]
+.sym 31396 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 31397 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 31398 spi_if_ins.spi.r_tx_byte[1]
+.sym 31399 spi_if_ins.spi.r_tx_byte[5]
+.sym 31400 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 31401 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 31402 spi_if_ins.spi.r_tx_byte[3]
+.sym 31403 spi_if_ins.spi.r_tx_byte[7]
+.sym 31404 spi_if_ins.spi.r_tx_bit_count[2]
+.sym 31405 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 31407 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 31408 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[1]
+.sym 31409 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 31410 spi_if_ins.r_tx_byte[5]
+.sym 31414 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[0]
+.sym 31415 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[1]
+.sym 31416 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2]
+.sym 31417 spi_if_ins.spi.SCKr_SB_LUT4_I0_O[0]
+.sym 31418 spi_if_ins.r_tx_byte[7]
+.sym 31422 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
+.sym 31423 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[1]
+.sym 31424 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 31425 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 31427 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 31432 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 31436 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 31437 spi_if_ins.spi.r_rx_bit_count_SB_DFFR_Q_D_SB_LUT4_O_I3[2]
+.sym 31445 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 31447 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 31448 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 31449 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 31469 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 31473 o_miso_$_TBUF__Y_E
+.sym 31479 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 31480 spi_if_ins.spi.r_rx_bit_count[2]
+.sym 31481 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 31484 spi_if_ins.spi.r_rx_bit_count[1]
+.sym 31485 spi_if_ins.spi.r_rx_bit_count[0]
+.sym 31490 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 31502 i_mosi$SB_IO_IN
+.sym 31514 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 31518 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 31522 i_mosi$SB_IO_IN
+.sym 31526 spi_if_ins.spi.r_temp_rx_byte[2]
+.sym 31530 spi_if_ins.spi.r_temp_rx_byte[0]
+.sym 31538 spi_if_ins.spi.r_temp_rx_byte[1]
+.sym 31546 spi_if_ins.spi.r_temp_rx_byte[3]
+.sym 31554 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 31555 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 31556 spi_if_ins.state_if[0]
+.sym 31557 spi_if_ins.state_if[1]
+.sym 31558 w_rx_data[7]
+.sym 31562 w_rx_data[4]
+.sym 31566 w_rx_data[3]
+.sym 31570 w_rx_data[5]
+.sym 31582 w_rx_data[6]
+.sym 31586 spi_if_ins.state_if_SB_DFFESR_Q_1_D[1]
+.sym 31590 spi_if_ins.w_rx_data[5]
+.sym 31594 spi_if_ins.w_rx_data[1]
+.sym 31598 spi_if_ins.w_rx_data[6]
+.sym 31602 spi_if_ins.w_rx_data[4]
+.sym 31606 spi_if_ins.w_rx_data[2]
+.sym 31610 spi_if_ins.w_rx_data[3]
+.sym 31614 spi_if_ins.w_rx_data[0]
+.sym 31620 i_button_SB_LUT4_I3_I2[2]
+.sym 31621 i_config[3]$SB_IO_IN
+.sym 31622 w_rx_data[7]
+.sym 31626 w_rx_data[3]
+.sym 31630 w_rx_data[6]
+.sym 31634 w_rx_data[5]
+.sym 31638 w_rx_data[0]
+.sym 31642 w_rx_data[4]
+.sym 31648 i_button_SB_LUT4_I3_I2[2]
+.sym 31649 i_config[2]$SB_IO_IN
+.sym 31650 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 31651 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 31652 io_ctrl_ins.rf_mode[0]
+.sym 31653 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 31656 i_button_SB_LUT4_I3_I2[2]
+.sym 31657 i_button$SB_IO_IN
+.sym 31658 io_ctrl_ins.pmod_dir_state[3]
+.sym 31659 i_button_SB_LUT4_I3_O[1]
+.sym 31660 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[2]
+.sym 31661 io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O[3]
+.sym 31662 i_button_SB_LUT4_I3_I2[0]
+.sym 31663 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 31664 i_button_SB_LUT4_I3_I2[2]
+.sym 31665 i_config[1]$SB_IO_IN
+.sym 31666 io_ctrl_ins.o_pmod[3]
+.sym 31667 o_tr_vc2$SB_IO_OUT
+.sym 31668 w_ioc[0]
+.sym 31669 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 31670 io_ctrl_ins.pmod_dir_state[4]
+.sym 31671 i_button_SB_LUT4_I3_O[1]
+.sym 31672 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[2]
+.sym 31673 io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O[3]
+.sym 31674 io_ctrl_ins.o_pmod[4]
+.sym 31675 o_tr_vc1_b$SB_IO_OUT
+.sym 31676 w_ioc[0]
+.sym 31677 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 31678 i_button_SB_LUT4_I3_I2[0]
+.sym 31679 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 31680 i_button_SB_LUT4_I3_I2[2]
+.sym 31681 i_config[0]$SB_IO_IN
+.sym 31686 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0]
+.sym 31687 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 31688 io_ctrl_ins.rf_pin_state[5]
+.sym 31689 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 31690 io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0[0]
+.sym 31691 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 31692 io_ctrl_ins.rf_pin_state[4]
+.sym 31693 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 31694 io_ctrl_ins.rf_pin_state[3]
+.sym 31695 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 31696 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
 .sym 31697 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 31702 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
-.sym 31703 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
-.sym 31704 io_ctrl_ins.rf_pin_state[4]
+.sym 31700 io_ctrl_ins.rf_mode[0]
+.sym 31701 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
+.sym 31702 io_ctrl_ins.rf_pin_state[0]
+.sym 31703 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[0]
+.sym 31704 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[1]
 .sym 31705 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
-.sym 32167 spi_if_ins.o_load_cmd_SB_LUT4_I3_O[1]
-.sym 32168 io_ctrl_ins.led1_state_SB_LUT4_I0_I2[1]
-.sym 32169 w_lvds_rx_09_d1_SB_LUT4_I0_O[0]
-.sym 32182 w_rx_data[0]
-.sym 32190 w_rx_data[1]
-.sym 32709 o_tr_vc1_b$SB_IO_OUT
+.sym 31785 r_counter[0]
+.sym 31828 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[1]
+.sym 31829 rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O[2]
+.sym 31862 rx_09_fifo.rd_addr_gray[1]
+.sym 31927 spi_if_ins.r_tx_byte[7]
+.sym 31928 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2[1]
+.sym 31929 spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O[2]
+.sym 31966 spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D[1]
+.sym 31972 spi_if_ins.spi.r3_rx_done
+.sym 31973 spi_if_ins.spi.r2_rx_done
+.sym 31986 spi_if_ins.spi.r_rx_done
+.sym 31990 spi_if_ins.spi.r2_rx_done
+.sym 32003 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 32004 spi_if_ins.state_if[1]
+.sym 32005 spi_if_ins.state_if[0]
+.sym 32019 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 32020 spi_if_ins.state_if[0]
+.sym 32021 spi_if_ins.state_if[1]
+.sym 32030 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
+.sym 32042 spi_if_ins.o_load_cmd_SB_DFFESR_Q_D[1]
+.sym 32043 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 32044 spi_if_ins.state_if[0]
+.sym 32045 spi_if_ins.state_if[1]
+.sym 32046 spi_if_ins.state_if_SB_DFFESR_Q_1_D[0]
+.sym 32047 spi_if_ins.state_if_SB_DFFESR_Q_1_D[1]
+.sym 32048 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+.sym 32049 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[0]
+.sym 32074 i_button_SB_LUT4_I3_O[0]
+.sym 32075 i_button_SB_LUT4_I3_O[1]
+.sym 32076 i_button_SB_LUT4_I3_O[2]
+.sym 32077 i_button_SB_LUT4_I3_O[3]
+.sym 32086 io_ctrl_ins.o_pmod[5]
+.sym 32087 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1]
+.sym 32088 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[2]
+.sym 32089 io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O[3]
+.sym 32094 io_ctrl_ins.o_pmod[6]
+.sym 32095 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[1]
+.sym 32096 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[2]
+.sym 32097 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O[3]
+.sym 32098 io_ctrl_ins.o_pmod[7]
+.sym 32099 o_rx_h_tx_l$SB_IO_OUT
+.sym 32100 w_ioc[0]
+.sym 32101 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 32106 i_button_SB_LUT4_I3_O[1]
+.sym 32107 io_ctrl_ins.pmod_dir_state[6]
+.sym 32108 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_I2[2]
+.sym 32109 o_rx_h_tx_l_b$SB_IO_OUT
+.sym 32112 io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3[1]
+.sym 32113 w_ioc[0]
+.sym 32118 i_button_SB_LUT4_I3_O[1]
+.sym 32124 io_ctrl_ins.led0_state_SB_LUT4_I3_I0[0]
+.sym 32125 i_button_SB_LUT4_I3_I2[0]
+.sym 32126 i_button_SB_LUT4_I3_O[1]
+.sym 32127 io_ctrl_ins.pmod_dir_state[5]
+.sym 32128 io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_I2[2]
+.sym 32129 o_tr_vc1$SB_IO_OUT
+.sym 32143 io_ctrl_ins.rf_pin_state[7]
+.sym 32144 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 32145 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 32155 io_ctrl_ins.debug_mode_SB_LUT4_I2_O[3]
+.sym 32156 io_ctrl_ins.rf_pin_state[6]
+.sym 32157 io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 32401 spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E
+.sym 32472 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 32473 io_pmod[5]$SB_IO_IN
+.sym 32488 lvds_rx_09_inst.r_state_if_SB_LUT4_I2_O[0]
+.sym 32489 io_pmod[4]$SB_IO_IN
+.sym 32526 w_rx_24_fifo_empty
+.sym 32556 w_rx_24_fifo_empty
+.sym 32557 io_pmod[2]$SB_IO_IN
+.sym 32562 spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3[1]
+.sym 32586 $PACKER_GND_NET
diff --git a/firmware/top.bin b/firmware/top.bin
index 70e72a5..6aae84f 100644
Binary files a/firmware/top.bin and b/firmware/top.bin differ
diff --git a/firmware/top.json b/firmware/top.json
index d9fec1a..f9578d4 100644
--- a/firmware/top.json
+++ b/firmware/top.json
@@ -64,7 +64,7 @@
         }
       },
       "cells": {
-        "$specify$266": {
+        "$specify$291": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -95,7 +95,7 @@
             "SRC": [ 6 ]
           }
         },
-        "$specify$267": {
+        "$specify$292": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -126,7 +126,7 @@
             "SRC": [ 2 ]
           }
         },
-        "$specify$268": {
+        "$specify$293": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -157,7 +157,7 @@
             "SRC": [ 2 ]
           }
         },
-        "$specify$269": {
+        "$specify$294": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -188,7 +188,7 @@
             "SRC": [ 3 ]
           }
         },
-        "$specify$270": {
+        "$specify$295": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -219,7 +219,7 @@
             "SRC": [ 3 ]
           }
         },
-        "$specify$271": {
+        "$specify$296": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -250,7 +250,7 @@
             "SRC": [ 3 ]
           }
         },
-        "$specify$272": {
+        "$specify$297": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -281,7 +281,7 @@
             "SRC": [ 4 ]
           }
         },
-        "$specify$273": {
+        "$specify$298": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -312,7 +312,7 @@
             "SRC": [ 4 ]
           }
         },
-        "$specify$274": {
+        "$specify$299": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -343,7 +343,7 @@
             "SRC": [ 4 ]
           }
         },
-        "$specify$275": {
+        "$specify$300": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -374,7 +374,7 @@
             "SRC": [ 5 ]
           }
         },
-        "$specify$276": {
+        "$specify$301": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -405,7 +405,7 @@
             "SRC": [ 5 ]
           }
         },
-        "$specify$277": {
+        "$specify$302": {
           "hide_name": 1,
           "type": "$specify3",
           "parameters": {
@@ -442,7 +442,7 @@
             "SRC": [ 7 ]
           }
         },
-        "$specify$278": {
+        "$specify$303": {
           "hide_name": 1,
           "type": "$specify2",
           "parameters": {
@@ -473,7 +473,7 @@
             "SRC": [ 9 ]
           }
         },
-        "$specify$279": {
+        "$specify$304": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -508,7 +508,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$280": {
+        "$specify$305": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -543,7 +543,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$281": {
+        "$specify$306": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -578,7 +578,7 @@
             "SRC_EN": [ "1" ]
           }
         },
-        "$specify$282": {
+        "$specify$307": {
           "hide_name": 1,
           "type": "$specrule",
           "parameters": {
@@ -613,7 +613,7 @@
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@@ -10513,11 +11310,11 @@
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@@ -10611,11 +11408,11 @@
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@@ -10635,43 +11432,18 @@
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@@ -10685,14 +11457,14 @@
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@@ -10736,17 +11508,17 @@
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@@ -10761,10 +11533,10 @@
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@@ -10784,22 +11556,22 @@
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@@ -10809,11 +11581,11 @@
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@@ -10833,18 +11605,18 @@
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@@ -10858,11 +11630,11 @@
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@@ -10882,43 +11654,18 @@
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@@ -10932,39 +11679,14 @@
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@@ -10984,9 +11706,84 @@
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@@ -11006,11 +11803,11 @@
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@@ -11031,11 +11828,11 @@
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@@ -11851,9 +12598,9 @@
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@@ -11900,18 +12647,18 @@
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@@ -11948,9 +12720,9 @@
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@@ -11997,18 +12769,18 @@
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@@ -12649,9 +13546,9 @@
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@@ -12700,7 +13597,7 @@
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@@ -19428,11 +25527,11 @@
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@@ -19455,9 +25554,9 @@
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@@ -19480,9 +25579,9 @@
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@@ -19505,9 +25604,9 @@
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@@ -19530,12 +25629,62 @@
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@@ -19553,86 +25702,11 @@
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@@ -19653,11 +25727,36 @@
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+          "hide_name": 0,
+          "type": "SB_LUT4",
+          "parameters": {
+            "LUT_INIT": "0000000100010111"
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         "spi_if_ins.o_data_in_SB_DFFE_Q": {
@@ -19676,10 +25775,10 @@
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@@ -19698,10 +25797,10 @@
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@@ -19720,10 +25819,10 @@
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@@ -19742,10 +25841,10 @@
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@@ -19764,10 +25863,10 @@
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@@ -19786,10 +25885,10 @@
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@@ -19808,10 +25907,10 @@
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@@ -19830,10 +25929,35 @@
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+          "hide_name": 0,
+          "type": "SB_LUT4",
+          "parameters": {
+            "LUT_INIT": "0100000000000000"
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+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
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         "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q": {
@@ -19853,11 +25977,11 @@
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@@ -19880,16 +26004,16 @@
           "connections": {
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-            "I2": [ 490 ],
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+            "I2": [ 869 ],
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           "hide_name": 0,
           "type": "SB_LUT4",
           "parameters": {
-            "LUT_INIT": "0000001111110000"
+            "LUT_INIT": "1100111100000000"
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@@ -19904,10 +26028,35 @@
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+          "hide_name": 0,
+          "type": "SB_LUT4",
+          "parameters": {
+            "LUT_INIT": "0000101111111111"
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@@ -19929,17 +26078,17 @@
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           "hide_name": 0,
           "type": "SB_LUT4",
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-            "LUT_INIT": "0100000000000000"
+            "LUT_INIT": "0001000000000000"
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@@ -19953,18 +26102,18 @@
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+            "I0": [ 104 ],
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         },
-        "spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O_SB_LUT4_O": {
+        "spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O_SB_LUT4_I2": {
           "hide_name": 0,
           "type": "SB_LUT4",
           "parameters": {
-            "LUT_INIT": "0000001100000000"
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@@ -19979,21 +26128,21 @@
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-        "spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O_SB_LUT4_O_1": {
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           "hide_name": 0,
           "type": "SB_LUT4",
           "parameters": {
-            "LUT_INIT": "1111111011101111"
+            "LUT_INIT": "1100111111111111"
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-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
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@@ -20003,11 +26152,36 @@
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+          "hide_name": 0,
+          "type": "SB_LUT4",
+          "parameters": {
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         "spi_if_ins.o_ioc_SB_DFFE_Q": {
@@ -20026,10 +26200,10 @@
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@@ -20048,10 +26222,10 @@
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@@ -20070,10 +26244,10 @@
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@@ -20092,10 +26266,10 @@
             "Q": "output"
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@@ -20114,10 +26288,10 @@
             "Q": "output"
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@@ -20137,11 +26311,11 @@
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@@ -20163,10 +26337,35 @@
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+            "I1": [ 869 ],
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+            "I3": [ 862 ],
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+          }
+        },
+        "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O_SB_LUT4_O": {
+          "hide_name": 0,
+          "type": "SB_LUT4",
+          "parameters": {
+            "LUT_INIT": "1111110011111111"
+          },
+          "attributes": {
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+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
+          },
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+            "I0": "input",
+            "I1": "input",
+            "I2": "input",
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         "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_O": {
@@ -20189,9 +26388,9 @@
           "connections": {
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         "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E_SB_LUT4_O": {
@@ -20212,14 +26411,14 @@
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         },
-        "spi_if_ins.o_load_cmd_SB_LUT4_I3": {
+        "spi_if_ins.o_load_cmd_SB_LUT4_I2": {
           "hide_name": 0,
           "type": "SB_LUT4",
           "parameters": {
@@ -20238,13 +26437,13 @@
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+            "O": [ 130 ]
           }
         },
-        "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2": {
+        "spi_if_ins.o_load_cmd_SB_LUT4_I2_O_SB_LUT4_I2": {
           "hide_name": 0,
           "type": "SB_LUT4",
           "parameters": {
@@ -20263,13 +26462,13 @@
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-            "O": [ 60 ]
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+            "O": [ 113 ]
           }
         },
-        "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3": {
+        "spi_if_ins.o_load_cmd_SB_LUT4_I2_O_SB_LUT4_I3": {
           "hide_name": 0,
           "type": "SB_LUT4",
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@@ -20289,12 +26488,37 @@
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-            "I2": [ 55 ],
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         },
-        "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3": {
+        "spi_if_ins.o_load_cmd_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_I2": {
+          "hide_name": 0,
+          "type": "SB_LUT4",
+          "parameters": {
+            "LUT_INIT": "1111000000000000"
+          },
+          "attributes": {
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+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+          },
+          "port_directions": {
+            "I0": "input",
+            "I1": "input",
+            "I2": "input",
+            "I3": "input",
+            "O": "output"
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+            "I3": [ 210 ],
+            "O": [ 197 ]
+          }
+        },
+        "spi_if_ins.o_load_cmd_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_I3": {
           "hide_name": 0,
           "type": "SB_LUT4",
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@@ -20314,16 +26538,16 @@
           "connections": {
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-            "I2": [ 89 ],
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+            "I2": [ 129 ],
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+            "O": [ 189 ]
           }
         },
-        "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1": {
+        "spi_if_ins.o_load_cmd_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O": {
           "hide_name": 0,
           "type": "SB_LUT4",
           "parameters": {
-            "LUT_INIT": "1111000000000000"
+            "LUT_INIT": "0000111100000000"
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           "attributes": {
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@@ -20339,34 +26563,9 @@
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-        "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2": {
-          "hide_name": 0,
-          "type": "SB_LUT4",
-          "parameters": {
-            "LUT_INIT": "1111000000000000"
-          },
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-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
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-            "I1": [ "0" ],
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-            "O": [ 152 ]
+            "I2": [ 48 ],
+            "I3": [ 133 ],
+            "O": [ 172 ]
           }
         },
         "spi_if_ins.r_tx_byte_SB_DFFE_Q": {
@@ -20385,10 +26584,10 @@
             "Q": "output"
           },
           "connections": {
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+            "C": [ 111 ],
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         "spi_if_ins.r_tx_byte_SB_DFFE_Q_1": {
@@ -20407,10 +26606,10 @@
             "Q": "output"
           },
           "connections": {
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-            "Q": [ 501 ]
+            "C": [ 111 ],
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         "spi_if_ins.r_tx_byte_SB_DFFE_Q_2": {
@@ -20429,10 +26628,10 @@
             "Q": "output"
           },
           "connections": {
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-            "Q": [ 502 ]
+            "C": [ 111 ],
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         "spi_if_ins.r_tx_byte_SB_DFFE_Q_3": {
@@ -20451,10 +26650,10 @@
             "Q": "output"
           },
           "connections": {
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+            "C": [ 111 ],
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         "spi_if_ins.r_tx_byte_SB_DFFE_Q_4": {
@@ -20473,10 +26672,10 @@
             "Q": "output"
           },
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+            "C": [ 111 ],
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         "spi_if_ins.r_tx_byte_SB_DFFE_Q_5": {
@@ -20495,10 +26694,10 @@
             "Q": "output"
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         "spi_if_ins.r_tx_byte_SB_DFFE_Q_6": {
@@ -20517,10 +26716,10 @@
             "Q": "output"
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+            "C": [ 111 ],
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         "spi_if_ins.r_tx_byte_SB_DFFE_Q_7": {
@@ -20539,10 +26738,10 @@
             "Q": "output"
           },
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+            "C": [ 111 ],
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+            "Q": [ 883 ]
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         "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q": {
@@ -20562,11 +26761,11 @@
             "R": "input"
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           "connections": {
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         "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3": {
@@ -20589,9 +26788,9 @@
           "connections": {
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+            "I2": [ 862 ],
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+            "O": [ 875 ]
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         "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_O": {
@@ -20613,21 +26812,21 @@
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+            "I1": [ 861 ],
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+            "I3": [ 864 ],
+            "O": [ 884 ]
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         "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E_SB_LUT4_O": {
           "hide_name": 0,
           "type": "SB_LUT4",
           "parameters": {
-            "LUT_INIT": "0011001100110101"
+            "LUT_INIT": "1111111100110000"
           },
           "attributes": {
             "module_not_derived": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52"
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
           },
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             "I0": "input",
@@ -20637,11 +26836,11 @@
             "O": "output"
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-            "I1": [ 493 ],
-            "I2": [ 491 ],
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+            "I0": [ "0" ],
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+            "I3": [ 122 ],
+            "O": [ 885 ]
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         "spi_if_ins.r_tx_data_valid_SB_LUT4_I3": {
@@ -20665,33 +26864,8 @@
             "I0": [ "0" ],
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             "I2": [ 44 ],
-            "I3": [ 510 ],
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-        "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O_SB_LUT4_I3": {
-          "hide_name": 0,
-          "type": "SB_LUT4",
-          "parameters": {
-            "LUT_INIT": "0011000011111111"
-          },
-          "attributes": {
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-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
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-            "I0": [ "0" ],
-            "I1": [ 512 ],
-            "I2": [ 513 ],
-            "I3": [ 511 ],
-            "O": [ 514 ]
+            "I3": [ 886 ],
+            "O": [ 887 ]
           }
         },
         "spi_if_ins.spi.SCKr_SB_DFF_Q": {
@@ -20709,9 +26883,9 @@
             "Q": "output"
           },
           "connections": {
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-            "D": [ 515 ],
-            "Q": [ 516 ]
+            "C": [ 111 ],
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         "spi_if_ins.spi.SCKr_SB_DFF_Q_1": {
@@ -20729,9 +26903,9 @@
             "Q": "output"
           },
           "connections": {
-            "C": [ 58 ],
-            "D": [ 517 ],
-            "Q": [ 515 ]
+            "C": [ 111 ],
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@@ -20749,9 +26923,9 @@
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@@ -20772,11 +26946,36 @@
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@@ -20795,10 +26994,10 @@
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@@ -20817,10 +27016,10 @@
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@@ -20839,10 +27038,10 @@
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@@ -20861,10 +27060,10 @@
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@@ -20883,10 +27082,10 @@
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@@ -20905,10 +27104,10 @@
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@@ -20927,10 +27126,10 @@
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@@ -20949,10 +27148,10 @@
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@@ -20970,34 +27169,9 @@
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@@ -21016,10 +27190,10 @@
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@@ -21041,17 +27215,17 @@
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@@ -21065,14 +27239,39 @@
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@@ -21090,14 +27289,14 @@
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@@ -21115,18 +27314,18 @@
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-        "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2": {
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@@ -21140,86 +27339,11 @@
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@@ -21237,9 +27361,9 @@
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@@ -21257,9 +27381,9 @@
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@@ -21282,9 +27406,9 @@
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         "spi_if_ins.spi.r_rx_bit_count_SB_DFFR_Q": {
@@ -21304,8 +27428,8 @@
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@@ -21326,8 +27450,8 @@
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@@ -21348,8 +27472,8 @@
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@@ -21374,8 +27498,8 @@
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@@ -21398,9 +27522,9 @@
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         "spi_if_ins.spi.r_rx_bit_count_SB_DFFR_Q_D_SB_LUT4_O_1": {
@@ -21423,9 +27547,9 @@
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         "spi_if_ins.spi.r_rx_bit_count_SB_DFFR_Q_D_SB_LUT4_O_I3_SB_CARRY_CO": {
@@ -21443,10 +27567,10 @@
             "I1": "input"
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@@ -21466,9 +27590,9 @@
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@@ -21488,9 +27612,9 @@
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@@ -21510,9 +27634,9 @@
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@@ -21532,9 +27656,9 @@
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@@ -21554,9 +27678,9 @@
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@@ -21576,9 +27700,9 @@
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@@ -21598,9 +27722,9 @@
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@@ -21621,8 +27745,8 @@
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@@ -21643,9 +27767,9 @@
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@@ -21670,8 +27794,8 @@
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@@ -21693,10 +27817,10 @@
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@@ -21718,10 +27842,10 @@
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@@ -21741,9 +27865,9 @@
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@@ -21763,9 +27887,9 @@
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@@ -21785,9 +27909,9 @@
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@@ -21807,9 +27931,9 @@
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@@ -21829,9 +27953,9 @@
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@@ -21851,9 +27975,9 @@
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@@ -21895,11 +28019,11 @@
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@@ -21921,10 +28045,10 @@
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@@ -21946,10 +28070,10 @@
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@@ -21973,8 +28097,8 @@
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@@ -21992,9 +28116,9 @@
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@@ -22019,8 +28143,8 @@
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@@ -22040,11 +28164,11 @@
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@@ -22064,11 +28188,11 @@
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@@ -22088,11 +28212,11 @@
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@@ -22112,11 +28236,11 @@
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@@ -22136,11 +28260,11 @@
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@@ -22160,11 +28284,11 @@
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@@ -22184,11 +28308,11 @@
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@@ -22208,11 +28332,11 @@
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@@ -22232,11 +28356,11 @@
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@@ -22256,11 +28380,36 @@
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@@ -22280,11 +28429,11 @@
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@@ -22304,11 +28453,36 @@
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+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
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@@ -22332,58 +28506,8 @@
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         "spi_if_ins.state_if_SB_DFFE_Q": {
@@ -22402,10 +28526,10 @@
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@@ -22426,11 +28550,11 @@
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@@ -22451,11 +28575,11 @@
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         "sys_ctrl_ins.i_cs_SB_DFFE_Q": {
@@ -22474,10 +28598,10 @@
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@@ -22496,96 +28620,21 @@
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@@ -22596,10 +28645,10 @@
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@@ -22620,11 +28669,11 @@
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         "sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q": {
@@ -22644,11 +28693,11 @@
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@@ -22672,8 +28721,8 @@
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         "sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S_SB_LUT4_O": {
@@ -22694,11 +28743,11 @@
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         "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q": {
@@ -22718,11 +28767,11 @@
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+          "port_directions": {
+            "I0": "input",
+            "I1": "input",
+            "I2": "input",
+            "I3": "input",
+            "O": "output"
+          },
+          "connections": {
+            "I0": [ "0" ],
+            "I1": [ "0" ],
+            "I2": [ 434 ],
+            "I3": [ 425 ],
+            "O": [ 420 ]
+          }
+        },
+        "w_lvds_rx_24_d1_SB_LUT4_I3_O_SB_LUT4_O_8": {
+          "hide_name": 0,
+          "type": "SB_LUT4",
+          "parameters": {
+            "LUT_INIT": "0000111100000000"
+          },
+          "attributes": {
+            "module_not_derived": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
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+          "port_directions": {
+            "I0": "input",
+            "I1": "input",
+            "I2": "input",
+            "I3": "input",
+            "O": "output"
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+          "connections": {
+            "I0": [ "0" ],
+            "I1": [ "0" ],
+            "I2": [ 434 ],
+            "I3": [ 367 ],
+            "O": [ 422 ]
+          }
+        },
+        "w_lvds_rx_24_d1_SB_LUT4_I3_O_SB_LUT4_O_9": {
+          "hide_name": 0,
+          "type": "SB_LUT4",
+          "parameters": {
+            "LUT_INIT": "0000111100000000"
+          },
+          "attributes": {
+            "module_not_derived": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+          },
+          "port_directions": {
+            "I0": "input",
+            "I1": "input",
+            "I2": "input",
+            "I3": "input",
+            "O": "output"
+          },
+          "connections": {
+            "I0": [ "0" ],
+            "I1": [ "0" ],
+            "I2": [ 434 ],
+            "I3": [ 369 ],
+            "O": [ 424 ]
+          }
+        },
+        "w_smi_read_req_SB_LUT4_O": {
+          "hide_name": 0,
+          "type": "SB_LUT4",
+          "parameters": {
+            "LUT_INIT": "0000111111111111"
+          },
+          "attributes": {
+            "module_not_derived": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52"
+          },
+          "port_directions": {
+            "I0": "input",
+            "I1": "input",
+            "I2": "input",
+            "I3": "input",
+            "O": "output"
+          },
+          "connections": {
+            "I0": [ "0" ],
+            "I1": [ "0" ],
+            "I2": [ 66 ],
+            "I3": [ 20 ],
+            "O": [ 219 ]
           }
         }
       },
@@ -23272,9 +31070,17 @@
             "src": "top.v:40.13-40.21"
           }
         },
+        "i_button_SB_LUT4_I3_I2": {
+          "hide_name": 0,
+          "bits": [ 127, 116, 46, 26 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
         "i_button_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 49, 131 ],
+          "bits": [ 182, 129, 47, 183 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -23336,6 +31142,162 @@
             "src": "top.v:46.13-46.21"
           }
         },
+        "i_smi_a1_SB_LUT4_I1_O": {
+          "hide_name": 0,
+          "bits": [ 52, 53, 54, 51 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O": {
+          "hide_name": 0,
+          "bits": [ 58, 55, 104 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1": {
+          "hide_name": 0,
+          "bits": [ "1", "1", "1", "1", 59, 56 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:296.13-327.5|smi_ctrl.v:151.29-151.43|/usr/local/bin/../share/yosys/ice40/arith_map.v:37.23-37.25"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_CARRY_CO_CI": {
+          "hide_name": 0,
+          "bits": [ "1", "1", "1", 63, 59, 60 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:296.13-327.5|smi_ctrl.v:159.25-159.39|/usr/local/bin/../share/yosys/ice40/arith_map.v:49.21-49.23"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I1_O_SB_LUT4_O_I1": {
+          "hide_name": 0,
+          "bits": [ 65, 53, 57 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I2_O": {
+          "hide_name": 0,
+          "bits": [ 71, 72, 67 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2": {
+          "hide_name": 0,
+          "bits": [ 63, 75, 72, 970 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:296.13-327.5|smi_ctrl.v:151.59-151.73|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27",
+            "unused_bits": "3"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_I2_SB_LUT4_O_I3": {
+          "hide_name": 0,
+          "bits": [ "1", 62, 74, 971 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:296.13-327.5|smi_ctrl.v:151.59-151.73|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22",
+            "unused_bits": "3"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_1_O": {
+          "hide_name": 0,
+          "bits": [ 72, 81, 78, 73 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2": {
+          "hide_name": 0,
+          "bits": [ 52, 53, 82, 67 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_2_I2_SB_LUT4_O_I1": {
+          "hide_name": 0,
+          "bits": [ 84, 53, 85 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2": {
+          "hide_name": 0,
+          "bits": [ 102, 90, 69, 972 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:296.13-327.5|smi_ctrl.v:125.59-125.73|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27",
+            "unused_bits": "3"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3": {
+          "hide_name": 0,
+          "bits": [ "1", 88, 89, 973 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:296.13-327.5|smi_ctrl.v:125.59-125.73|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22",
+            "unused_bits": "3"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 69, 94, 70, 95 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I3": {
+          "hide_name": 0,
+          "bits": [ 91, 92, 88, 93 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I3_I0": {
+          "hide_name": 0,
+          "bits": [ "1", "1", "1", 102, 100, 85 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:296.13-327.5|smi_ctrl.v:133.25-133.39|/usr/local/bin/../share/yosys/ice40/arith_map.v:37.23-37.25"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I3_I0_SB_CARRY_CO_CI": {
+          "hide_name": 0,
+          "bits": [ "1", "1", "1", "1", 102, 100 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:296.13-327.5|smi_ctrl.v:133.25-133.39|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I3_I0_SB_CARRY_CO_I1": {
+          "hide_name": 0,
+          "bits": [ "1", "1", "1", 102, 103, 101 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:296.13-327.5|smi_ctrl.v:133.25-133.39|/usr/local/bin/../share/yosys/ice40/arith_map.v:49.21-49.23"
+          }
+        },
+        "i_smi_a1_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 98, 108, 105, 99 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
         "i_smi_a2": {
           "hide_name": 0,
           "bits": [ 29 ],
@@ -23343,14 +31305,36 @@
             "src": "top.v:47.13-47.21"
           }
         },
-        "i_smi_a2_SB_LUT4_I1_O": {
+        "i_smi_a2_SB_LUT4_I2_I1": {
           "hide_name": 0,
-          "bits": [ 50, 434, 51, 435 ],
+          "bits": [ "1", "1", "1", 63, 107, 57 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:296.13-327.5|smi_ctrl.v:159.25-159.39|/usr/local/bin/../share/yosys/ice40/arith_map.v:37.23-37.25"
+          }
+        },
+        "i_smi_a2_SB_LUT4_I2_I1_SB_CARRY_CO_CI": {
+          "hide_name": 0,
+          "bits": [ "1", "1", "1", "1", 63, 107 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:296.13-327.5|smi_ctrl.v:159.25-159.39|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
+          }
+        },
+        "i_smi_a2_SB_LUT4_I2_O": {
+          "hide_name": 0,
+          "bits": [ 85, 98, 29, 28 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
+        "i_smi_a2_SB_LUT4_I2_O_SB_LUT4_I0_O": {
+          "hide_name": 0,
+          "bits": [ 109 ],
+          "attributes": {
+          }
+        },
         "i_smi_a3": {
           "hide_name": 0,
           "bits": [ 30 ],
@@ -23365,18 +31349,6 @@
             "src": "top.v:50.13-50.25"
           }
         },
-        "i_smi_soe_se_SB_LUT4_I1_1_O": {
-          "hide_name": 0,
-          "bits": [ 56 ],
-          "attributes": {
-          }
-        },
-        "i_smi_soe_se_SB_LUT4_I1_O": {
-          "hide_name": 0,
-          "bits": [ 54 ],
-          "attributes": {
-          }
-        },
         "i_smi_swe_srw": {
           "hide_name": 0,
           "bits": [ 31 ],
@@ -23391,36 +31363,24 @@
             "src": "top.v:59.13-59.17"
           }
         },
-        "i_ss_SB_LUT4_I3_O": {
-          "hide_name": 0,
-          "bits": [ 57 ],
-          "attributes": {
-          }
-        },
         "int_miso": {
           "hide_name": 0,
-          "bits": [ 315 ],
+          "bits": [ 477 ],
           "attributes": {
             "src": "top.v:110.9-110.17"
           }
         },
         "io_ctrl_ins.debug_mode": {
           "hide_name": 0,
-          "bits": [ 63, 61 ],
+          "bits": [ 116, 114 ],
           "attributes": {
             "hdlname": "io_ctrl_ins debug_mode",
             "src": "top.v:128.12-156.5|io_ctrl.v:67.17-67.27"
           }
         },
-        "io_ctrl_ins.debug_mode_SB_LUT4_I0_O": {
-          "hide_name": 0,
-          "bits": [ 66 ],
-          "attributes": {
-          }
-        },
         "io_ctrl_ins.debug_mode_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 69, 64, 155, 67 ],
+          "bits": [ 118, 117, 138, 120 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -23444,7 +31404,7 @@
         },
         "io_ctrl_ins.i_cs": {
           "hide_name": 0,
-          "bits": [ 72 ],
+          "bits": [ 123 ],
           "attributes": {
             "hdlname": "io_ctrl_ins i_cs",
             "src": "top.v:128.12-156.5|io_ctrl.v:9.29-9.33"
@@ -23452,7 +31412,7 @@
         },
         "io_ctrl_ins.i_data_in": {
           "hide_name": 0,
-          "bits": [ 62, 59, 146, 144, 142, 140, 139, 136 ],
+          "bits": [ 115, 112, 196, 195, 194, 192, 190, 188 ],
           "attributes": {
             "hdlname": "io_ctrl_ins i_data_in",
             "src": "top.v:128.12-156.5|io_ctrl.v:7.29-7.38"
@@ -23460,7 +31420,7 @@
         },
         "io_ctrl_ins.i_fetch_cmd": {
           "hide_name": 0,
-          "bits": [ 488 ],
+          "bits": [ 867 ],
           "attributes": {
             "hdlname": "io_ctrl_ins i_fetch_cmd",
             "src": "top.v:128.12-156.5|io_ctrl.v:10.29-10.40"
@@ -23468,7 +31428,7 @@
         },
         "io_ctrl_ins.i_ioc": {
           "hide_name": 0,
-          "bits": [ 132, 160, 163, 162, 161 ],
+          "bits": [ 48, 49, 214, 213, 212 ],
           "attributes": {
             "hdlname": "io_ctrl_ins i_ioc",
             "src": "top.v:128.12-156.5|io_ctrl.v:6.29-6.34"
@@ -23476,7 +31436,7 @@
         },
         "io_ctrl_ins.i_load_cmd": {
           "hide_name": 0,
-          "bits": [ 495 ],
+          "bits": [ 874 ],
           "attributes": {
             "hdlname": "io_ctrl_ins i_load_cmd",
             "src": "top.v:128.12-156.5|io_ctrl.v:11.29-11.39"
@@ -23484,7 +31444,7 @@
         },
         "io_ctrl_ins.i_reset": {
           "hide_name": 0,
-          "bits": [ 55 ],
+          "bits": [ 104 ],
           "attributes": {
             "hdlname": "io_ctrl_ins i_reset",
             "src": "top.v:128.12-156.5|io_ctrl.v:3.29-3.36"
@@ -23492,7 +31452,7 @@
         },
         "io_ctrl_ins.i_sys_clk": {
           "hide_name": 0,
-          "bits": [ 58 ],
+          "bits": [ 111 ],
           "attributes": {
             "hdlname": "io_ctrl_ins i_sys_clk",
             "src": "top.v:128.12-156.5|io_ctrl.v:4.29-4.38"
@@ -23500,7 +31460,7 @@
         },
         "io_ctrl_ins.i_sys_clk_SB_DFF_Q_D": {
           "hide_name": 0,
-          "bits": [ 74, "x" ],
+          "bits": [ 125, "x" ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:169.20-169.33|/usr/local/bin/../share/yosys/techmap.v:270.23-270.24"
@@ -23514,15 +31474,17 @@
             "src": "top.v:128.12-156.5|io_ctrl.v:71.17-71.27"
           }
         },
-        "io_ctrl_ins.led0_state_SB_DFFESR_Q_E": {
+        "io_ctrl_ins.led0_state_SB_LUT4_I3_I0": {
           "hide_name": 0,
-          "bits": [ 75 ],
+          "bits": [ 147, 127 ],
           "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
         "io_ctrl_ins.led0_state_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 135, 89, 82, 79 ],
+          "bits": [ 187, 129, 145, 128 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -23536,9 +31498,15 @@
             "src": "top.v:128.12-156.5|io_ctrl.v:72.17-72.27"
           }
         },
-        "io_ctrl_ins.led1_state_SB_LUT4_I0_I2": {
+        "io_ctrl_ins.led1_state_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 27, 48, 83, 84 ],
+          "bits": [ 126 ],
+          "attributes": {
+          }
+        },
+        "io_ctrl_ins.led1_state_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 184, 129, 134, 131 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -23554,7 +31522,7 @@
         },
         "io_ctrl_ins.lna_rx_shutdown_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 87 ],
+          "bits": [ 135 ],
           "attributes": {
             "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8"
           }
@@ -23569,14 +31537,14 @@
         },
         "io_ctrl_ins.lna_tx_shutdown_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 91 ],
+          "bits": [ 137 ],
           "attributes": {
             "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8"
           }
         },
         "io_ctrl_ins.mixer_en_state": {
           "hide_name": 0,
-          "bits": [ 77 ],
+          "bits": [ 142 ],
           "attributes": {
             "hdlname": "io_ctrl_ins mixer_en_state",
             "src": "top.v:128.12-156.5|io_ctrl.v:76.17-76.31"
@@ -23584,14 +31552,14 @@
         },
         "io_ctrl_ins.mixer_en_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 95 ],
+          "bits": [ 141 ],
           "attributes": {
             "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8"
           }
         },
         "io_ctrl_ins.o_data_out": {
           "hide_name": 0,
-          "bits": [ 134, 98, 110, 101, 105, 120, 125, 130 ],
+          "bits": [ 186, 148, 162, 151, 156, 169, 176, 181 ],
           "attributes": {
             "hdlname": "io_ctrl_ins o_data_out",
             "src": "top.v:128.12-156.5|io_ctrl.v:8.29-8.39"
@@ -23599,7 +31567,7 @@
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 100 ],
+          "bits": [ 150 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
@@ -23607,7 +31575,7 @@
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_2_D": {
           "hide_name": 0,
-          "bits": [ 104 ],
+          "bits": [ 155 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
@@ -23615,7 +31583,7 @@
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D": {
           "hide_name": 0,
-          "bits": [ 108 ],
+          "bits": [ 160 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
@@ -23623,7 +31591,7 @@
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_D_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 112, 94 ],
+          "bits": [ 164, 129, 165, 140 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -23631,27 +31599,19 @@
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E": {
           "hide_name": 0,
-          "bits": [ 109 ],
+          "bits": [ 161 ],
           "attributes": {
           }
         },
-        "io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_E_SB_LUT4_O_I2": {
-          "hide_name": 0,
-          "bits": [ 114, 115 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_3_R": {
           "hide_name": 0,
-          "bits": [ 111 ],
+          "bits": [ 163 ],
           "attributes": {
           }
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_4_D": {
           "hide_name": 0,
-          "bits": [ 118 ],
+          "bits": [ 167 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
@@ -23659,7 +31619,7 @@
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_5_D": {
           "hide_name": 0,
-          "bits": [ 124 ],
+          "bits": [ 175 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
@@ -23667,7 +31627,7 @@
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_D": {
           "hide_name": 0,
-          "bits": [ 129 ],
+          "bits": [ 180 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
@@ -23675,33 +31635,35 @@
         },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_E": {
           "hide_name": 0,
-          "bits": [ 119 ],
+          "bits": [ 168 ],
           "attributes": {
           }
         },
+        "io_ctrl_ins.o_data_out_SB_DFFESR_Q_6_R": {
+          "hide_name": 0,
+          "bits": [ 48, 50, 170 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 85 ],
+          "bits": [ 146 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
           }
         },
-        "io_ctrl_ins.o_data_out_SB_DFFESR_Q_E": {
-          "hide_name": 0,
-          "bits": [ 97 ],
-          "attributes": {
-          }
-        },
         "io_ctrl_ins.o_data_out_SB_DFFESR_Q_R": {
           "hide_name": 0,
-          "bits": [ 99 ],
+          "bits": [ 149 ],
           "attributes": {
           }
         },
         "io_ctrl_ins.o_data_out_SB_DFFESS_Q_D": {
           "hide_name": 0,
-          "bits": [ 133 ],
+          "bits": [ 185 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:128.12-156.5|io_ctrl.v:122.21-161.28|io_ctrl.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22"
@@ -23741,7 +31703,7 @@
         },
         "io_ctrl_ins.o_pmod": {
           "hide_name": 0,
-          "bits": [ 80, 86, 113, 151, 150, 149, 148, 46 ],
+          "bits": [ 144, 132, 139, 200, 199, 171, 177, 198 ],
           "attributes": {
             "hdlname": "io_ctrl_ins o_pmod",
             "src": "top.v:128.12-156.5|io_ctrl.v:18.29-18.35"
@@ -23805,23 +31767,35 @@
         },
         "io_ctrl_ins.pmod_dir_state": {
           "hide_name": 0,
-          "bits": [ 135, 90, 93, 145, 143, 141, 126, 138 ],
+          "bits": [ 187, 184, 164, 152, 157, 193, 191, 182 ],
           "attributes": {
             "hdlname": "io_ctrl_ins pmod_dir_state",
             "src": "top.v:128.12-156.5|io_ctrl.v:73.17-73.31"
           }
         },
+        "io_ctrl_ins.pmod_dir_state_SB_DFFE_Q_E": {
+          "hide_name": 0,
+          "bits": [ 189 ],
+          "attributes": {
+          }
+        },
         "io_ctrl_ins.pmod_state": {
           "hide_name": 0,
-          "bits": [ 80, 86, 113, 151, 150, 149, 148, 46 ],
+          "bits": [ 144, 132, 139, 200, 199, 171, 177, 198 ],
           "attributes": {
             "hdlname": "io_ctrl_ins pmod_state",
             "src": "top.v:128.12-156.5|io_ctrl.v:74.17-74.27"
           }
         },
+        "io_ctrl_ins.pmod_state_SB_DFFE_Q_E": {
+          "hide_name": 0,
+          "bits": [ 197 ],
+          "attributes": {
+          }
+        },
         "io_ctrl_ins.rf_mode": {
           "hide_name": 0,
-          "bits": [ 68, 64, 65 ],
+          "bits": [ 166, 118, 117 ],
           "attributes": {
             "hdlname": "io_ctrl_ins rf_mode",
             "src": "top.v:128.12-156.5|io_ctrl.v:68.17-68.24"
@@ -23829,7 +31803,7 @@
         },
         "io_ctrl_ins.rf_pin_state": {
           "hide_name": 0,
-          "bits": [ 96, 88, 92, 157, 156, 155, 154, 153 ],
+          "bits": [ 143, 136, 138, 206, 205, 204, 203, 202 ],
           "attributes": {
             "hdlname": "io_ctrl_ins rf_pin_state",
             "src": "top.v:128.12-156.5|io_ctrl.v:75.17-75.29"
@@ -23845,38 +31819,28 @@
         },
         "io_ctrl_ins.rx_h_b_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 158 ],
+          "bits": [ 207 ],
           "attributes": {
             "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8"
           }
         },
-        "io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3": {
+        "io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_I2": {
           "hide_name": 0,
-          "bits": [ 148, 4, 132, 117 ],
+          "bits": [ 129, 193, 209, 5 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I2_O": {
+        "io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_I2_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 7, 78, 89, 145 ],
+          "bits": [ 201 ],
           "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_I3_SB_LUT4_I3_O": {
+        "io_ctrl_ins.rx_h_b_state_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 47, 151, 81, 64 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "io_ctrl_ins.rx_h_b_state_SB_LUT4_I1_O": {
-          "hide_name": 0,
-          "bits": [ 126, 89, 127, 128 ],
+          "bits": [ 177, 172, 178, 179 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -23892,14 +31856,28 @@
         },
         "io_ctrl_ins.rx_h_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 165 ],
+          "bits": [ 211 ],
           "attributes": {
             "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8"
           }
         },
         "io_ctrl_ins.rx_h_state_SB_DFFE_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 153, 67, 159 ],
+          "bits": [ 202, 120, 208 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "io_ctrl_ins.rx_h_state_SB_DFFE_Q_E": {
+          "hide_name": 0,
+          "bits": [ 119 ],
+          "attributes": {
+          }
+        },
+        "io_ctrl_ins.rx_h_state_SB_LUT4_I1_I3": {
+          "hide_name": 0,
+          "bits": [ 48, 133 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -23915,14 +31893,14 @@
         },
         "io_ctrl_ins.tr_vc_1_b_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 166 ],
+          "bits": [ 215 ],
           "attributes": {
             "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8"
           }
         },
-        "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I0_O": {
+        "io_ctrl_ins.tr_vc_1_b_state_SB_LUT4_I1_O": {
           "hide_name": 0,
-          "bits": [ 14, 48, 106, 107 ],
+          "bits": [ 157, 129, 158, 159 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -23938,14 +31916,22 @@
         },
         "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 167 ],
+          "bits": [ 217 ],
           "attributes": {
             "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8"
           }
         },
-        "io_ctrl_ins.tr_vc_1_state_SB_LUT4_I0_O": {
+        "io_ctrl_ins.tr_vc_1_state_SB_DFFE_Q_D_SB_LUT4_O_I0": {
           "hide_name": 0,
-          "bits": [ 122, 123 ],
+          "bits": [ 216, 118, 205, 120 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "io_ctrl_ins.tr_vc_1_state_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 171, 172, 173, 174 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -23961,14 +31947,14 @@
         },
         "io_ctrl_ins.tr_vc_2_state_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 168 ],
+          "bits": [ 218 ],
           "attributes": {
             "src": "top.v:128.12-156.5|io_ctrl.v:207.5-302.8"
           }
         },
-        "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I0_O": {
+        "io_ctrl_ins.tr_vc_2_state_SB_LUT4_I1_O": {
           "hide_name": 0,
-          "bits": [ 13, 48, 102, 103 ],
+          "bits": [ 152, 129, 153, 154 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -23983,14 +31969,29 @@
         },
         "io_pmod_SB_DFFSS_Q_D": {
           "hide_name": 0,
-          "bits": [ 175 ],
+          "bits": [ 226 ],
           "attributes": {
-            "src": "top.v:259.17-270.5|complex_fifo.v:83.14-83.65"
           }
         },
-        "io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I2": {
+        "io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0": {
           "hide_name": 0,
-          "bits": [ 176, 177, 178, 179 ],
+          "bits": [ 227, 228, 229, 230 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I1": {
+          "hide_name": 0,
+          "bits": [ 245, 246, 240, 247 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "io_pmod_SB_DFFSS_Q_D_SB_LUT4_O_I0_SB_LUT4_O_3_I3": {
+          "hide_name": 0,
+          "bits": [ 240, 241, 242 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -24005,21 +32006,21 @@
         },
         "lvds_clock": {
           "hide_name": 0,
-          "bits": [ 197 ],
+          "bits": [ 259 ],
           "attributes": {
             "src": "top.v:184.9-184.19"
           }
         },
         "lvds_clock_buf": {
           "hide_name": 0,
-          "bits": [ 169 ],
+          "bits": [ 220 ],
           "attributes": {
             "src": "top.v:185.9-185.23"
           }
         },
         "lvds_rx_09_inst.i_ddr_clk": {
           "hide_name": 0,
-          "bits": [ 169 ],
+          "bits": [ 220 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst i_ddr_clk",
             "src": "top.v:248.12-257.5|lvds_rx.v:4.29-4.38"
@@ -24027,7 +32028,7 @@
         },
         "lvds_rx_09_inst.i_ddr_data": {
           "hide_name": 0,
-          "bits": [ 194, 193 ],
+          "bits": [ 256, 255 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst i_ddr_data",
             "src": "top.v:248.12-257.5|lvds_rx.v:5.29-5.39"
@@ -24035,7 +32036,7 @@
         },
         "lvds_rx_09_inst.i_fifo_full": {
           "hide_name": 0,
-          "bits": [ 213 ],
+          "bits": [ 330 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst i_fifo_full",
             "src": "top.v:248.12-257.5|lvds_rx.v:7.29-7.40"
@@ -24043,7 +32044,7 @@
         },
         "lvds_rx_09_inst.i_reset": {
           "hide_name": 0,
-          "bits": [ 55 ],
+          "bits": [ 104 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst i_reset",
             "src": "top.v:248.12-257.5|lvds_rx.v:3.29-3.36"
@@ -24051,16 +32052,15 @@
         },
         "lvds_rx_09_inst.o_fifo_data": {
           "hide_name": 0,
-          "bits": [ 201, 199, 22, 23, 24, 25, "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ],
+          "bits": [ 301, 299, 22, 23, 24, 25, 297, 295, 293, 291, 289, 287, 283, 281, 279, 277, 275, 273, 271, 269, 267, 265, 315, 313, 311, 309, 307, 305, 303, 285, 263, 261 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst o_fifo_data",
-            "src": "top.v:248.12-257.5|lvds_rx.v:10.29-10.40",
-            "unused_bits": "4 5"
+            "src": "top.v:248.12-257.5|lvds_rx.v:10.29-10.40"
           }
         },
         "lvds_rx_09_inst.o_fifo_push": {
           "hide_name": 0,
-          "bits": [ 211 ],
+          "bits": [ 328 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst o_fifo_push",
             "src": "top.v:248.12-257.5|lvds_rx.v:9.29-9.40"
@@ -24068,7 +32068,7 @@
         },
         "lvds_rx_09_inst.o_fifo_write_clk": {
           "hide_name": 0,
-          "bits": [ 169 ],
+          "bits": [ 220 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst o_fifo_write_clk",
             "src": "top.v:248.12-257.5|lvds_rx.v:8.29-8.45"
@@ -24076,24 +32076,15 @@
         },
         "lvds_rx_09_inst.r_data": {
           "hide_name": 0,
-          "bits": [ 201, 199, 22, 23, 24, 25, "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ],
+          "bits": [ 301, 299, 22, 23, 24, 25, 297, 295, 293, 291, 289, 287, 283, 281, 279, 277, 275, 273, 271, 269, 267, 265, 315, 313, 311, 309, 307, 305, 303, 285, 263, 261 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst r_data",
-            "src": "top.v:248.12-257.5|lvds_rx.v:21.17-21.23",
-            "unused_bits": "4 5"
-          }
-        },
-        "lvds_rx_09_inst.r_data_SB_LUT4_I3_I2": {
-          "hide_name": 0,
-          "bits": [ 202, 216 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:248.12-257.5|lvds_rx.v:47.13-78.20|lvds_rx.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22"
+            "src": "top.v:248.12-257.5|lvds_rx.v:21.17-21.23"
           }
         },
         "lvds_rx_09_inst.r_phase_count": {
           "hide_name": 0,
-          "bits": [ 203, 205, 592 ],
+          "bits": [ 316, 318, 974 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst r_phase_count",
             "src": "top.v:248.12-257.5|lvds_rx.v:20.17-20.30",
@@ -24102,23 +32093,23 @@
         },
         "lvds_rx_09_inst.r_phase_count_SB_CARRY_CI_CO": {
           "hide_name": 0,
-          "bits": [ "1", 203, 204 ],
+          "bits": [ "1", 316, 317 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:248.12-257.5|lvds_rx.v:63.42-63.59|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
           }
         },
-        "lvds_rx_09_inst.r_phase_count_SB_LUT4_I1_O": {
+        "lvds_rx_09_inst.r_phase_count_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 208, 206, 217 ],
+          "bits": [ 320, 324 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:248.12-257.5|lvds_rx.v:63.42-63.59|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
         "lvds_rx_09_inst.r_push": {
           "hide_name": 0,
-          "bits": [ 211 ],
+          "bits": [ 328 ],
           "attributes": {
             "hdlname": "lvds_rx_09_inst r_push",
             "src": "top.v:248.12-257.5|lvds_rx.v:22.17-22.23"
@@ -24126,114 +32117,50 @@
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@@ -24241,21 +32168,21 @@
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-        "lvds_rx_09_inst.r_state_if_SB_DFFNESR_Q_E_SB_LUT4_O_I2": {
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@@ -24263,7 +32190,7 @@
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@@ -24271,7 +32198,7 @@
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@@ -24279,15 +32206,23 @@
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             "src": "top.v:272.12-281.5|lvds_rx.v:3.29-3.36"
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@@ -24295,15 +32230,23 @@
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             "src": "top.v:272.12-281.5|lvds_rx.v:8.29-8.45"
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+        "lvds_rx_24_inst.r_data": {
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+            "src": "top.v:272.12-281.5|lvds_rx.v:21.17-21.23"
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@@ -24312,23 +32255,43 @@
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-        "lvds_rx_24_inst.r_phase_count_SB_LUT4_I1_O": {
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@@ -24336,133 +32299,105 @@
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+        "lvds_rx_24_inst.r_state_if_SB_DFFNESR_Q_E_SB_LUT4_O_I0_SB_LUT4_I3_O": {
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+        "lvds_rx_24_inst.r_state_if_SB_LUT4_I2_O": {
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@@ -24519,6 +32454,12 @@
             "src": "top.v:60.14-60.20"
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@@ -24598,7 +32539,7 @@
         },
         "r_counter": {
           "hide_name": 0,
-          "bits": [ 58, "x" ],
+          "bits": [ 111, "x" ],
           "attributes": {
             "src": "top.v:65.16-65.25"
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@@ -24612,29 +32553,44 @@
         },
         "r_tx_data": {
           "hide_name": 0,
-          "bits": [ 334, 318, 321, 323, 325, 327, 329, 332 ],
+          "bits": [ 498, 480, 483, 485, 487, 489, 491, 494 ],
           "attributes": {
             "src": "top.v:70.16-70.25"
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         "r_tx_data_SB_DFFESR_Q_5_D": {
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             "unused_bits": "8 10 13 15 16 17 18 19 24 25 26 27 29 31"
           }
         },
+        "r_tx_data_SB_DFFESR_Q_D": {
+          "hide_name": 0,
+          "bits": [ 990, 478, 482, 484, 486, 488, 490, 493 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:0.0-0.0|top.v:171.7-177.14|/usr/local/bin/../share/yosys/techmap.v:578.19-578.22",
+            "unused_bits": "0 "
+          }
+        },
         "r_tx_data_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 333, 611, 612, 613, 614, 615, 616, 617 ],
+          "bits": [ 497, 991, 992, 993, 994, 995, 996, 997 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:0.0-0.0|top.v:171.7-177.14|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22",
             "unused_bits": "1 2 3 4 5 6 7"
           }
         },
+        "r_tx_data_SB_DFFE_Q_E": {
+          "hide_name": 0,
+          "bits": [ 479 ],
+          "attributes": {
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+        },
         "rx_09_fifo.empty_o": {
           "hide_name": 0,
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@@ -24645,7 +32601,7 @@
         },
         "rx_09_fifo.full_o": {
           "hide_name": 0,
-          "bits": [ 213 ],
+          "bits": [ 330 ],
           "attributes": {
             "hdlname": "rx_09_fifo full_o",
             "src": "top.v:259.17-270.5|complex_fifo.v:16.17-16.23"
@@ -24653,13 +32609,45 @@
         },
         "rx_09_fifo.full_o_SB_DFFSR_Q_D": {
           "hide_name": 0,
-          "bits": [ 335 ],
+          "bits": [ 499 ],
           "attributes": {
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         },
+        "rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1": {
+          "hide_name": 0,
+          "bits": [ 500, 501, 502 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2": {
+          "hide_name": 0,
+          "bits": [ 503, 504, 505 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_09_fifo.full_o_SB_DFFSR_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1": {
+          "hide_name": 0,
+          "bits": [ 506, 507, 508, 503 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:259.17-270.5|complex_fifo.v:57.23-57.34|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
         "rx_09_fifo.full_o_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 245, 246, 247, 248 ],
+          "bits": [ 511, 514, 515, 513 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_09_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 517, 516, 518, 519 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -24667,7 +32655,7 @@
         },
         "rx_09_fifo.rd_addr": {
           "hide_name": 0,
-          "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ],
+          "bits": [ 526, 527, 528, 529, 530, 244, 241, 246 ],
           "attributes": {
             "hdlname": "rx_09_fifo rd_addr",
             "src": "top.v:259.17-270.5|complex_fifo.v:24.22-24.29"
@@ -24675,15 +32663,69 @@
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         "rx_09_fifo.rd_addr_gray": {
           "hide_name": 0,
-          "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ],
+          "bits": [ 583, 582, 580, 574, 573, 571, 569, 246 ],
           "attributes": {
             "hdlname": "rx_09_fifo rd_addr_gray",
             "src": "top.v:259.17-270.5|complex_fifo.v:25.22-25.34"
           }
         },
+        "rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_1_D": {
+          "hide_name": 0,
+          "bits": [ 568 ],
+          "attributes": {
+            "src": "top.v:259.17-270.5|complex_fifo.v:33.8-33.47"
+          }
+        },
+        "rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_4_D": {
+          "hide_name": 0,
+          "bits": [ 233, 234, 235, 236 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_5_D": {
+          "hide_name": 0,
+          "bits": [ 572, 577, 578, 579 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_6_D": {
+          "hide_name": 0,
+          "bits": [ 581 ],
+          "attributes": {
+            "src": "top.v:259.17-270.5|complex_fifo.v:33.8-33.47"
+          }
+        },
+        "rx_09_fifo.rd_addr_gray_SB_DFFESR_Q_7_D": {
+          "hide_name": 0,
+          "bits": [ 575, 576, 243, 570 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_09_fifo.rd_addr_gray_SB_LUT4_I2_I3": {
+          "hide_name": 0,
+          "bits": [ "0", 526, 589, 588, 587, 586, 585, 584 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:259.17-270.5|complex_fifo.v:66.14-66.28|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
+          }
+        },
+        "rx_09_fifo.rd_addr_gray_SB_LUT4_I2_O": {
+          "hide_name": 0,
+          "bits": [ 566, 565, 564, 563, 562, 561, 559, 567 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:259.17-270.5|complex_fifo.v:66.14-66.28|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
+          }
+        },
         "rx_09_fifo.rd_addr_gray_wr": {
           "hide_name": 0,
-          "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ],
+          "bits": [ 597, 596, 595, 594, 593, 592, 591, 590 ],
           "attributes": {
             "hdlname": "rx_09_fifo rd_addr_gray_wr",
             "src": "top.v:259.17-270.5|complex_fifo.v:26.22-26.37"
@@ -24691,7 +32733,7 @@
         },
         "rx_09_fifo.rd_addr_gray_wr_r": {
           "hide_name": 0,
-          "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ],
+          "bits": [ 510, 506, 511, 355, 353, 333, 348, 349 ],
           "attributes": {
             "hdlname": "rx_09_fifo rd_addr_gray_wr_r",
             "src": "top.v:259.17-270.5|complex_fifo.v:27.22-27.39"
@@ -24699,15 +32741,23 @@
         },
         "rx_09_fifo.rd_clk_i": {
           "hide_name": 0,
-          "bits": [ 58 ],
+          "bits": [ 111 ],
           "attributes": {
             "hdlname": "rx_09_fifo rd_clk_i",
             "src": "top.v:259.17-270.5|complex_fifo.v:12.29-12.37"
           }
         },
+        "rx_09_fifo.rd_data_o": {
+          "hide_name": 0,
+          "bits": [ 68, 546, 547, 548, 549, 550, 96, 551, 552, 553, 554, 555, 556, 557, 91, 558, 531, 532, 533, 534, 535, 536, 97, 537, 538, 539, 540, 541, 542, 543, 92, 544 ],
+          "attributes": {
+            "hdlname": "rx_09_fifo rd_data_o",
+            "src": "top.v:259.17-270.5|complex_fifo.v:14.33-14.42"
+          }
+        },
         "rx_09_fifo.rd_en_i": {
           "hide_name": 0,
-          "bits": [ "0" ],
+          "bits": [ 108 ],
           "attributes": {
             "hdlname": "rx_09_fifo rd_en_i",
             "src": "top.v:259.17-270.5|complex_fifo.v:13.29-13.36"
@@ -24715,7 +32765,7 @@
         },
         "rx_09_fifo.rd_rst_i": {
           "hide_name": 0,
-          "bits": [ 55 ],
+          "bits": [ 104 ],
           "attributes": {
             "hdlname": "rx_09_fifo rd_rst_i",
             "src": "top.v:259.17-270.5|complex_fifo.v:11.29-11.37"
@@ -24723,7 +32773,7 @@
         },
         "rx_09_fifo.wr_addr": {
           "hide_name": 0,
-          "bits": [ 244, 242, 243, 229, 241, 237, 234, 232 ],
+          "bits": [ 509, 503, 508, 345, 342, 340, 338, 545 ],
           "attributes": {
             "hdlname": "rx_09_fifo wr_addr",
             "src": "top.v:259.17-270.5|complex_fifo.v:20.22-20.29"
@@ -24731,46 +32781,70 @@
         },
         "rx_09_fifo.wr_addr_gray": {
           "hide_name": 0,
-          "bits": [ 351, 350, 349, 348, 347, 346, 345, 232 ],
+          "bits": [ 610, 609, 608, 606, 605, 604, 603, 545 ],
           "attributes": {
             "hdlname": "rx_09_fifo wr_addr_gray",
             "src": "top.v:259.17-270.5|complex_fifo.v:21.22-21.34"
           }
         },
-        "rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_1_D": {
+        "rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_3_D": {
           "hide_name": 0,
-          "bits": [ 344 ],
-          "attributes": {
-            "src": "top.v:259.17-270.5|complex_fifo.v:33.8-33.47"
-          }
-        },
-        "rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D": {
-          "hide_name": 0,
-          "bits": [ 250, 251, 252 ],
+          "bits": [ 353, 522, 523, 348 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3": {
+        "rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_4_D": {
           "hide_name": 0,
-          "bits": [ "0", 244, 357, 356, 355, 354, 353, 352 ],
+          "bits": [ 355, 524, 525, 333 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_5_D": {
+          "hide_name": 0,
+          "bits": [ 607 ],
+          "attributes": {
+            "src": "top.v:259.17-270.5|complex_fifo.v:33.8-33.47"
+          }
+        },
+        "rx_09_fifo.wr_addr_gray_SB_DFFESR_Q_7_D": {
+          "hide_name": 0,
+          "bits": [ 510, 520, 506, 521 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_I3": {
+          "hide_name": 0,
+          "bits": [ "0", 509, 617, 616, 615, 614, 613, 612 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:259.17-270.5|complex_fifo.v:42.14-42.28|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
           }
         },
-        "rx_09_fifo.wr_addr_gray_SB_LUT4_I2_O": {
+        "rx_09_fifo.wr_addr_gray_SB_LUT4_I2_1_O": {
           "hide_name": 0,
-          "bits": [ 343, 340, 338, 339, 342, 341, 337, 336 ],
+          "bits": [ 602, 601, 514, 515, 600, 599, 598, 512 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:259.17-270.5|complex_fifo.v:42.14-42.28|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
           }
         },
+        "rx_09_fifo.wr_addr_gray_SB_LUT4_I2_I3": {
+          "hide_name": 0,
+          "bits": [ "0", 503, 346, 343, 341, 339, 611 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:259.17-270.5|complex_fifo.v:57.23-57.34|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
+          }
+        },
         "rx_09_fifo.wr_addr_gray_rd": {
           "hide_name": 0,
-          "bits": [ 365, 364, 363, 362, 361, 360, 359, 358 ],
+          "bits": [ 625, 624, 623, 622, 621, 620, 619, 618 ],
           "attributes": {
             "hdlname": "rx_09_fifo wr_addr_gray_rd",
             "src": "top.v:259.17-270.5|complex_fifo.v:22.22-22.37"
@@ -24778,7 +32852,7 @@
         },
         "rx_09_fifo.wr_addr_gray_rd_r": {
           "hide_name": 0,
-          "bits": [ 176, 177, 180, 181, 182, 183, 184, 185 ],
+          "bits": [ 575, 626, 578, 233, 577, 243, 247, 245 ],
           "attributes": {
             "hdlname": "rx_09_fifo wr_addr_gray_rd_r",
             "src": "top.v:259.17-270.5|complex_fifo.v:23.22-23.39"
@@ -24786,7 +32860,7 @@
         },
         "rx_09_fifo.wr_clk_i": {
           "hide_name": 0,
-          "bits": [ 169 ],
+          "bits": [ 220 ],
           "attributes": {
             "hdlname": "rx_09_fifo wr_clk_i",
             "src": "top.v:259.17-270.5|complex_fifo.v:7.29-7.37"
@@ -24794,16 +32868,15 @@
         },
         "rx_09_fifo.wr_data_i": {
           "hide_name": 0,
-          "bits": [ 201, 199, 22, 23, 24, 25, "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ],
+          "bits": [ 301, 299, 22, 23, 24, 25, 297, 295, 293, 291, 289, 287, 283, 281, 279, 277, 275, 273, 271, 269, 267, 265, 315, 313, 311, 309, 307, 305, 303, 285, 263, 261 ],
           "attributes": {
             "hdlname": "rx_09_fifo wr_data_i",
-            "src": "top.v:259.17-270.5|complex_fifo.v:9.33-9.42",
-            "unused_bits": "4 5"
+            "src": "top.v:259.17-270.5|complex_fifo.v:9.33-9.42"
           }
         },
         "rx_09_fifo.wr_en_i": {
           "hide_name": 0,
-          "bits": [ 211 ],
+          "bits": [ 328 ],
           "attributes": {
             "hdlname": "rx_09_fifo wr_en_i",
             "src": "top.v:259.17-270.5|complex_fifo.v:8.29-8.36"
@@ -24811,7 +32884,7 @@
         },
         "rx_09_fifo.wr_rst_i": {
           "hide_name": 0,
-          "bits": [ 55 ],
+          "bits": [ 104 ],
           "attributes": {
             "hdlname": "rx_09_fifo wr_rst_i",
             "src": "top.v:259.17-270.5|complex_fifo.v:6.29-6.37"
@@ -24819,7 +32892,7 @@
         },
         "rx_24_fifo.empty_o": {
           "hide_name": 0,
-          "bits": [ 367 ],
+          "bits": [ 66 ],
           "attributes": {
             "hdlname": "rx_24_fifo empty_o",
             "src": "top.v:283.17-294.5|complex_fifo.v:17.17-17.24"
@@ -24827,22 +32900,13 @@
         },
         "rx_24_fifo.empty_o_SB_DFFSS_Q_D": {
           "hide_name": 0,
-          "bits": [ 366 ],
+          "bits": [ 627 ],
           "attributes": {
-            "src": "top.v:283.17-294.5|complex_fifo.v:83.14-83.65"
           }
         },
-        "rx_24_fifo.empty_o_SB_DFFSS_Q_D_SB_LUT4_O_I3": {
+        "rx_24_fifo.empty_o_SB_LUT4_I2_I3": {
           "hide_name": 0,
-          "bits": [ 368, 369, 370 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "rx_24_fifo.empty_o_SB_LUT4_I3_I2": {
-          "hide_name": 0,
-          "bits": [ 371, 372, 373, 367 ],
+          "bits": [ 106, 66, 632 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -24850,7 +32914,7 @@
         },
         "rx_24_fifo.full_o": {
           "hide_name": 0,
-          "bits": [ 269 ],
+          "bits": [ 444 ],
           "attributes": {
             "hdlname": "rx_24_fifo full_o",
             "src": "top.v:283.17-294.5|complex_fifo.v:16.17-16.23"
@@ -24858,13 +32922,29 @@
         },
         "rx_24_fifo.full_o_SB_DFFSR_Q_D": {
           "hide_name": 0,
-          "bits": [ 378 ],
+          "bits": [ 638 ],
           "attributes": {
           }
         },
         "rx_24_fifo.full_o_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 303, 304, 305, 306 ],
+          "bits": [ 447, 645, 646, 644 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 647, 648, 649, 650 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.full_o_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O_I3": {
+          "hide_name": 0,
+          "bits": [ 471, 645, 651, 652 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -24872,7 +32952,7 @@
         },
         "rx_24_fifo.rd_addr": {
           "hide_name": 0,
-          "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ],
+          "bits": [ 661, 662, 663, 664, 665, 666, 637, 635 ],
           "attributes": {
             "hdlname": "rx_24_fifo rd_addr",
             "src": "top.v:283.17-294.5|complex_fifo.v:24.22-24.29"
@@ -24880,15 +32960,125 @@
         },
         "rx_24_fifo.rd_addr_gray": {
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-          "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ],
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             "hdlname": "rx_24_fifo rd_addr_gray",
             "src": "top.v:283.17-294.5|complex_fifo.v:25.22-25.34"
           }
         },
+        "rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_1_D": {
+          "hide_name": 0,
+          "bits": [ 705, 634, 729 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_2_D": {
+          "hide_name": 0,
+          "bits": [ 707 ],
+          "attributes": {
+            "src": "top.v:283.17-294.5|complex_fifo.v:33.8-33.47"
+          }
+        },
+        "rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_4_D": {
+          "hide_name": 0,
+          "bits": [ 717, 711, 718, 709 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_5_D": {
+          "hide_name": 0,
+          "bits": [ 713 ],
+          "attributes": {
+            "src": "top.v:283.17-294.5|complex_fifo.v:33.8-33.47"
+          }
+        },
+        "rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_6_D": {
+          "hide_name": 0,
+          "bits": [ 728, 715, 719 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D": {
+          "hide_name": 0,
+          "bits": [ 720, 722 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O": {
+          "hide_name": 0,
+          "bits": [ 724, 698, 696, 723 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O": {
+          "hide_name": 0,
+          "bits": [ 628, 629, 630, 631 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0": {
+          "hide_name": 0,
+          "bits": [ 725, 726, 633, 727 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3": {
+          "hide_name": 0,
+          "bits": [ 731, 663, 664, 732 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_2_I0": {
+          "hide_name": 0,
+          "bits": [ 733, 662, 728, 663 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.rd_addr_gray_SB_DFFESR_Q_7_D_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_I0": {
+          "hide_name": 0,
+          "bits": [ 730, 666, 724, 637 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.rd_addr_gray_SB_LUT4_I2_I3": {
+          "hide_name": 0,
+          "bits": [ "0", 661, 739, 738, 737, 736, 735, 734 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:283.17-294.5|complex_fifo.v:66.14-66.28|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
+          }
+        },
+        "rx_24_fifo.rd_addr_gray_SB_LUT4_I2_O": {
+          "hide_name": 0,
+          "bits": [ 703, 702, 701, 700, 699, 698, 696, 704 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:283.17-294.5|complex_fifo.v:66.14-66.28|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
+          }
+        },
         "rx_24_fifo.rd_addr_gray_wr": {
           "hide_name": 0,
-          "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ],
+          "bits": [ 747, 746, 745, 744, 743, 742, 741, 740 ],
           "attributes": {
             "hdlname": "rx_24_fifo rd_addr_gray_wr",
             "src": "top.v:283.17-294.5|complex_fifo.v:26.22-26.37"
@@ -24896,7 +33086,7 @@
         },
         "rx_24_fifo.rd_addr_gray_wr_r": {
           "hide_name": 0,
-          "bits": [ "0", "0", "0", "0", "0", "0", "0", "0" ],
+          "bits": [ 653, 659, 471, 447, 640, 655, 468, 469 ],
           "attributes": {
             "hdlname": "rx_24_fifo rd_addr_gray_wr_r",
             "src": "top.v:283.17-294.5|complex_fifo.v:27.22-27.39"
@@ -24904,15 +33094,23 @@
         },
         "rx_24_fifo.rd_clk_i": {
           "hide_name": 0,
-          "bits": [ 58 ],
+          "bits": [ 111 ],
           "attributes": {
             "hdlname": "rx_24_fifo rd_clk_i",
             "src": "top.v:283.17-294.5|complex_fifo.v:12.29-12.37"
           }
         },
+        "rx_24_fifo.rd_data_o": {
+          "hide_name": 0,
+          "bits": [ 71, 683, 684, 685, 686, 687, 80, 688, 689, 690, 691, 692, 693, 694, 79, 695, 667, 668, 669, 670, 671, 672, 77, 673, 674, 675, 676, 677, 678, 679, 76, 680 ],
+          "attributes": {
+            "hdlname": "rx_24_fifo rd_data_o",
+            "src": "top.v:283.17-294.5|complex_fifo.v:14.33-14.42"
+          }
+        },
         "rx_24_fifo.rd_en_i": {
           "hide_name": 0,
-          "bits": [ "0" ],
+          "bits": [ 106 ],
           "attributes": {
             "hdlname": "rx_24_fifo rd_en_i",
             "src": "top.v:283.17-294.5|complex_fifo.v:13.29-13.36"
@@ -24920,7 +33118,7 @@
         },
         "rx_24_fifo.rd_rst_i": {
           "hide_name": 0,
-          "bits": [ 55 ],
+          "bits": [ 104 ],
           "attributes": {
             "hdlname": "rx_24_fifo rd_rst_i",
             "src": "top.v:283.17-294.5|complex_fifo.v:11.29-11.37"
@@ -24928,7 +33126,7 @@
         },
         "rx_24_fifo.wr_addr": {
           "hide_name": 0,
-          "bits": [ 300, 302, 301, 295, 292, 289, 298, 287 ],
+          "bits": [ 681, 455, 454, 452, 463, 460, 457, 682 ],
           "attributes": {
             "hdlname": "rx_24_fifo wr_addr",
             "src": "top.v:283.17-294.5|complex_fifo.v:20.22-20.29"
@@ -24936,30 +33134,85 @@
         },
         "rx_24_fifo.wr_addr_gray": {
           "hide_name": 0,
-          "bits": [ 394, 393, 392, 391, 390, 389, 388, 287 ],
+          "bits": [ 763, 762, 760, 759, 753, 752, 751, 682 ],
           "attributes": {
             "hdlname": "rx_24_fifo wr_addr_gray",
             "src": "top.v:283.17-294.5|complex_fifo.v:21.22-21.34"
           }
         },
-        "rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_1_D": {
+        "rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D": {
           "hide_name": 0,
-          "bits": [ 387 ],
-          "attributes": {
-            "src": "top.v:283.17-294.5|complex_fifo.v:33.8-33.47"
-          }
-        },
-        "rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_4_D": {
-          "hide_name": 0,
-          "bits": [ 308, 309, 310 ],
+          "bits": [ 639, 640, 641, 642 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
+        "rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_O_I1": {
+          "hide_name": 0,
+          "bits": [ 467, 754, 755 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0": {
+          "hide_name": 0,
+          "bits": [ 757, 462, 655, 459 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I0": {
+          "hide_name": 0,
+          "bits": [ 756, 659, 456, 455 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_4_D": {
+          "hide_name": 0,
+          "bits": [ 758 ],
+          "attributes": {
+            "src": "top.v:283.17-294.5|complex_fifo.v:33.8-33.47"
+          }
+        },
+        "rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_5_D": {
+          "hide_name": 0,
+          "bits": [ 657, 471, 658, 468 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_6_D": {
+          "hide_name": 0,
+          "bits": [ 761 ],
+          "attributes": {
+            "src": "top.v:283.17-294.5|complex_fifo.v:33.8-33.47"
+          }
+        },
+        "rx_24_fifo.wr_addr_gray_SB_DFFESR_Q_7_D": {
+          "hide_name": 0,
+          "bits": [ 653, 654, 655, 656 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "rx_24_fifo.wr_addr_gray_SB_LUT4_I2_1_I3": {
+          "hide_name": 0,
+          "bits": [ "0", 455, 453, 464, 461, 458, 765 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:283.17-294.5|complex_fifo.v:57.23-57.34|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
+          }
+        },
         "rx_24_fifo.wr_addr_gray_SB_LUT4_I2_I3": {
           "hide_name": 0,
-          "bits": [ "0", 300, 400, 399, 398, 397, 396, 395 ],
+          "bits": [ "0", 681, 770, 769, 768, 767, 766, 764 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:283.17-294.5|complex_fifo.v:42.14-42.28|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
@@ -24967,7 +33220,7 @@
         },
         "rx_24_fifo.wr_addr_gray_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 386, 383, 381, 382, 385, 384, 380, 379 ],
+          "bits": [ 750, 660, 651, 645, 646, 749, 748, 643 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:283.17-294.5|complex_fifo.v:42.14-42.28|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
@@ -24975,7 +33228,7 @@
         },
         "rx_24_fifo.wr_addr_gray_rd": {
           "hide_name": 0,
-          "bits": [ 408, 407, 406, 405, 404, 403, 402, 401 ],
+          "bits": [ 778, 777, 776, 775, 774, 773, 772, 771 ],
           "attributes": {
             "hdlname": "rx_24_fifo wr_addr_gray_rd",
             "src": "top.v:283.17-294.5|complex_fifo.v:22.22-22.37"
@@ -24983,7 +33236,7 @@
         },
         "rx_24_fifo.wr_addr_gray_rd_r": {
           "hide_name": 0,
-          "bits": [ 374, 375, 376, 368, 369, 377, 371, 372 ],
+          "bits": [ 722, 728, 731, 717, 718, 724, 634, 636 ],
           "attributes": {
             "hdlname": "rx_24_fifo wr_addr_gray_rd_r",
             "src": "top.v:283.17-294.5|complex_fifo.v:23.22-23.39"
@@ -24991,15 +33244,23 @@
         },
         "rx_24_fifo.wr_clk_i": {
           "hide_name": 0,
-          "bits": [ 169 ],
+          "bits": [ 220 ],
           "attributes": {
             "hdlname": "rx_24_fifo wr_clk_i",
             "src": "top.v:283.17-294.5|complex_fifo.v:7.29-7.37"
           }
         },
+        "rx_24_fifo.wr_data_i": {
+          "hide_name": 0,
+          "bits": [ 413, 411, 407, 405, 403, 401, 399, 397, 395, 393, 391, 389, 385, 383, 381, 379, 377, 375, 373, 371, 369, 367, 425, 423, 421, 419, 417, 415, 409, 387, 365, 363 ],
+          "attributes": {
+            "hdlname": "rx_24_fifo wr_data_i",
+            "src": "top.v:283.17-294.5|complex_fifo.v:9.33-9.42"
+          }
+        },
         "rx_24_fifo.wr_en_i": {
           "hide_name": 0,
-          "bits": [ 268 ],
+          "bits": [ 443 ],
           "attributes": {
             "hdlname": "rx_24_fifo wr_en_i",
             "src": "top.v:283.17-294.5|complex_fifo.v:8.29-8.36"
@@ -25007,7 +33268,7 @@
         },
         "rx_24_fifo.wr_rst_i": {
           "hide_name": 0,
-          "bits": [ 55 ],
+          "bits": [ 104 ],
           "attributes": {
             "hdlname": "rx_24_fifo wr_rst_i",
             "src": "top.v:283.17-294.5|complex_fifo.v:6.29-6.37"
@@ -25015,7 +33276,7 @@
         },
         "smi_ctrl_ins.i_cs": {
           "hide_name": 0,
-          "bits": [ 410 ],
+          "bits": [ 780 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_cs",
             "src": "top.v:296.13-327.5|smi_ctrl.v:9.29-9.33"
@@ -25023,7 +33284,7 @@
         },
         "smi_ctrl_ins.i_data_in": {
           "hide_name": 0,
-          "bits": [ 62, 59, 146, 144, 142, 140, 139, 136 ],
+          "bits": [ 115, 112, 196, 195, 194, 192, 190, 188 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_data_in",
             "src": "top.v:296.13-327.5|smi_ctrl.v:7.29-7.38"
@@ -25031,7 +33292,7 @@
         },
         "smi_ctrl_ins.i_fetch_cmd": {
           "hide_name": 0,
-          "bits": [ 488 ],
+          "bits": [ 867 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_fetch_cmd",
             "src": "top.v:296.13-327.5|smi_ctrl.v:10.29-10.40"
@@ -25047,15 +33308,23 @@
         },
         "smi_ctrl_ins.i_fifo_09_full": {
           "hide_name": 0,
-          "bits": [ 213 ],
+          "bits": [ 330 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_fifo_09_full",
             "src": "top.v:296.13-327.5|smi_ctrl.v:16.29-16.43"
           }
         },
+        "smi_ctrl_ins.i_fifo_09_pulled_data": {
+          "hide_name": 0,
+          "bits": [ 68, 546, 547, 548, 549, 550, 96, 551, 552, 553, 554, 555, 556, 557, 91, 558, 531, 532, 533, 534, 535, 536, 97, 537, 538, 539, 540, 541, 542, 543, 92, 544 ],
+          "attributes": {
+            "hdlname": "smi_ctrl_ins i_fifo_09_pulled_data",
+            "src": "top.v:296.13-327.5|smi_ctrl.v:15.29-15.50"
+          }
+        },
         "smi_ctrl_ins.i_fifo_24_empty": {
           "hide_name": 0,
-          "bits": [ 367 ],
+          "bits": [ 66 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_fifo_24_empty",
             "src": "top.v:296.13-327.5|smi_ctrl.v:23.29-23.44"
@@ -25063,15 +33332,23 @@
         },
         "smi_ctrl_ins.i_fifo_24_full": {
           "hide_name": 0,
-          "bits": [ 269 ],
+          "bits": [ 444 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_fifo_24_full",
             "src": "top.v:296.13-327.5|smi_ctrl.v:22.29-22.43"
           }
         },
+        "smi_ctrl_ins.i_fifo_24_pulled_data": {
+          "hide_name": 0,
+          "bits": [ 71, 683, 684, 685, 686, 687, 80, 688, 689, 690, 691, 692, 693, 694, 79, 695, 667, 668, 669, 670, 671, 672, 77, 673, 674, 675, 676, 677, 678, 679, 76, 680 ],
+          "attributes": {
+            "hdlname": "smi_ctrl_ins i_fifo_24_pulled_data",
+            "src": "top.v:296.13-327.5|smi_ctrl.v:21.29-21.50"
+          }
+        },
         "smi_ctrl_ins.i_ioc": {
           "hide_name": 0,
-          "bits": [ 132, 160, 163, 162, 161 ],
+          "bits": [ 48, 49, 214, 213, 212 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_ioc",
             "src": "top.v:296.13-327.5|smi_ctrl.v:6.29-6.34"
@@ -25079,7 +33356,7 @@
         },
         "smi_ctrl_ins.i_load_cmd": {
           "hide_name": 0,
-          "bits": [ 495 ],
+          "bits": [ 874 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_load_cmd",
             "src": "top.v:296.13-327.5|smi_ctrl.v:11.29-11.39"
@@ -25087,7 +33364,7 @@
         },
         "smi_ctrl_ins.i_reset": {
           "hide_name": 0,
-          "bits": [ 55 ],
+          "bits": [ 104 ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_reset",
             "src": "top.v:296.13-327.5|smi_ctrl.v:3.29-3.36"
@@ -25128,7 +33405,7 @@
         },
         "smi_ctrl_ins.i_smi_test": {
           "hide_name": 0,
-          "bits": [ "1" ],
+          "bits": [ "0" ],
           "attributes": {
             "hdlname": "smi_ctrl_ins i_smi_test",
             "src": "top.v:296.13-327.5|smi_ctrl.v:34.29-34.39"
@@ -25142,9 +33419,89 @@
             "src": "top.v:296.13-327.5|smi_ctrl.v:4.29-4.38"
           }
         },
+        "smi_ctrl_ins.int_cnt_09": {
+          "hide_name": 0,
+          "bits": [ "0", "0", "0", 88, 86, 87 ],
+          "attributes": {
+            "hdlname": "smi_ctrl_ins int_cnt_09",
+            "src": "top.v:296.13-327.5|smi_ctrl.v:94.15-94.25"
+          }
+        },
+        "smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_1_D": {
+          "hide_name": 0,
+          "bits": [ 783 ],
+          "attributes": {
+          }
+        },
+        "smi_ctrl_ins.int_cnt_09_SB_DFFESR_Q_D": {
+          "hide_name": 0,
+          "bits": [ 781 ],
+          "attributes": {
+          }
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@@ -25191,7 +33531,7 @@
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@@ -25271,42 +33771,112 @@
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@@ -25315,57 +33885,9 @@
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-            "hdlname": "smi_ctrl_ins r_smi_test_count_24",
-            "src": "top.v:296.13-327.5|smi_ctrl.v:99.15-99.34"
-          }
-        },
-        "smi_ctrl_ins.r_smi_test_count_24_SB_DFFESR_Q_D": {
-          "hide_name": 0,
-          "bits": [ 473, 472, 471, 470, 469, 468, 467, 466 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:296.13-327.5|smi_ctrl.v:150.48-150.74|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
-          }
-        },
-        "smi_ctrl_ins.r_smi_test_count_24_SB_DFFESR_Q_D_SB_LUT4_O_I3": {
-          "hide_name": 0,
-          "bits": [ "0", 440, 460, 465, 464, 463, 461, 462 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "top.v:296.13-327.5|smi_ctrl.v:150.48-150.74|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
-          }
-        },
         "spi_if_ins.i_data_out": {
           "hide_name": 0,
-          "bits": [ 334, 318, 321, 323, 325, 327, 329, 332 ],
+          "bits": [ 498, 480, 483, 485, 487, 489, 491, 494 ],
           "attributes": {
             "hdlname": "spi_if_ins i_data_out",
             "src": "top.v:92.11-108.5|spi_if.v:10.29-10.39"
@@ -25373,7 +33895,7 @@
         },
         "spi_if_ins.i_rst_b": {
           "hide_name": 0,
-          "bits": [ 55 ],
+          "bits": [ 104 ],
           "attributes": {
             "hdlname": "spi_if_ins i_rst_b",
             "src": "top.v:92.11-108.5|spi_if.v:5.29-5.36"
@@ -25405,7 +33927,7 @@
         },
         "spi_if_ins.i_sys_clk": {
           "hide_name": 0,
-          "bits": [ 58 ],
+          "bits": [ 111 ],
           "attributes": {
             "hdlname": "spi_if_ins i_sys_clk",
             "src": "top.v:92.11-108.5|spi_if.v:6.29-6.38"
@@ -25413,7 +33935,7 @@
         },
         "spi_if_ins.o_cs": {
           "hide_name": 0,
-          "bits": [ 478, 72, 410, 475 ],
+          "bits": [ 853, 123, 780, 850 ],
           "attributes": {
             "hdlname": "spi_if_ins o_cs",
             "src": "top.v:92.11-108.5|spi_if.v:11.29-11.33"
@@ -25421,7 +33943,7 @@
         },
         "spi_if_ins.o_cs_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ "0", "0", "0", 474, "0", "0", 409, "0", "0", 70, "0", "0" ],
+          "bits": [ "0", "0", "0", 849, "0", "0", 779, "0", "0", 121, "0", "0" ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:92.11-108.5|spi_if.v:65.21-70.28|spi_if.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:583.28-583.35"
@@ -25429,30 +33951,24 @@
         },
         "spi_if_ins.o_cs_SB_DFFESR_Q_R": {
           "hide_name": 0,
-          "bits": [ 73, 619, 620, 621 ],
+          "bits": [ 124, 998, 999, 1000 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:92.11-108.5|spi_if.v:65.21-70.28|spi_if.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22",
             "unused_bits": "1 2 3"
           }
         },
-        "spi_if_ins.o_cs_SB_LUT4_I0_O": {
+        "spi_if_ins.o_cs_SB_LUT4_I2_2_O": {
           "hide_name": 0,
-          "bits": [ 574, 319, 419, 417 ],
+          "bits": [ 949, 481, 495, 798 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "spi_if_ins.o_cs_SB_LUT4_I1_2_O": {
+        "spi_if_ins.o_cs_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 317 ],
-          "attributes": {
-          }
-        },
-        "spi_if_ins.o_cs_SB_LUT4_I1_O": {
-          "hide_name": 0,
-          "bits": [ 415, 416, 330, 134 ],
+          "bits": [ 794, 797, 492, 148 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -25460,7 +33976,7 @@
         },
         "spi_if_ins.o_data_in": {
           "hide_name": 0,
-          "bits": [ 62, 59, 146, 144, 142, 140, 139, 136 ],
+          "bits": [ 115, 112, 196, 195, 194, 192, 190, 188 ],
           "attributes": {
             "hdlname": "spi_if_ins o_data_in",
             "src": "top.v:92.11-108.5|spi_if.v:9.29-9.38"
@@ -25468,13 +33984,13 @@
         },
         "spi_if_ins.o_data_in_SB_DFFE_Q_E": {
           "hide_name": 0,
-          "bits": [ 480 ],
+          "bits": [ 855 ],
           "attributes": {
           }
         },
         "spi_if_ins.o_fetch_cmd": {
           "hide_name": 0,
-          "bits": [ 488 ],
+          "bits": [ 867 ],
           "attributes": {
             "hdlname": "spi_if_ins o_fetch_cmd",
             "src": "top.v:92.11-108.5|spi_if.v:12.29-12.40"
@@ -25482,19 +33998,35 @@
         },
         "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 486 ],
+          "bits": [ 865 ],
           "attributes": {
           }
         },
         "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 487 ],
+          "bits": [ 866 ],
           "attributes": {
           }
         },
+        "spi_if_ins.o_fetch_cmd_SB_DFFESR_Q_E_SB_LUT4_O_I3": {
+          "hide_name": 0,
+          "bits": [ 862, 870, 871 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "spi_if_ins.o_fetch_cmd_SB_LUT4_I3_1_O": {
+          "hide_name": 0,
+          "bits": [ 50, 796 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
         "spi_if_ins.o_fetch_cmd_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 132, 116, 121, 115 ],
+          "bits": [ 133, 50, 872 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -25502,7 +34034,7 @@
         },
         "spi_if_ins.o_ioc": {
           "hide_name": 0,
-          "bits": [ 132, 160, 163, 162, 161 ],
+          "bits": [ 48, 49, 214, 213, 212 ],
           "attributes": {
             "hdlname": "spi_if_ins o_ioc",
             "src": "top.v:92.11-108.5|spi_if.v:8.29-8.34"
@@ -25510,7 +34042,7 @@
         },
         "spi_if_ins.o_load_cmd": {
           "hide_name": 0,
-          "bits": [ 495 ],
+          "bits": [ 874 ],
           "attributes": {
             "hdlname": "spi_if_ins o_load_cmd",
             "src": "top.v:92.11-108.5|spi_if.v:13.29-13.39"
@@ -25518,7 +34050,7 @@
         },
         "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 490, 491 ],
+          "bits": [ 869, 861 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -25526,59 +34058,43 @@
         },
         "spi_if_ins.o_load_cmd_SB_DFFESR_Q_D_SB_LUT4_I1_O": {
           "hide_name": 0,
-          "bits": [ 71 ],
+          "bits": [ 862, 870, 122 ],
           "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
         "spi_if_ins.o_load_cmd_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 494 ],
+          "bits": [ 873 ],
           "attributes": {
           }
         },
-        "spi_if_ins.o_load_cmd_SB_LUT4_I3_O": {
+        "spi_if_ins.o_load_cmd_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 55, 76 ],
+          "bits": [ 104, 130 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I2_O": {
+        "spi_if_ins.o_load_cmd_SB_LUT4_I2_O_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 60 ],
+          "bits": [ 113 ],
           "attributes": {
           }
         },
-        "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O": {
+        "spi_if_ins.o_load_cmd_SB_LUT4_I2_O_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 47, 498 ],
+          "bits": [ 172, 210 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_1_O": {
-          "hide_name": 0,
-          "bits": [ 147 ],
-          "attributes": {
-          }
-        },
-        "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_2_O": {
-          "hide_name": 0,
-          "bits": [ 152 ],
-          "attributes": {
-          }
-        },
-        "spi_if_ins.o_load_cmd_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_I3_O": {
-          "hide_name": 0,
-          "bits": [ 137 ],
-          "attributes": {
-          }
-        },
         "spi_if_ins.o_spi_miso": {
           "hide_name": 0,
-          "bits": [ 315 ],
+          "bits": [ 477 ],
           "attributes": {
             "hdlname": "spi_if_ins o_spi_miso",
             "src": "top.v:92.11-108.5|spi_if.v:17.29-17.39"
@@ -25586,7 +34102,7 @@
         },
         "spi_if_ins.r_tx_byte": {
           "hide_name": 0,
-          "bits": [ 507, 506, 505, 504, 503, 502, 501, 500 ],
+          "bits": [ 883, 882, 881, 880, 879, 878, 877, 876 ],
           "attributes": {
             "hdlname": "spi_if_ins r_tx_byte",
             "src": "top.v:92.11-108.5|spi_if.v:32.17-32.26"
@@ -25594,7 +34110,7 @@
         },
         "spi_if_ins.r_tx_data_valid": {
           "hide_name": 0,
-          "bits": [ 510 ],
+          "bits": [ 886 ],
           "attributes": {
             "hdlname": "spi_if_ins r_tx_data_valid",
             "src": "top.v:92.11-108.5|spi_if.v:31.17-31.32"
@@ -25602,7 +34118,7 @@
         },
         "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 493, 508 ],
+          "bits": [ 862, 884 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -25610,19 +34126,19 @@
         },
         "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_D_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 499 ],
+          "bits": [ 875 ],
           "attributes": {
           }
         },
         "spi_if_ins.r_tx_data_valid_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 509 ],
+          "bits": [ 885 ],
           "attributes": {
           }
         },
         "spi_if_ins.r_tx_data_valid_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 511 ],
+          "bits": [ 889, 888, 887 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -25630,7 +34146,7 @@
         },
         "spi_if_ins.spi.SCKr": {
           "hide_name": 0,
-          "bits": [ 517, 515, 516 ],
+          "bits": [ 890, 888, 889 ],
           "attributes": {
             "hdlname": "spi_if_ins spi SCKr",
             "src": "top.v:92.11-108.5|spi_slave.v:62.13-62.17|spi_if.v:42.15-54.6"
@@ -25638,7 +34154,7 @@
         },
         "spi_if_ins.spi.SCKr_SB_LUT4_I0_O": {
           "hide_name": 0,
-          "bits": [ 512, 513, 511 ],
+          "bits": [ 909, 893, 887 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -25670,7 +34186,7 @@
         },
         "spi_if_ins.spi.i_sys_clk": {
           "hide_name": 0,
-          "bits": [ 58 ],
+          "bits": [ 111 ],
           "attributes": {
             "hdlname": "spi_if_ins spi i_sys_clk",
             "src": "top.v:92.11-108.5|spi_slave.v:5.23-5.32|spi_if.v:42.15-54.6"
@@ -25678,7 +34194,7 @@
         },
         "spi_if_ins.spi.i_tx_byte": {
           "hide_name": 0,
-          "bits": [ 507, 506, 505, 504, 503, 502, 501, 500 ],
+          "bits": [ 883, 882, 881, 880, 879, 878, 877, 876 ],
           "attributes": {
             "hdlname": "spi_if_ins spi i_tx_byte",
             "src": "top.v:92.11-108.5|spi_slave.v:9.23-9.32|spi_if.v:42.15-54.6"
@@ -25686,7 +34202,7 @@
         },
         "spi_if_ins.spi.i_tx_data_valid": {
           "hide_name": 0,
-          "bits": [ 510 ],
+          "bits": [ 886 ],
           "attributes": {
             "hdlname": "spi_if_ins spi i_tx_data_valid",
             "src": "top.v:92.11-108.5|spi_slave.v:8.23-8.38|spi_if.v:42.15-54.6"
@@ -25694,7 +34210,7 @@
         },
         "spi_if_ins.spi.o_rx_byte": {
           "hide_name": 0,
-          "bits": [ 485, 484, 483, 482, 481, 477, 476, 479 ],
+          "bits": [ 860, 859, 858, 857, 856, 852, 851, 854 ],
           "attributes": {
             "hdlname": "spi_if_ins spi o_rx_byte",
             "src": "top.v:92.11-108.5|spi_slave.v:7.23-7.32|spi_if.v:42.15-54.6"
@@ -25702,7 +34218,7 @@
         },
         "spi_if_ins.spi.o_rx_data_valid": {
           "hide_name": 0,
-          "bits": [ 493 ],
+          "bits": [ 862 ],
           "attributes": {
             "hdlname": "spi_if_ins spi o_rx_data_valid",
             "src": "top.v:92.11-108.5|spi_slave.v:6.23-6.38|spi_if.v:42.15-54.6"
@@ -25710,7 +34226,7 @@
         },
         "spi_if_ins.spi.o_spi_miso": {
           "hide_name": 0,
-          "bits": [ 315 ],
+          "bits": [ 477 ],
           "attributes": {
             "hdlname": "spi_if_ins spi o_spi_miso",
             "src": "top.v:92.11-108.5|spi_slave.v:13.23-13.33|spi_if.v:42.15-54.6"
@@ -25718,14 +34234,14 @@
         },
         "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 529 ],
+          "bits": [ 904 ],
           "attributes": {
             "src": "top.v:92.11-108.5|spi_slave.v:69.3-86.6|spi_if.v:42.15-54.6"
           }
         },
         "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2": {
           "hide_name": 0,
-          "bits": [ 500, 531, 511 ],
+          "bits": [ 876, 905, 887 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -25733,15 +34249,15 @@
         },
         "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0": {
           "hide_name": 0,
-          "bits": [ 532, 533, 512, 534 ],
+          "bits": [ 906, 907, 908, 909 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_2_I0": {
+        "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ 539, 540, 512, 518 ],
+          "bits": [ 910, 911, 891, 912 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -25749,13 +34265,13 @@
         },
         "spi_if_ins.spi.o_spi_miso_SB_DFFE_Q_E": {
           "hide_name": 0,
-          "bits": [ 530 ],
+          "bits": [ 894 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.r2_rx_done": {
           "hide_name": 0,
-          "bits": [ 546 ],
+          "bits": [ 920 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r2_rx_done",
             "src": "top.v:92.11-108.5|spi_slave.v:22.7-22.17|spi_if.v:42.15-54.6"
@@ -25763,7 +34279,7 @@
         },
         "spi_if_ins.spi.r3_rx_done": {
           "hide_name": 0,
-          "bits": [ 547 ],
+          "bits": [ 921 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r3_rx_done",
             "src": "top.v:92.11-108.5|spi_slave.v:23.7-23.17|spi_if.v:42.15-54.6"
@@ -25771,14 +34287,14 @@
         },
         "spi_if_ins.spi.r3_rx_done_SB_LUT4_I2_O": {
           "hide_name": 0,
-          "bits": [ 521 ],
+          "bits": [ 896 ],
           "attributes": {
             "src": "top.v:92.11-108.5|spi_slave.v:48.3-60.6|spi_if.v:42.15-54.6"
           }
         },
         "spi_if_ins.spi.r_rx_bit_count": {
           "hide_name": 0,
-          "bits": [ 553, 551, 549 ],
+          "bits": [ 927, 925, 923 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_rx_bit_count",
             "src": "top.v:92.11-108.5|spi_slave.v:17.13-17.27|spi_if.v:42.15-54.6"
@@ -25786,7 +34302,7 @@
         },
         "spi_if_ins.spi.r_rx_bit_count_SB_DFFR_Q_2_D": {
           "hide_name": 0,
-          "bits": [ 552, 551, 549 ],
+          "bits": [ 926, 925, 923 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:92.11-108.5|spi_slave.v:34.25-34.43|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.23-33.24"
@@ -25794,7 +34310,7 @@
         },
         "spi_if_ins.spi.r_rx_bit_count_SB_DFFR_Q_D": {
           "hide_name": 0,
-          "bits": [ 552, 550, 548 ],
+          "bits": [ 926, 924, 922 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:92.11-108.5|spi_slave.v:34.25-34.43|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
@@ -25802,7 +34318,7 @@
         },
         "spi_if_ins.spi.r_rx_bit_count_SB_DFFR_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ "0", 553, 554 ],
+          "bits": [ "0", 927, 928 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:92.11-108.5|spi_slave.v:34.25-34.43|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
@@ -25810,7 +34326,7 @@
         },
         "spi_if_ins.spi.r_rx_byte": {
           "hide_name": 0,
-          "bits": [ 528, 527, 526, 525, 524, 523, 522, 520 ],
+          "bits": [ 903, 902, 901, 900, 899, 898, 897, 895 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_rx_byte",
             "src": "top.v:92.11-108.5|spi_slave.v:20.13-20.22|spi_if.v:42.15-54.6"
@@ -25818,7 +34334,7 @@
         },
         "spi_if_ins.spi.r_rx_done": {
           "hide_name": 0,
-          "bits": [ 545 ],
+          "bits": [ 919 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_rx_done",
             "src": "top.v:92.11-108.5|spi_slave.v:21.7-21.16|spi_if.v:42.15-54.6"
@@ -25826,7 +34342,7 @@
         },
         "spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D": {
           "hide_name": 0,
-          "bits": [ 44, 563 ],
+          "bits": [ 44, 937 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -25834,19 +34350,19 @@
         },
         "spi_if_ins.spi.r_rx_done_SB_DFFER_Q_D_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 556 ],
+          "bits": [ 930 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.r_rx_done_SB_DFFER_Q_E": {
           "hide_name": 0,
-          "bits": [ 564 ],
+          "bits": [ 938 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.r_temp_rx_byte": {
           "hide_name": 0,
-          "bits": [ 562, 561, 560, 559, 558, 557, 555, "x" ],
+          "bits": [ 936, 935, 934, 933, 932, 931, 929, "x" ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_temp_rx_byte",
             "src": "top.v:92.11-108.5|spi_slave.v:19.13-19.27|spi_if.v:42.15-54.6"
@@ -25854,7 +34370,7 @@
         },
         "spi_if_ins.spi.r_tx_bit_count": {
           "hide_name": 0,
-          "bits": [ 518, 512, 519 ],
+          "bits": [ 891, 909, 892 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_tx_bit_count",
             "src": "top.v:92.11-108.5|spi_slave.v:18.13-18.27|spi_if.v:42.15-54.6"
@@ -25862,7 +34378,7 @@
         },
         "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 565, 569, 568 ],
+          "bits": [ 939, 943, 942 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:92.11-108.5|spi_slave.v:77.27-77.45|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
@@ -25870,7 +34386,7 @@
         },
         "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ "1", 518, 567 ],
+          "bits": [ "1", 891, 941 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:92.11-108.5|spi_slave.v:77.27-77.45|spi_if.v:42.15-54.6|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
@@ -25878,13 +34394,13 @@
         },
         "spi_if_ins.spi.r_tx_bit_count_SB_DFFESR_Q_R": {
           "hide_name": 0,
-          "bits": [ 566 ],
+          "bits": [ 940 ],
           "attributes": {
           }
         },
         "spi_if_ins.spi.r_tx_byte": {
           "hide_name": 0,
-          "bits": [ 543, 541, 535, 537, 544, 542, 536, 538 ],
+          "bits": [ 910, 917, 913, 915, 911, 918, 914, 916 ],
           "attributes": {
             "hdlname": "spi_if_ins spi r_tx_byte",
             "src": "top.v:92.11-108.5|spi_slave.v:24.13-24.22|spi_if.v:42.15-54.6"
@@ -25892,49 +34408,48 @@
         },
         "spi_if_ins.spi.r_tx_byte_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 514 ],
+          "bits": [ 944 ],
           "attributes": {
           }
         },
         "spi_if_ins.state_if": {
           "hide_name": 0,
-          "bits": [ 496, 497, 491 ],
+          "bits": [ 863, 864, 861 ],
           "attributes": {
             "hdlname": "spi_if_ins state_if",
             "src": "top.v:92.11-108.5|spi_if.v:28.17-28.25"
           }
         },
-        "spi_if_ins.state_if_SB_DFFESR_Q_1_R": {
+        "spi_if_ins.state_if_SB_DFFESR_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 489 ],
-          "attributes": {
-          }
-        },
-        "spi_if_ins.state_if_SB_DFFESR_Q_D": {
-          "hide_name": 0,
-          "bits": [ 572, 479, 570, 493 ],
+          "bits": [ 946, 854, 870, 862 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
+        "spi_if_ins.state_if_SB_DFFESR_Q_1_R": {
+          "hide_name": 0,
+          "bits": [ 868 ],
+          "attributes": {
+          }
+        },
         "spi_if_ins.state_if_SB_DFFE_Q_D": {
           "hide_name": 0,
-          "bits": [ 490, 492, 493 ],
+          "bits": [ 947 ],
           "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+            "src": "top.v:92.11-108.5|spi_if.v:56.5-111.8"
           }
         },
         "spi_if_ins.state_if_SB_DFFE_Q_E": {
           "hide_name": 0,
-          "bits": [ 571 ],
+          "bits": [ 945 ],
           "attributes": {
           }
         },
         "spi_if_ins.w_rx_data": {
           "hide_name": 0,
-          "bits": [ 485, 484, 483, 482, 481, 477, 476, 479 ],
+          "bits": [ 860, 859, 858, 857, 856, 852, 851, 854 ],
           "attributes": {
             "hdlname": "spi_if_ins w_rx_data",
             "src": "top.v:92.11-108.5|spi_if.v:30.17-30.26"
@@ -25942,7 +34457,7 @@
         },
         "spi_if_ins.w_rx_data_valid": {
           "hide_name": 0,
-          "bits": [ 493 ],
+          "bits": [ 862 ],
           "attributes": {
             "hdlname": "spi_if_ins w_rx_data_valid",
             "src": "top.v:92.11-108.5|spi_if.v:29.17-29.32"
@@ -25950,7 +34465,7 @@
         },
         "sys_ctrl_ins.i_cs": {
           "hide_name": 0,
-          "bits": [ 478 ],
+          "bits": [ 853 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_cs",
             "src": "top.v:113.13-126.5|sys_ctrl.v:9.29-9.33"
@@ -25958,7 +34473,7 @@
         },
         "sys_ctrl_ins.i_data_in": {
           "hide_name": 0,
-          "bits": [ 62, 59, 146, 144, 142, 140, 139, 136 ],
+          "bits": [ 115, 112, 196, 195, 194, 192, 190, 188 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_data_in",
             "src": "top.v:113.13-126.5|sys_ctrl.v:7.29-7.38"
@@ -25974,7 +34489,7 @@
         },
         "sys_ctrl_ins.i_fetch_cmd": {
           "hide_name": 0,
-          "bits": [ 488 ],
+          "bits": [ 867 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_fetch_cmd",
             "src": "top.v:113.13-126.5|sys_ctrl.v:10.29-10.40"
@@ -25982,7 +34497,7 @@
         },
         "sys_ctrl_ins.i_ioc": {
           "hide_name": 0,
-          "bits": [ 132, 160, 163, 162, 161 ],
+          "bits": [ 48, 49, 214, 213, 212 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_ioc",
             "src": "top.v:113.13-126.5|sys_ctrl.v:6.29-6.34"
@@ -25990,7 +34505,7 @@
         },
         "sys_ctrl_ins.i_load_cmd": {
           "hide_name": 0,
-          "bits": [ 495 ],
+          "bits": [ 874 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_load_cmd",
             "src": "top.v:113.13-126.5|sys_ctrl.v:11.29-11.39"
@@ -26006,7 +34521,7 @@
         },
         "sys_ctrl_ins.i_sys_clk": {
           "hide_name": 0,
-          "bits": [ 58 ],
+          "bits": [ 111 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins i_sys_clk",
             "src": "top.v:113.13-126.5|sys_ctrl.v:4.29-4.38"
@@ -26014,7 +34529,7 @@
         },
         "sys_ctrl_ins.o_data_out": {
           "hide_name": 0,
-          "bits": [ 574, "0", "0", "0", "0", "0", "0", "0" ],
+          "bits": [ 949, "0", "0", "0", "0", "0", "0", "0" ],
           "attributes": {
             "hdlname": "sys_ctrl_ins o_data_out",
             "src": "top.v:113.13-126.5|sys_ctrl.v:8.29-8.39"
@@ -26022,21 +34537,13 @@
         },
         "sys_ctrl_ins.o_data_out_SB_DFFE_Q_E": {
           "hide_name": 0,
-          "bits": [ 573 ],
+          "bits": [ 948 ],
           "attributes": {
           }
         },
-        "sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I3": {
+        "sys_ctrl_ins.o_data_out_SB_LUT4_I0_I2": {
           "hide_name": 0,
-          "bits": [ 132, 161, 164, 160 ],
-          "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
-          }
-        },
-        "sys_ctrl_ins.o_data_out_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_I2_O": {
-          "hide_name": 0,
-          "bits": [ 48, 16 ],
+          "bits": [ 495, 496 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -26044,7 +34551,7 @@
         },
         "sys_ctrl_ins.o_soft_reset": {
           "hide_name": 0,
-          "bits": [ 55 ],
+          "bits": [ 104 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins o_soft_reset",
             "src": "top.v:113.13-126.5|sys_ctrl.v:13.29-13.41"
@@ -26052,13 +34559,13 @@
         },
         "sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_E": {
           "hide_name": 0,
-          "bits": [ 575 ],
+          "bits": [ 950 ],
           "attributes": {
           }
         },
         "sys_ctrl_ins.o_soft_reset_SB_DFFESS_Q_S": {
           "hide_name": 0,
-          "bits": [ 576 ],
+          "bits": [ 951 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:113.13-126.5|sys_ctrl.v:72.17-72.36|/usr/local/bin/../share/yosys/cmp2lut.v:24.22-24.23"
@@ -26066,7 +34573,7 @@
         },
         "sys_ctrl_ins.reset_cmd": {
           "hide_name": 0,
-          "bits": [ 577 ],
+          "bits": [ 952 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins reset_cmd",
             "src": "top.v:113.13-126.5|sys_ctrl.v:35.9-35.18"
@@ -26074,19 +34581,19 @@
         },
         "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 582 ],
+          "bits": [ 957 ],
           "attributes": {
           }
         },
         "sys_ctrl_ins.reset_cmd_SB_DFFESR_Q_R": {
           "hide_name": 0,
-          "bits": [ 583 ],
+          "bits": [ 958 ],
           "attributes": {
           }
         },
         "sys_ctrl_ins.reset_count": {
           "hide_name": 0,
-          "bits": [ 581, 580, 579, 578 ],
+          "bits": [ 956, 954, 955, 953 ],
           "attributes": {
             "hdlname": "sys_ctrl_ins reset_count",
             "src": "top.v:113.13-126.5|sys_ctrl.v:34.15-34.26"
@@ -26094,31 +34601,31 @@
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_1_D": {
           "hide_name": 0,
-          "bits": [ 586 ],
+          "bits": [ 961 ],
           "attributes": {
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_2_D": {
           "hide_name": 0,
-          "bits": [ 588 ],
+          "bits": [ 963 ],
           "attributes": {
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_3_D": {
           "hide_name": 0,
-          "bits": [ 589 ],
+          "bits": [ 964 ],
           "attributes": {
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_D": {
           "hide_name": 0,
-          "bits": [ 585 ],
+          "bits": [ 960 ],
           "attributes": {
           }
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_D_SB_LUT4_O_I3": {
           "hide_name": 0,
-          "bits": [ "0", 581, 587, 590 ],
+          "bits": [ "0", 956, 962, 965 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "top.v:113.13-126.5|sys_ctrl.v:73.32-73.50|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22"
@@ -26126,69 +34633,69 @@
         },
         "sys_ctrl_ins.reset_count_SB_DFFESR_Q_E": {
           "hide_name": 0,
-          "bits": [ 584 ],
+          "bits": [ 959 ],
           "attributes": {
           }
         },
         "w_clock_spi": {
           "hide_name": 0,
-          "bits": [ 58 ],
+          "bits": [ 111 ],
           "attributes": {
             "src": "top.v:66.16-66.27"
           }
         },
         "w_clock_sys": {
           "hide_name": 0,
-          "bits": [ 58 ],
+          "bits": [ 111 ],
           "attributes": {
             "src": "top.v:67.16-67.27"
           }
         },
         "w_cs": {
           "hide_name": 0,
-          "bits": [ 478, 72, 410, 475 ],
+          "bits": [ 853, 123, 780, 850 ],
           "attributes": {
             "src": "top.v:71.16-71.20"
           }
         },
         "w_fetch": {
           "hide_name": 0,
-          "bits": [ 488 ],
+          "bits": [ 867 ],
           "attributes": {
             "src": "top.v:72.16-72.23"
           }
         },
         "w_ioc": {
           "hide_name": 0,
-          "bits": [ 132, 160, 163, 162, 161 ],
+          "bits": [ 48, 49, 214, 213, 212 ],
           "attributes": {
             "src": "top.v:68.16-68.21"
           }
         },
         "w_load": {
           "hide_name": 0,
-          "bits": [ 495 ],
+          "bits": [ 874 ],
           "attributes": {
             "src": "top.v:73.16-73.22"
           }
         },
         "w_lvds_rx_09_d0": {
           "hide_name": 0,
-          "bits": [ 193 ],
+          "bits": [ 255 ],
           "attributes": {
             "src": "top.v:227.9-227.24"
           }
         },
         "w_lvds_rx_09_d1": {
           "hide_name": 0,
-          "bits": [ 194 ],
+          "bits": [ 256 ],
           "attributes": {
             "src": "top.v:228.9-228.24"
           }
         },
         "w_lvds_rx_09_d1_SB_LUT4_I0_O": {
           "hide_name": 0,
-          "bits": [ 55, 256 ],
+          "bits": [ 359, 360, 104 ],
           "attributes": {
             "force_downto": "00000000000000000000000000000001",
             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
@@ -26196,13 +34703,61 @@
         },
         "w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 171 ],
+          "bits": [ 222 ],
+          "attributes": {
+          }
+        },
+        "w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1": {
+          "hide_name": 0,
+          "bits": [ 321, 319, 969 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "top.v:248.12-257.5|lvds_rx.v:63.42-63.59|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27"
+          }
+        },
+        "w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1_SB_DFFNESR_Q_D": {
+          "hide_name": 0,
+          "bits": [ 968 ],
+          "attributes": {
+          }
+        },
+        "w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I1_SB_DFFNESR_Q_E": {
+          "hide_name": 0,
+          "bits": [ 323 ],
+          "attributes": {
+          }
+        },
+        "w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2": {
+          "hide_name": 0,
+          "bits": [ 329, 321, 967, 331 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O": {
+          "hide_name": 0,
+          "bits": [ 332, 356, 319, 966 ],
+          "attributes": {
+            "force_downto": "00000000000000000000000000000001",
+            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+          }
+        },
+        "w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_I0_1_O": {
+          "hide_name": 0,
+          "bits": [ 325 ],
+          "attributes": {
+          }
+        },
+        "w_lvds_rx_09_d1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_I0_O": {
+          "hide_name": 0,
+          "bits": [ 322 ],
           "attributes": {
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         },
         "w_lvds_rx_09_d1_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 200, 198, 174, 173, 172, 170 ],
+          "bits": [ 300, 298, 225, 224, 223, 221, 296, 294, 292, 290, 288, 286, 282, 280, 278, 276, 274, 272, 270, 268, 266, 264, 314, 312, 310, 308, 306, 304, 302, 284, 262, 260 ],
           "attributes": {
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             "src": "top.v:248.12-257.5|lvds_rx.v:47.13-78.20|lvds_rx.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22"
@@ -26210,47 +34765,44 @@
         },
         "w_lvds_rx_24_d0": {
           "hide_name": 0,
-          "bits": [ 195 ],
+          "bits": [ 257 ],
           "attributes": {
             "src": "top.v:229.9-229.24"
           }
         },
         "w_lvds_rx_24_d1": {
           "hide_name": 0,
-          "bits": [ 196 ],
+          "bits": [ 258 ],
           "attributes": {
             "src": "top.v:230.9-230.24"
           }
         },
-        "w_lvds_rx_24_d1_SB_LUT4_I2_O": {
+        "w_lvds_rx_24_d1_SB_LUT4_I0_O": {
           "hide_name": 0,
-          "bits": [ 591, 271, 277, 278 ],
+          "bits": [ 104, 475 ],
           "attributes": {
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             "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_I1": {
+        "w_lvds_rx_24_d1_SB_LUT4_I0_O_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 271, 278, 277, 55 ],
+          "bits": [ 362 ],
           "attributes": {
-            "force_downto": "00000000000000000000000000000001",
-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
           }
         },
-        "w_lvds_rx_24_d1_SB_LUT4_I2_O_SB_LUT4_I0_O": {
+        "w_lvds_rx_24_d1_SB_LUT4_I3_O": {
           "hide_name": 0,
-          "bits": [ 314, 272, 55 ],
+          "bits": [ 412, 410, 406, 404, 402, 400, 398, 396, 394, 392, 390, 388, 384, 382, 380, 378, 376, 374, 372, 370, 368, 366, 424, 422, 420, 418, 416, 414, 408, 386, 364, 361 ],
           "attributes": {
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-            "src": "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
+            "src": "top.v:272.12-281.5|lvds_rx.v:47.13-78.20|lvds_rx.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22"
           }
         },
         "w_rx_09_fifo_data": {
           "hide_name": 0,
-          "bits": [ 201, 199, 22, 23, 24, 25 ],
+          "bits": [ 301, 299, 22, 23, 24, 25 ],
           "attributes": {
-            "unused_bits": "4 5"
           }
         },
         "w_rx_09_fifo_empty": {
@@ -26262,70 +34814,91 @@
         },
         "w_rx_09_fifo_full": {
           "hide_name": 0,
-          "bits": [ 213 ],
+          "bits": [ 330 ],
           "attributes": {
             "src": "top.v:232.9-232.26"
           }
         },
         "w_rx_09_fifo_pull": {
           "hide_name": 0,
-          "bits": [ "0" ],
+          "bits": [ 108 ],
           "attributes": {
             "src": "top.v:237.9-237.26"
           }
         },
+        "w_rx_09_fifo_pulled_data": {
+          "hide_name": 0,
+          "bits": [ 68, 546, 547, 548, 549, 550, 96, 551, 552, 553, 554, 555, 556, 557, 91, 558, 531, 532, 533, 534, 535, 536, 97, 537, 538, 539, 540, 541, 542, 543, 92, 544 ],
+          "attributes": {
+            "src": "top.v:238.16-238.40"
+          }
+        },
         "w_rx_09_fifo_push": {
           "hide_name": 0,
-          "bits": [ 211 ],
+          "bits": [ 328 ],
           "attributes": {
             "src": "top.v:235.9-235.26"
           }
         },
         "w_rx_09_fifo_write_clk": {
           "hide_name": 0,
-          "bits": [ 169 ],
+          "bits": [ 220 ],
           "attributes": {
             "src": "top.v:234.9-234.31"
           }
         },
+        "w_rx_24_fifo_data": {
+          "hide_name": 0,
+          "bits": [ 413, 411, 407, 405, 403, 401, 399, 397, 395, 393, 391, 389, 385, 383, 381, 379, 377, 375, 373, 371, 369, 367, 425, 423, 421, 419, 417, 415, 409, 387, 365, 363 ],
+          "attributes": {
+            "src": "top.v:244.16-244.33"
+          }
+        },
         "w_rx_24_fifo_empty": {
           "hide_name": 0,
-          "bits": [ 367 ],
+          "bits": [ 66 ],
           "attributes": {
             "src": "top.v:241.9-241.27"
           }
         },
         "w_rx_24_fifo_full": {
           "hide_name": 0,
-          "bits": [ 269 ],
+          "bits": [ 444 ],
           "attributes": {
             "src": "top.v:240.9-240.26"
           }
         },
         "w_rx_24_fifo_pull": {
           "hide_name": 0,
-          "bits": [ "0" ],
+          "bits": [ 106 ],
           "attributes": {
             "src": "top.v:245.9-245.26"
           }
         },
+        "w_rx_24_fifo_pulled_data": {
+          "hide_name": 0,
+          "bits": [ 71, 683, 684, 685, 686, 687, 80, 688, 689, 690, 691, 692, 693, 694, 79, 695, 667, 668, 669, 670, 671, 672, 77, 673, 674, 675, 676, 677, 678, 679, 76, 680 ],
+          "attributes": {
+            "src": "top.v:246.16-246.40"
+          }
+        },
         "w_rx_24_fifo_push": {
           "hide_name": 0,
-          "bits": [ 268 ],
+          "bits": [ 443 ],
           "attributes": {
             "src": "top.v:243.9-243.26"
           }
         },
         "w_rx_24_fifo_write_clk": {
           "hide_name": 0,
-          "bits": [ 169 ],
+          "bits": [ 220 ],
           "attributes": {
             "src": "top.v:242.9-242.31"
           }
         },
         "w_rx_data": {
           "hide_name": 0,
-          "bits": [ 62, 59, 146, 144, 142, 140, 139, 136 ],
+          "bits": [ 115, 112, 196, 195, 194, 192, 190, 188 ],
           "attributes": {
             "src": "top.v:69.16-69.25"
           }
@@ -26346,21 +34919,21 @@
         },
         "w_smi_data_output": {
           "hide_name": 0,
-          "bits": [ 32, 192, 191, 190, 189, 188, 187, 186 ],
+          "bits": [ 32, 254, 253, 252, 251, 250, 249, 248 ],
           "attributes": {
             "src": "top.v:330.15-330.32"
           }
         },
         "w_smi_read_req": {
           "hide_name": 0,
-          "bits": [ "1" ],
+          "bits": [ 219 ],
           "attributes": {
             "src": "top.v:332.9-332.23"
           }
         },
         "w_smi_test": {
           "hide_name": 0,
-          "bits": [ "1" ],
+          "bits": [ "0" ],
           "attributes": {
             "src": "top.v:335.9-335.19"
           }
@@ -26381,27 +34954,27 @@
         },
         "w_soft_reset": {
           "hide_name": 0,
-          "bits": [ 55 ],
+          "bits": [ 104 ],
           "attributes": {
             "src": "top.v:75.16-75.28"
           }
         },
         "w_tx_data_io": {
           "hide_name": 0,
-          "bits": [ 134, 98, 110, 101, 105, 120, 125, 130 ],
+          "bits": [ 186, 148, 162, 151, 156, 169, 176, 181 ],
           "attributes": {
             "src": "top.v:78.16-78.28"
           }
         },
         "w_tx_data_smi": {
           "hide_name": 0,
-          "bits": [ 415, 414, 413, 412 ],
+          "bits": [ 795, 794, 793, 792 ],
           "attributes": {
           }
         },
         "w_tx_data_sys": {
           "hide_name": 0,
-          "bits": [ 574, "0", "0", "0", "0", "0", "0", "0" ],
+          "bits": [ 949, "0", "0", "0", "0", "0", "0", "0" ],
           "attributes": {
             "src": "top.v:77.16-77.29"
           }
diff --git a/firmware/top.v b/firmware/top.v
index 4bfe3ac..999a7ce 100644
--- a/firmware/top.v
+++ b/firmware/top.v
@@ -335,7 +335,7 @@ module top(
    wire w_smi_test;
 
    //assign w_smi_data_output = 8'b10100101;
-   assign w_smi_test = 1'b1;
+   assign w_smi_test = 1'b0;
    assign w_smi_addr = {i_smi_a3, i_smi_a2, i_smi_a1};
    assign io_smi_data = (w_smi_writing)?w_smi_data_output:1'bZ;
    assign w_smi_data_input = io_smi_data;
diff --git a/software/libcariboulite/src/caribou_smi/build/CMakeFiles/test_caribou_smi.dir/C.includecache b/software/libcariboulite/src/caribou_smi/build/CMakeFiles/test_caribou_smi.dir/C.includecache
index 6602ba2..94ce6fa 100644
--- a/software/libcariboulite/src/caribou_smi/build/CMakeFiles/test_caribou_smi.dir/C.includecache
+++ b/software/libcariboulite/src/caribou_smi/build/CMakeFiles/test_caribou_smi.dir/C.includecache
@@ -8,51 +8,19 @@
 
 ../../zf_log/zf_log.h
 
-/home/pi/projects/cariboulite/software/libcariboulite/src/caribou_smi/bcm2835_smi.h
-linux/ioctl.h
+/home/pi/projects/cariboulite/software/libcariboulite/src/caribou_smi/caribou_smi.h
+pthread.h
 -
 stdint.h
 -
-stdbool.h
--
-linux/dmaengine.h
--
-linux/of.h
--
-linux/semaphore.h
--
 
-/home/pi/projects/cariboulite/software/libcariboulite/src/caribou_smi/caribou_smi.c
+/home/pi/projects/cariboulite/software/libcariboulite/src/caribou_smi/test_caribou_smi.c
 zf_log/zf_log.h
 /home/pi/projects/cariboulite/software/libcariboulite/src/caribou_smi/zf_log/zf_log.h
-caribou_smi.h
-/home/pi/projects/cariboulite/software/libcariboulite/src/caribou_smi/caribou_smi.h
-bcm2835_smi.h
-/home/pi/projects/cariboulite/software/libcariboulite/src/caribou_smi/bcm2835_smi.h
-string.h
--
-fcntl.h
--
-stdint.h
--
 stdio.h
 -
-stdlib.h
--
-sys/ioctl.h
--
-sys/stat.h
--
-unistd.h
--
-sched.h
--
-pthread.h
--
-
-/home/pi/projects/cariboulite/software/libcariboulite/src/caribou_smi/caribou_smi.h
-pthread.h
--
 stdint.h
 -
+caribou_smi.h
+/home/pi/projects/cariboulite/software/libcariboulite/src/caribou_smi/caribou_smi.h
 
diff --git a/software/libcariboulite/src/caribou_smi/build/test_caribou_smi b/software/libcariboulite/src/caribou_smi/build/test_caribou_smi
index 2573980..3d8d185 100755
Binary files a/software/libcariboulite/src/caribou_smi/build/test_caribou_smi and b/software/libcariboulite/src/caribou_smi/build/test_caribou_smi differ
diff --git a/software/libcariboulite/src/caribou_smi/test_caribou_smi.c b/software/libcariboulite/src/caribou_smi/test_caribou_smi.c
index 89fbe97..e101908 100644
--- a/software/libcariboulite/src/caribou_smi/test_caribou_smi.c
+++ b/software/libcariboulite/src/caribou_smi/test_caribou_smi.c
@@ -10,17 +10,36 @@
 
 caribou_smi_st dev = {0};
 
-
-
 void caribou_smi_data_event(void *ctx, caribou_smi_stream_type_en type, caribou_smi_channel_en ch,
                             uint32_t byte_count, uint8_t *buffer, uint32_t buffer_len_bytes)
 {
+    static int c = 1;
+    static uint8_t last_byte = 0;
+    static int err_count = 0;
     switch(type)
     {
         //-------------------------------------------------------
         case caribou_smi_stream_type_read:
             {
-                ZF_LOGD("data event: stream channel %d, received %d bytes\n", ch, byte_count);
+                //ZF_LOGD("data event: stream channel %d, received %d bytes\n", ch, byte_count);
+                for (int i = 0; i< byte_count; i++)
+                {
+                    uint8_t dist = (uint8_t)(buffer[i] - last_byte);
+                    if ( dist > 1)
+                    {
+                        err_count ++;
+                        float bER = (float)(err_count) / (float)(c);
+                        printf("ERR > at %d, dist: %d, V: %d, bER: %.7f\n", c, dist, buffer[i], bER);
+                    }
+                    /*printf("CUR CHUNK >  %d %d %d %d ... %d %d %d %d\n", buffer[0],buffer[1],buffer[2],buffer[3],
+                                                                        buffer[byte_count-4],
+                                                                        buffer[byte_count-3],
+                                                                        buffer[byte_count-2],
+                                                                        buffer[byte_count-1]);
+                    */
+                    last_byte = buffer[i];
+                    c++;
+                }
             }
             break;