2021-06-13 11:45:08 +00:00
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#ifndef __CARIBOU_FPGA_H__
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#define __CARIBOU_FPGA_H__
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2021-09-09 19:51:58 +00:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2021-06-13 11:45:08 +00:00
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#include <stdio.h>
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#include <stdint.h>
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#include "io_utils/io_utils.h"
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#include "io_utils/io_utils_spi.h"
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#pragma pack(1)
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typedef struct
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{
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uint8_t sys_ver;
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uint8_t sys_manu_id;
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uint8_t sys_ctrl_mod_ver;
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uint8_t io_ctrl_mod_ver;
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uint8_t smi_ctrl_mod_ver;
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} caribou_fpga_versions_st;
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typedef enum
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{
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caribou_fpga_ec_okay = 0x00,
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caribou_fpga_ec_write_attempt_to_readonly = 0x01,
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} caribou_fpga_ec_en; // error codes
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typedef enum
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{
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caribou_fpga_io_ctrl_rfm_low_power = 0,
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caribou_fpga_io_ctrl_rfm_bypass = 1,
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caribou_fpga_io_ctrl_rfm_rx_lowpass = 2,
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caribou_fpga_io_ctrl_rfm_rx_hipass = 3,
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caribou_fpga_io_ctrl_rfm_tx_lowpass = 4,
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caribou_fpga_io_ctrl_rfm_tx_hipass = 5,
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} caribou_fpga_io_ctrl_rfm_en;
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typedef struct
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{
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2021-07-14 13:11:06 +00:00
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uint8_t mixer_en : 1; // LSB
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2021-06-13 11:45:08 +00:00
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uint8_t lna_rx_shdn : 1;
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uint8_t lna_tx_shdn : 1;
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uint8_t trvc2 : 1;
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uint8_t trvc1_b : 1;
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uint8_t trvc1 : 1;
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uint8_t rx_h_tx_l_b : 1;
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uint8_t rx_h_tx_l : 1; // MSB
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} caribou_fpga_rf_pin_st;
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2021-07-14 13:11:06 +00:00
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typedef struct
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{
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uint8_t rx_fifo_09_empty : 1; // LSB
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uint8_t rx_fifo_09_full : 1;
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uint8_t rx_fifo_24_empty : 1;
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uint8_t rx_fifo_24_full : 1;
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uint8_t res : 4; // MSB
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} caribou_fpga_smi_fifo_status_st;
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2021-06-13 11:45:08 +00:00
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#pragma pack()
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typedef struct
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{
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// pinout
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int reset_pin;
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int irq_pin;
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int cs_pin;
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// spi device
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int spi_dev;
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int spi_channel;
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// internal controls
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io_utils_spi_st* io_spi;
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int io_spi_handle;
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int initialized;
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} caribou_fpga_st;
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int caribou_fpga_init(caribou_fpga_st* dev, io_utils_spi_st* io_spi);
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int caribou_fpga_close(caribou_fpga_st* dev);
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2021-07-14 13:11:06 +00:00
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int caribou_fpga_soft_reset(caribou_fpga_st* dev);
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2021-06-13 11:45:08 +00:00
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// System Controller
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int caribou_fpga_get_versions (caribou_fpga_st* dev, caribou_fpga_versions_st *vers);
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int caribou_fpga_get_errors (caribou_fpga_st* dev, uint8_t *err_map);
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// I/O Controller
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int caribou_fpga_set_io_ctrl_mode (caribou_fpga_st* dev, uint8_t debug_mode, caribou_fpga_io_ctrl_rfm_en rfm);
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int caribou_fpga_get_io_ctrl_mode (caribou_fpga_st* dev, uint8_t *debug_mode, caribou_fpga_io_ctrl_rfm_en *rfm);
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int caribou_fpga_set_io_ctrl_dig (caribou_fpga_st* dev, int ldo, int led0, int led1);
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int caribou_fpga_get_io_ctrl_dig (caribou_fpga_st* dev, int *ldo, int *led0, int *led1, int *btn, int *cfg);
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int caribou_fpga_set_io_ctrl_pmod_dir (caribou_fpga_st* dev, uint8_t dir);
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int caribou_fpga_get_io_ctrl_pmod_dir (caribou_fpga_st* dev, uint8_t *dir);
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int caribou_fpga_set_io_ctrl_pmod_val (caribou_fpga_st* dev, uint8_t val);
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int caribou_fpga_get_io_ctrl_pmod_val (caribou_fpga_st* dev, uint8_t *val);
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int caribou_fpga_set_io_ctrl_rf_state (caribou_fpga_st* dev, caribou_fpga_rf_pin_st pins);
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int caribou_fpga_get_io_ctrl_rf_state (caribou_fpga_st* dev, caribou_fpga_rf_pin_st *pins);
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2021-07-14 13:11:06 +00:00
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int caribou_fpga_get_smi_ctrl_fifo_status (caribou_fpga_st* dev, caribou_fpga_smi_fifo_status_st *status);
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2021-09-09 19:51:58 +00:00
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#ifdef __cplusplus
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}
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#endif
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2021-06-13 11:45:08 +00:00
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#endif // __CARIBOU_FPGA_H__
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