kopia lustrzana https://github.com/c9/core
34 wiersze
830 B
VHDL
34 wiersze
830 B
VHDL
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library IEEE
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user IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity COUNT16 is
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port (
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cOut :out std_logic_vector(15 downto 0); -- counter output
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clkEn :in std_logic; -- count enable
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clk :in std_logic; -- clock input
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rst :in std_logic -- reset input
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);
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end entity;
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architecture count_rtl of COUNT16 is
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signal count :std_logic_vector (15 downto 0);
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begin
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process (clk, rst) begin
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if(rst = '1') then
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count <= (others=>'0');
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elsif(rising_edge(clk)) then
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if(clkEn = '1') then
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count <= count + 1;
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end if;
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end if;
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end process;
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cOut <= count;
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end architecture;
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