kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
546 wiersze
21 KiB
VHDL
546 wiersze
21 KiB
VHDL
-- (C) 2001-2018 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions and other
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-- software and tools, and its AMPP partner logic functions, and any output
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-- files from any of the foregoing (including device programming or simulation
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-- files), and any associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License Subscription
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-- Agreement, Intel FPGA IP License Agreement, or other applicable
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-- license agreement, including, without limitation, that your use is for the
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-- sole purpose of programming logic devices manufactured by Intel and sold by
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-- Intel or its authorized distributors. Please refer to the applicable
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-- agreement for further details.
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-------------------------------------------------------------------------
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-------------------------------------------------------------------------
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--
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-- Revision Control Information
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--
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-- $Revision: #1 $
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-- $Date: 2009/07/29 $
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-- Author : Boon Hong Oh
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--
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-- Project : Atlantic II Sink Interface with ready_latency=0
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--
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-- Description :
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--
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-- This interface is capable of handling single or multi channel streams as
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-- well as blocks of data. The at_sink_sop and at_sink_eop must be fed as
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-- described in the Atlantic II specification. The at_sink_error input is a 2-
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-- bit signal that complies with the PFC error format (by Kent Orthner). The
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-- error checking is extensively done, however the resulting information is
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-- still mapped on the available 3 error states as shown below.
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-- 00: no error
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-- 01: missing sop
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-- 10: missing eop
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-- 11: unexpected eop
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-- other types of errors also marked as 11.
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--
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-- ALTERA Confidential and Proprietary
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-- Copyright 2006 (c) Altera Corporation
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-- All rights reserved
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--
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-------------------------------------------------------------------------
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-------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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--use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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use work.auk_dspip_lib_pkg_hpfir.all;
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use work.auk_dspip_math_pkg_hpfir.all;
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library altera_mf;
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use altera_mf.altera_mf_components.all;
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entity auk_dspip_avalon_streaming_sink_hpfir is
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generic(
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WIDTH_g : integer := 24; -- DATA_PORT_COUNT * DATA_WIDTH
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DATA_WIDTH : integer := 8;
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DATA_PORT_COUNT : integer := 3;
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PACKET_SIZE_g : natural := 2
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--FIFO_DEPTH_g : natural := 8 --if PFC mode is selected, this generic
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--is used for passing the poly_factor.
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--MIN_DATA_COUNT_g : natural := 2;
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--PFC_MODE_g : boolean := false;
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--SOP_EOP_CALC_g : boolean := false; -- calculate sop and eop rather than
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-- reading value from fifo
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--FAMILY_g : string := "Stratix II";
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--MEM_TYPE_g : string := "Auto"
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);
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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----------------- DESIGN SIDE SIGNALS
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data : out std_logic_vector(WIDTH_g-1 downto 0);
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data_valid : out std_logic_vector(0 downto 0);
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sink_ready_ctrl : in std_logic; --the controller will tell
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--the interface whether
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--new input can be accepted.
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--sink_stall : out std_logic; --needs to stall the design
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--if no new data is coming
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packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
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--when any of these doesn't behave as
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--expected, the error is flagged.
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--send_sop : out std_logic; -- transmit SOP signal to the design.
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-- It only transmits the legal SOP.
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--send_eop : out std_logic; -- transmit EOP signal to the design.
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-- It only transmits the legal EOP.
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----------------- ATLANTIC SIDE SIGNALS
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at_sink_ready : out std_logic; --it will be '1' whenever the
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--sink_ready_ctrl signal is high.
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at_sink_valid : in std_logic;
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at_sink_data : in std_logic_vector(WIDTH_g-1 downto 0);
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at_sink_sop : in std_logic := '0';
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at_sink_eop : in std_logic := '0';
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at_sink_error : in std_logic_vector(1 downto 0) := "00" --it indicates
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--that there is an error in the packet.
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);
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end auk_dspip_avalon_streaming_sink_hpfir;
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-- hds interface_end
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architecture rtl of auk_dspip_avalon_streaming_sink_hpfir is
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type STATE_TYPE_t is (start, stall, run1, st_err, end1); -- stall,run_once,wait1,
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type OUT_STATE_TYPE_t is (normal, empty_and_not_ready, empty_and_ready);
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constant LOG2PACKET_SIZE_c : natural := log2_ceil_one(PACKET_SIZE_g);
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signal sink_state : STATE_TYPE_t;
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signal sink_next_state : STATE_TYPE_t;
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signal reset_count : std_logic;
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signal count_enable : std_logic;
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signal count : unsigned(LOG2PACKET_SIZE_c -1 downto 0);
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signal count_finished : boolean;
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signal at_sink_error_int : std_logic;
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signal packet_error_int : std_logic_vector (1 downto 0);
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signal packet_error_s : std_logic_vector(1 downto 0);
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signal at_sink_ready_s : std_logic;
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--signal reset : std_logic;
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signal max_reached : boolean; -- flag to show counter has reached max value
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-- component altera_avalon_sc_fifo is
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-- generic(
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-- SYMBOLS_PER_BEAT : integer := 1;
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-- BITS_PER_SYMBOL : integer := 8;
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-- FIFO_DEPTH : integer := 16;
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-- CHANNEL_WIDTH : integer := 0;
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-- ERROR_WIDTH : integer := 0;
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-- USE_PACKETS : integer := 0
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-- );
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-- port (
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-- -- inputs:
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-- signal clk : IN STD_LOGIC;
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-- signal in_data : IN STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0);
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-- signal in_valid : IN STD_LOGIC;
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-- signal in_startofpacket : IN STD_LOGIC;
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-- signal in_endofpacket : IN STD_LOGIC;
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-- signal out_ready : IN STD_LOGIC;
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-- signal reset : IN STD_LOGIC;
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--
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-- signal in_empty : IN STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0);
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-- signal in_error : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
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-- signal in_channel : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
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--
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-- signal csr_address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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-- signal csr_write : IN STD_LOGIC;
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-- signal csr_read : IN STD_LOGIC;
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-- signal csr_writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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--
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-- -- outputs:
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-- signal in_ready : OUT STD_LOGIC;
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-- signal out_data : OUT STD_LOGIC_VECTOR (DATA_WIDTH*DATA_PORT_COUNT-1 DOWNTO 0);
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-- signal out_valid : OUT STD_LOGIC;
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--
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-- signal out_empty : OUT STD_LOGIC_VECTOR (log2_ceil_one(DATA_PORT_COUNT)-1 DOWNTO 0);
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-- signal out_error : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
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-- signal out_channel : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
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-- );
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-- end component altera_avalon_sc_fifo;
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begin
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valid_generate_single : if PACKET_SIZE_g = 1 generate
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signal packet_error0 : std_logic;
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begin
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at_sink_error_int <= at_sink_error(0) when at_sink_valid = '1' else
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'0';
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packet_error_int <= '0' & packet_error0;
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packet_error0 <= '0' when at_sink_error_int = '0' and sink_next_state /= st_err else
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'1';
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sink_comb_update_1 : process (sink_state, at_sink_valid, at_sink_error_int, at_sink_ready_s)
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begin -- process sink_comb_update_1
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case sink_state is
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when start =>
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--fifo_wrreq <= '0';
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if at_sink_error_int = '1' then
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sink_next_state <= st_err;
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else
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if at_sink_ready_s = '0' and at_sink_valid = '0' then
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sink_next_state <= start;
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elsif at_sink_ready_s = '0' and at_sink_valid = '1' then
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sink_next_state <= start;
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elsif at_sink_ready_s = '1' and at_sink_valid = '0' then
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sink_next_state <= stall;
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elsif at_sink_ready_s = '1' and at_sink_valid = '1' then
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sink_next_state <= run1;
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else
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sink_next_state <= st_err;
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end if;
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end if;
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when stall =>
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--fifo_wrreq <= '0';
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if at_sink_error_int = '1' then
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sink_next_state <= st_err;
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else
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if at_sink_ready_s = '0' and at_sink_valid = '0' then
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sink_next_state <= start;
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elsif at_sink_ready_s = '0' and at_sink_valid = '1' then
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sink_next_state <= start;
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elsif at_sink_ready_s = '1' and at_sink_valid = '0' then
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sink_next_state <= stall;
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elsif at_sink_ready_s = '1' and at_sink_valid = '1' then
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sink_next_state <= run1;
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else
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sink_next_state <= st_err;
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end if;
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end if;
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when run1 =>
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--fifo_wrreq <= '1';
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if at_sink_error_int = '1' then
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sink_next_state <= st_err;
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else
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if at_sink_ready_s = '0' and at_sink_valid = '0' then
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sink_next_state <= start;
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elsif at_sink_ready_s = '0' and at_sink_valid = '1' then
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sink_next_state <= start;
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elsif at_sink_ready_s = '1' and at_sink_valid = '0' then
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sink_next_state <= stall;
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elsif at_sink_ready_s = '1' and at_sink_valid = '1' then
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sink_next_state <= run1;
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else
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sink_next_state <= st_err;
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end if;
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end if;
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when st_err =>
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--fifo_wrreq <= '0';
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if at_sink_error_int = '1' then
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sink_next_state <= st_err;
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else
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if at_sink_ready_s = '0' and at_sink_valid = '0' then
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sink_next_state <= start;
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elsif at_sink_ready_s = '0' and at_sink_valid = '1' then
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sink_next_state <= start;
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elsif at_sink_ready_s = '1' and at_sink_valid = '0' then
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sink_next_state <= stall;
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elsif at_sink_ready_s = '1' and at_sink_valid = '1' then
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sink_next_state <= run1;
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else
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sink_next_state <= st_err;
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end if;
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end if;
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when others =>
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sink_next_state <= st_err;
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--fifo_wrreq <= '0';
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end case;
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end process sink_comb_update_1;
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end generate valid_generate_single;
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valid_generate_mult : if PACKET_SIZE_g > 1 generate
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at_sink_error_int <= at_sink_error(1) or at_sink_error(0) when at_sink_valid = '1' else
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'0';
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count_enable <= '1' when (sink_next_state = run1 or sink_next_state = end1) else --
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--or sink_next_state = run_once) else
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'0';
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reset_count <= '1' when sink_next_state = st_err else
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'0';
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sink_comb_update_2 : process (sink_state, at_sink_ready_s, at_sink_valid,
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at_sink_error, at_sink_error_int, at_sink_sop,
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at_sink_eop, count, count_finished)
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begin -- process sink_comb_update_2
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case sink_state is
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when start =>
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--fifo_wrreq <= '0';
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if at_sink_error_int = '1' then
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sink_next_state <= st_err;
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packet_error_int <= at_sink_error;
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else
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if at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '1' then
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sink_next_state <= run1;
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packet_error_int <= "00";
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elsif (at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '0') then
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sink_next_state <= st_err;
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packet_error_int <= "01";
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else
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sink_next_state <= start;
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packet_error_int <= "00";
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end if;
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end if;
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when run1 =>
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--fifo_wrreq <= '1';
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if at_sink_error_int = '1' then
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sink_next_state <= st_err;
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packet_error_int <= at_sink_error;
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elsif at_sink_sop = '1' and at_sink_valid = '1' then
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sink_next_state <= st_err;
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packet_error_int <= "01";
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elsif (count_finished = false and at_sink_eop = '1' and at_sink_valid = '1') then
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sink_next_state <= st_err;
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packet_error_int <= "11";
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else
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if at_sink_eop = '0' and count_finished = false and at_sink_valid = '1' and at_sink_ready_s = '1' then
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sink_next_state <= run1;
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packet_error_int <= "00";
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elsif at_sink_eop = '1' and count_finished = true and at_sink_valid = '1' and at_sink_ready_s = '1' then
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sink_next_state <= end1;
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packet_error_int <= "00";
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elsif (count_finished = true and at_sink_valid = '0' and at_sink_ready_s = '1') or
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(at_sink_valid = '0' and at_sink_ready_s = '1') then
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sink_next_state <= stall;
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packet_error_int <= "00";
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elsif (count_finished = true and at_sink_ready_s = '0') or (at_sink_eop = '0' and at_sink_ready_s = '0') then
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sink_next_state <= stall; --wait1;
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packet_error_int <= "00";
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elsif (count_finished = true and at_sink_eop = '0' and at_sink_valid = '1' and at_sink_ready_s = '1') then
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sink_next_state <= st_err;
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packet_error_int <= "10";
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else
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sink_next_state <= st_err;
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packet_error_int <= "11";
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end if;
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end if;
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when stall =>
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--fifo_wrreq <= '0';
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if at_sink_error_int = '1' then
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sink_next_state <= st_err;
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packet_error_int <= at_sink_error;
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elsif at_sink_sop = '1' and at_sink_valid = '1' then
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sink_next_state <= st_err;
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packet_error_int <= "01";
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elsif (count_finished = false and at_sink_eop = '1' and at_sink_valid = '1') then
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sink_next_state <= st_err;
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packet_error_int <= "11";
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else
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if at_sink_eop = '0' and count_finished = false and at_sink_valid = '1' and at_sink_ready_s = '1' then --and at_sink_ready_int = '1' then
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sink_next_state <= run1;
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packet_error_int <= "00";
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elsif at_sink_eop = '1' and count_finished = true and at_sink_valid = '1' and at_sink_ready_s = '1' then
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sink_next_state <= end1;
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packet_error_int <= "00";
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elsif (count_finished = true and at_sink_valid = '0') or -- and at_sink_ready_s = '1') or
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(at_sink_valid = '0' and at_sink_ready_s = '1') then
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sink_next_state <= stall;
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packet_error_int <= "00";
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elsif (count_finished = true and at_sink_ready_s = '0') or (at_sink_eop = '0' and at_sink_ready_s = '0') then
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sink_next_state <= stall; --wait1;
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packet_error_int <= "00";
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elsif (count_finished = true and at_sink_eop = '0' and at_sink_valid = '1' and at_sink_ready_s = '1') then
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sink_next_state <= st_err;
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packet_error_int <= "10";
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else
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sink_next_state <= st_err;
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packet_error_int <= "11";
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end if;
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end if;
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when end1 =>
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--fifo_wrreq <= '1';
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if at_sink_error_int = '1' then
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sink_next_state <= st_err;
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packet_error_int <= at_sink_error;
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else
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if at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '1' then
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sink_next_state <= run1;
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packet_error_int <= "00";
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elsif (at_sink_valid = '1' and at_sink_sop = '0') then
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sink_next_state <= st_err;
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packet_error_int <= "01";
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else
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sink_next_state <= start;
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packet_error_int <= "00";
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end if;
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end if;
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when st_err =>
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--fifo_wrreq <= '0';
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if at_sink_error_int = '1' then
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sink_next_state <= st_err;
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packet_error_int <= at_sink_error;
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else
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if at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '1' then
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sink_next_state <= run1;
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packet_error_int <= "00";
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elsif (at_sink_ready_s = '1' and at_sink_valid = '1' and at_sink_sop = '0') then
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sink_next_state <= st_err;
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packet_error_int <= "01";
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else
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sink_next_state <= start;
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packet_error_int <= "00";
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end if;
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end if;
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when others => null;
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end case;
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end process sink_comb_update_2;
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counter : process (clk, reset_n)
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begin -- process counter
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if reset_n = '0' then
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count <= (others => '0');
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max_reached <= false;
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elsif clk'event and clk = '1' then -- rising clock edge
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if reset_count = '1' then
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count <= (others => '0');
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else
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if count_enable = '1' then
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if count = PACKET_SIZE_g-2 then
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max_reached <= true;
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else
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max_reached <= false;
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end if;
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if max_reached = false then
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count <= count + 1;
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else
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count <= (others => '0');
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end if;
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end if;
|
|
end if;
|
|
end if;
|
|
end process counter;
|
|
|
|
count_finished <= max_reached;
|
|
|
|
end generate valid_generate_mult;
|
|
|
|
sink_input_update : process (clk, reset_n)
|
|
begin -- process
|
|
if reset_n = '0' then
|
|
sink_state <= start;
|
|
elsif clk'event and clk = '1' then
|
|
sink_state <= sink_next_state;
|
|
end if;
|
|
end process sink_input_update;
|
|
|
|
-- sink_output_update : process (clk, reset_n)
|
|
-- begin -- process
|
|
-- if reset_n = '0' then
|
|
-- sink_out_state <= normal;
|
|
-- elsif clk'event and clk = '1' then
|
|
-- sink_out_state <= sink_out_next_state;
|
|
-- end if;
|
|
-- end process sink_output_update;
|
|
|
|
error_register : process (clk, reset_n)
|
|
begin -- process
|
|
if reset_n = '0' then
|
|
packet_error_s <= "00";
|
|
elsif clk'event and clk = '1' then
|
|
packet_error_s <= packet_error_int;
|
|
end if;
|
|
end process;
|
|
|
|
packet_error <= packet_error_s;
|
|
|
|
-----------------------------------------------------------------------------
|
|
-- This was included because the vho simulations of fifo produce 'X' in
|
|
-- reset whcih means that for the FFT, alll outputs go to X when sop = X
|
|
-----------------------------------------------------------------------------
|
|
--gen_calc_sop: if SOP_EOP_CALC_g = true generate
|
|
--
|
|
-- -- generate sop and eop separate
|
|
-- out_cnt_p : process (clk, reset)
|
|
-- begin -- process out_cnt_p
|
|
-- if reset = '1' then
|
|
-- fifo_rdreq_d <= '0';
|
|
-- out_cnt <= 0;
|
|
-- elsif rising_edge(clk) then
|
|
-- fifo_rdreq_d <= fifo_rdreq;
|
|
-- if fifo_rdreq = '1' then
|
|
-- if out_cnt < PACKET_SIZE_g - 1 then
|
|
-- out_cnt <= out_cnt + 1;
|
|
-- else
|
|
-- out_cnt <= 0;
|
|
-- end if;
|
|
-- end if;
|
|
-- end if;
|
|
-- end process out_cnt_p;
|
|
--
|
|
-- send_sop_eop_p : process (clk, reset)
|
|
-- begin -- process send_sop_eop_p
|
|
-- if reset = '1' then
|
|
-- send_sop_s <= '0';
|
|
-- send_eop_s <= '0';
|
|
-- elsif rising_edge(clk) then
|
|
-- if fifo_rdreq = '1' and sink_ready_ctrl = '1' then
|
|
-- send_sop_s <= '0';
|
|
-- send_eop_s <= '0';
|
|
-- if out_cnt = 0 then
|
|
-- send_sop_s <= '1';
|
|
-- end if;
|
|
-- if out_cnt = PACKET_SIZE_g - 1 then
|
|
-- send_eop_s <= '1';
|
|
-- end if;
|
|
-- end if;
|
|
-- end if;
|
|
-- end process send_sop_eop_p;
|
|
--
|
|
-- end generate gen_calc_sop;
|
|
|
|
|
|
|
|
--reset <= not reset_n;
|
|
at_sink_ready <= at_sink_ready_s;
|
|
at_sink_ready_s <= sink_ready_ctrl;
|
|
data <= at_sink_data;
|
|
data_valid(0) <= at_sink_valid;
|
|
|
|
-- sink_scfifo : altera_avalon_sc_fifo
|
|
-- generic map (
|
|
-- SYMBOLS_PER_BEAT => DATA_PORT_COUNT,
|
|
-- BITS_PER_SYMBOL => DATA_WIDTH,
|
|
-- FIFO_DEPTH => FIFO_DEPTH_g,
|
|
-- CHANNEL_WIDTH => 0,
|
|
-- ERROR_WIDTH => 0,
|
|
-- USE_PACKETS => 0)
|
|
-- port map (
|
|
-- clk => clk,
|
|
-- reset => reset,
|
|
-- in_ready => at_sink_ready_s,
|
|
-- in_data => at_sink_data,
|
|
-- in_valid => at_sink_valid,
|
|
-- in_startofpacket => '0',
|
|
-- in_endofpacket => '0',
|
|
-- out_ready => sink_ready_ctrl,
|
|
-- out_data => data,
|
|
-- out_valid => data_valid(0),
|
|
-- in_empty => (others => '0'),
|
|
-- in_error => (others => '0'),
|
|
-- in_channel => (others => '0'),
|
|
-- csr_address => (others => '0'),
|
|
-- csr_write => '0',
|
|
-- csr_read => '0',
|
|
-- csr_writedata => (others => '0'),
|
|
-- out_empty => open,
|
|
-- out_error => open,
|
|
-- out_channel => open);
|
|
|
|
end rtl;
|