kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
125 wiersze
4.5 KiB
Verilog
125 wiersze
4.5 KiB
Verilog
// megafunction wizard: %ALTIOBUF%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altiobuf_in
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// ============================================================
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// File Name: diffclock_buff.v
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// Megafunction Name(s):
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// altiobuf_in
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//
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// Simulation Library Files(s):
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// cycloneive
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 18.1.0 Build 625 09/12/2018 SJ Standard Edition
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// ************************************************************
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//Copyright (C) 2018 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details.
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//altiobuf_in CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone IV E" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 USE_DIFFERENTIAL_MODE="TRUE" USE_DYNAMIC_TERMINATION_CONTROL="FALSE" datain datain_b dataout
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//VERSION_BEGIN 18.1 cbx_altiobuf_in 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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//synthesis_resources = cycloneive_io_ibuf 1
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//synopsys translate_off
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`timescale 1 ps / 1 ps
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//synopsys translate_on
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module diffclock_buff_iobuf_in_k0j
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(
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datain,
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datain_b,
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dataout) ;
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input [0:0] datain;
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input [0:0] datain_b;
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output [0:0] dataout;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri0 [0:0] datain_b;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [0:0] wire_ibufa_o;
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cycloneive_io_ibuf ibufa_0
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(
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.i(datain),
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.ibar(datain_b),
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.o(wire_ibufa_o[0:0]));
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defparam
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ibufa_0.bus_hold = "false",
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ibufa_0.differential_mode = "true",
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ibufa_0.lpm_type = "cycloneive_io_ibuf";
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assign
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dataout = wire_ibufa_o;
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endmodule //diffclock_buff_iobuf_in_k0j
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//VALID FILE
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module diffclock_buff (
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datain,
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datain_b,
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dataout);
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input [0:0] datain;
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input [0:0] datain_b;
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output [0:0] dataout;
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wire [0:0] sub_wire0;
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wire [0:0] dataout = sub_wire0[0:0];
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diffclock_buff_iobuf_in_k0j diffclock_buff_iobuf_in_k0j_component (
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.datain (datain),
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.datain_b (datain_b),
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.dataout (sub_wire0));
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
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// Retrieval info: CONSTANT: number_of_channels NUMERIC "1"
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// Retrieval info: CONSTANT: use_differential_mode STRING "TRUE"
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// Retrieval info: CONSTANT: use_dynamic_termination_control STRING "FALSE"
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// Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"
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// Retrieval info: USED_PORT: datain_b 0 0 1 0 INPUT NODEFVAL "datain_b[0..0]"
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// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
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// Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0
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// Retrieval info: CONNECT: @datain_b 0 0 1 0 datain_b 0 0 1 0
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// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL diffclock_buff.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL diffclock_buff.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL diffclock_buff.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL diffclock_buff.bsf TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL diffclock_buff_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL diffclock_buff_bb.v FALSE
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// Retrieval info: LIB_FILE: cycloneive
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