kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
83 wiersze
2.9 KiB
Plaintext
83 wiersze
2.9 KiB
Plaintext
--lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_width=3 clock cnt_en q sclr updown
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--VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END
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-- Copyright (C) 2018 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details.
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FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad)
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WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT)
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RETURNS ( combout, cout);
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--synthesis_resources = lut 3 reg 3
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SUBDESIGN cntr_8a7
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(
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clock : input;
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cnt_en : input;
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q[2..0] : output;
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sclr : input;
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updown : input;
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)
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VARIABLE
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counter_comb_bita0 : cycloneive_lcell_comb
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WITH (
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LUT_MASK = "5A90",
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SUM_LUTC_INPUT = "cin"
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);
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counter_comb_bita1 : cycloneive_lcell_comb
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WITH (
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LUT_MASK = "5A90",
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SUM_LUTC_INPUT = "cin"
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);
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counter_comb_bita2 : cycloneive_lcell_comb
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WITH (
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LUT_MASK = "5A90",
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SUM_LUTC_INPUT = "cin"
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);
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counter_reg_bit[2..0] : dffeas;
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aclr_actual : WIRE;
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clk_en : NODE;
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data[2..0] : NODE;
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external_cin : WIRE;
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s_val[2..0] : WIRE;
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safe_q[2..0] : WIRE;
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sload : NODE;
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sset : NODE;
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updown_dir : WIRE;
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BEGIN
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counter_comb_bita[2..0].cin = ( counter_comb_bita[1..0].cout, external_cin);
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counter_comb_bita[2..0].dataa = ( counter_reg_bit[2..0].q);
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counter_comb_bita[2..0].datab = ( updown_dir, updown_dir, updown_dir);
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counter_comb_bita[2..0].datad = ( B"1", B"1", B"1");
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counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[])));
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counter_reg_bit[].clk = clock;
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counter_reg_bit[].clrn = (! aclr_actual);
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counter_reg_bit[].d = ( counter_comb_bita[2..0].combout);
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counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en));
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counter_reg_bit[].sload = ((sclr # sset) # sload);
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aclr_actual = B"0";
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clk_en = VCC;
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data[] = GND;
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external_cin = B"1";
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q[] = safe_q[];
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s_val[] = B"111";
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safe_q[] = counter_reg_bit[].q;
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sload = GND;
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sset = GND;
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updown_dir = updown;
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END;
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--VALID FILE
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