kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
46 wiersze
1.8 KiB
Plaintext
46 wiersze
1.8 KiB
Plaintext
--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=22 aclr clken clock dataa datab result
|
|
--VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END
|
|
|
|
|
|
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
|
|
-- Your use of Intel Corporation's design tools, logic functions
|
|
-- and other software and tools, and its AMPP partner logic
|
|
-- functions, and any output files from any of the foregoing
|
|
-- (including device programming or simulation files), and any
|
|
-- associated documentation or information are expressly subject
|
|
-- to the terms and conditions of the Intel Program License
|
|
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
-- the Intel FPGA IP License Agreement, or other applicable license
|
|
-- agreement, including, without limitation, that your use is for
|
|
-- the sole purpose of programming logic devices manufactured by
|
|
-- Intel and sold by Intel or its authorized distributors. Please
|
|
-- refer to the applicable agreement for further details.
|
|
|
|
|
|
|
|
--synthesis_resources = lut 22
|
|
SUBDESIGN add_sub_u4i
|
|
(
|
|
aclr : input;
|
|
clken : input;
|
|
clock : input;
|
|
dataa[21..0] : input;
|
|
datab[21..0] : input;
|
|
result[21..0] : output;
|
|
)
|
|
VARIABLE
|
|
pipeline_dffe[21..0] : DFFE
|
|
WITH (
|
|
power_up ="low"
|
|
);
|
|
result_int[21..0] : WIRE;
|
|
BEGIN
|
|
result_int[] = dataa[] + datab[];
|
|
pipeline_dffe[].clk = clock;
|
|
pipeline_dffe[].clrn = !aclr;
|
|
pipeline_dffe[].ena = clken;
|
|
result[] = pipeline_dffe[21..0].q;
|
|
pipeline_dffe[21..0].d = result_int[];
|
|
END;
|
|
--VALID FILE
|