kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
274 wiersze
10 KiB
VHDL
274 wiersze
10 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.auk_dspip_lib_pkg_hpfir.all;
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use work.auk_dspip_math_pkg_hpfir.all;
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entity rx_ciccomp_ast is
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generic (
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INWIDTH : integer := 32;
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OUT_WIDTH_UNTRIMMED : integer := 46;
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BANKINWIDTH : integer := 0;
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REM_LSB_BIT_g : integer := 0;
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REM_LSB_TYPE_g : string := "round";
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REM_MSB_BIT_g : integer := 0;
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REM_MSB_TYPE_g : string := "trunc";
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PHYSCHANIN : integer := 1;
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PHYSCHANOUT : integer := 1;
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CHANSPERPHYIN : natural := 1;
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CHANSPERPHYOUT : natural := 1;
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OUTPUTFIFODEPTH : integer := 4;
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USE_PACKETS : integer := 0;
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MODE_WIDTH : integer := 0;
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ENABLE_BACKPRESSURE : boolean := false;
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LOG2_CHANSPERPHYOUT : natural := log2_ceil_one(1);
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NUMCHANS : integer := 1;
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DEVICE_FAMILY : string := "Cyclone IV E";
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COMPLEX_CONST : integer := 1
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);
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port(
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clk : in std_logic;
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reset_n : in std_logic;
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ast_sink_ready : out std_logic;
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ast_source_data : out std_logic_vector(COMPLEX_CONST*(OUT_WIDTH_UNTRIMMED - REM_LSB_BIT_g - REM_MSB_BIT_g) * PHYSCHANOUT - 1 downto 0);
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ast_sink_data : in std_logic_vector( COMPLEX_CONST*(INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH - 1 downto 0);
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ast_sink_valid : in std_logic;
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ast_source_valid : out std_logic;
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ast_source_ready : in std_logic;
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ast_source_eop : out std_logic;
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ast_source_sop : out std_logic;
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ast_source_channel : out std_logic_vector (LOG2_CHANSPERPHYOUT - 1 downto 0);
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ast_sink_eop : in std_logic;
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ast_sink_sop : in std_logic;
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ast_sink_error : in std_logic_vector (1 downto 0);
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ast_source_error : out std_logic_vector (1 downto 0)
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);
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attribute altera_attribute : string;
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attribute altera_attribute of rx_ciccomp_ast:entity is "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 10036";
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end rx_ciccomp_ast;
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-- Warnings Suppression On
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-- altera message_off 10036
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architecture struct of rx_ciccomp_ast is
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constant OUTWIDTH : integer := OUT_WIDTH_UNTRIMMED - REM_LSB_BIT_g - REM_MSB_BIT_g;
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signal channel_out : std_logic_vector(LOG2_CHANSPERPHYOUT - 1 downto 0);
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signal core_channel_out : std_logic_vector(2 -1 downto 0);
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signal at_source_channel : std_logic_vector(2 -1 downto 0);
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signal sink_packet_error : std_logic_vector(1 downto 0);
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signal data_in : std_logic_vector((COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH - 1 downto 0);
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signal data_valid : std_logic_vector(0 downto 0);
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signal data_out : std_logic_vector(COMPLEX_CONST*OUTWIDTH * PHYSCHANOUT -1 downto 0);
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signal reset_fir : std_logic;
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signal sink_ready_ctrl : std_logic;
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signal source_packet_error : std_logic_vector(1 downto 0);
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signal source_stall : std_logic;
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signal source_valid_ctrl : std_logic;
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signal stall : std_logic;
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signal valid : std_logic;
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signal core_valid : std_logic;
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signal enable_in : std_logic_vector(0 downto 0);
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signal outp_out : std_logic_vector(COMPLEX_CONST*OUTWIDTH * PHYSCHANOUT - 1 downto 0);
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signal outp_blk_valid : std_logic_vector(PHYSCHANOUT - 1 downto 0);
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signal core_out : std_logic_vector(OUT_WIDTH_UNTRIMMED * PHYSCHANOUT - 1 downto 0);
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signal core_out_valid : std_logic_vector(0 downto 0);
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signal core_out_channel : std_logic_vector(7 downto 0);
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signal core_out_channel_0 : std_logic_vector(7 downto 0);
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begin
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sink : auk_dspip_avalon_streaming_sink_hpfir
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generic map (
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WIDTH_g => (COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH,
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DATA_WIDTH => (COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH,
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DATA_PORT_COUNT => 1,
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PACKET_SIZE_g => CHANSPERPHYIN)
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port map (
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clk => clk,
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reset_n => reset_n,
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data => data_in,
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data_valid => data_valid,
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sink_ready_ctrl => sink_ready_ctrl,
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packet_error => sink_packet_error,
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at_sink_ready => ast_sink_ready,
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at_sink_valid => ast_sink_valid,
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at_sink_data => ast_sink_data,
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at_sink_sop => ast_sink_sop,
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at_sink_eop => ast_sink_eop,
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at_sink_error => ast_sink_error);
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source : auk_dspip_avalon_streaming_source_hpfir
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generic map (
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WIDTH_g => COMPLEX_CONST*OUTWIDTH * PHYSCHANOUT,
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DATA_WIDTH => COMPLEX_CONST*OUTWIDTH,
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DATA_PORT_COUNT => PHYSCHANOUT,
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FIFO_DEPTH_g => OUTPUTFIFODEPTH,
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USE_PACKETS => USE_PACKETS,
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HAVE_COUNTER_g => false,
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PACKET_SIZE_g => CHANSPERPHYOUT,
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COUNTER_LIMIT_g => CHANSPERPHYOUT,
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ENABLE_BACKPRESSURE_g => ENABLE_BACKPRESSURE)
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port map (
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clk => clk,
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reset_n => reset_n,
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data_in => data_out,
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data_count => channel_out,
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source_valid_ctrl => source_valid_ctrl,
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source_stall => source_stall,
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packet_error => source_packet_error,
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at_source_ready => ast_source_ready,
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at_source_valid => ast_source_valid,
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at_source_data => ast_source_data,
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at_source_channel => ast_source_channel,
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at_source_sop => ast_source_sop,
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at_source_eop => ast_source_eop,
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at_source_error => ast_source_error);
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intf_ctrl : auk_dspip_avalon_streaming_controller_hpfir
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port map (
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clk => clk,
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reset_n => reset_n,
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sink_packet_error => sink_packet_error,
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source_stall => source_stall,
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valid => valid,
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reset_design => reset_fir,
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sink_ready_ctrl => sink_ready_ctrl,
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source_packet_error => source_packet_error,
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source_valid_ctrl => source_valid_ctrl,
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stall => stall);
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multi_data_out: for m in PHYSCHANOUT-1 downto 0 generate
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data_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH)) <= outp_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH));
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end generate multi_data_out;
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channel_pipe_lsb: if REM_LSB_TYPE_g = "round" and REM_LSB_BIT_g > 0 generate
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begin
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out_lsb_p : process (clk, reset_n)
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begin
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if reset_n = '0' then
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core_out_channel_0 <= (others => '0');
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elsif rising_edge(clk) then
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core_out_channel_0 <= core_out_channel;
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end if;
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end process out_lsb_p;
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end generate channel_pipe_lsb;
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channel_wire_lsb: if REM_LSB_TYPE_g = "trunc" or REM_LSB_BIT_g = 0 generate
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begin
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core_out_channel_0 <= core_out_channel;
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end generate channel_wire_lsb;
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channel_pipe_msb: if REM_MSB_TYPE_g = "sat" and REM_MSB_BIT_g > 0 generate
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begin
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out_p : process (clk, reset_n)
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begin
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if reset_n = '0' then
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channel_out <= (others => '0');
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elsif rising_edge(clk) then
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channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0);
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end if;
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end process out_p;
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end generate channel_pipe_msb;
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channel_wire_msb: if REM_MSB_TYPE_g = "trunc" or REM_MSB_BIT_g = 0 generate
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begin
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channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0);
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end generate channel_wire_msb;
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real_passthrough : if COMPLEX_CONST = 1 generate
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component rx_ciccomp_rtl_core is
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port (
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xIn_v : in std_logic_vector(0 downto 0);
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xIn_c : in std_logic_vector(7 downto 0);
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xIn_0 : in std_logic_vector(32 - 1 downto 0);
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xOut_v : out std_logic_vector(0 downto 0);
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xOut_c : out std_logic_vector(7 downto 0);
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xOut_0 : out std_logic_vector(46- 1 downto 0);
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clk : in std_logic;
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areset : in std_logic
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);
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end component rx_ciccomp_rtl_core;
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--Complex data re-ordering
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signal core_channel_out_core : std_logic_vector(2 -1 downto 0);
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signal data_in_core : std_logic_vector((COMPLEX_CONST*INWIDTH + BANKINWIDTH) * PHYSCHANIN + MODE_WIDTH - 1 downto 0);
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signal data_valid_core : std_logic_vector(0 downto 0);
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signal core_out_core : std_logic_vector(OUT_WIDTH_UNTRIMMED * PHYSCHANOUT - 1 downto 0);
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signal core_out_valid_core : std_logic_vector(0 downto 0);
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signal core_out_channel_core : std_logic_vector(7 downto 0);
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begin
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hpfircore_core: rx_ciccomp_rtl_core
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port map (
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xIn_v => data_valid_core,
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xIn_c => "00000000",
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xIn_0 => data_in_core((0 + 32) * 0 + 32 - 1 downto (0 + 32) * 0),
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xOut_v => core_out_valid_core,
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xOut_c => core_out_channel_core,
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xOut_0 => core_out_core(46* 0 + 46- 1 downto 46* 0),
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clk => clk,
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areset => reset_fir
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);
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core_channel_out <= core_channel_out_core;
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data_in_core <= data_in;
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data_valid_core <= data_valid;
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core_out <= core_out_core;
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core_out_valid(0) <= core_out_valid_core(0);
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core_out_channel <= core_out_channel_core;
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gen_outp_blk : for i in PHYSCHANOUT-1 downto 0 generate
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begin
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outp_blk : auk_dspip_roundsat_hpfir
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generic map (
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IN_WIDTH_g => OUT_WIDTH_UNTRIMMED ,
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REM_LSB_BIT_g => REM_LSB_BIT_g ,
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REM_LSB_TYPE_g => REM_LSB_TYPE_g ,
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REM_MSB_BIT_g => REM_MSB_BIT_g ,
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REM_MSB_TYPE_g => REM_MSB_TYPE_g
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)
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port map (
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clk => clk,
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reset_n => reset_n,
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enable => core_out_valid(0),
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datain => core_out(((i*OUT_WIDTH_UNTRIMMED)+OUT_WIDTH_UNTRIMMED-1) downto (i*OUT_WIDTH_UNTRIMMED)),
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valid => outp_blk_valid(i),
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dataout => outp_out(((i*OUTWIDTH)+OUTWIDTH-1) downto (i*OUTWIDTH))
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);
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end generate gen_outp_blk;
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end generate real_passthrough;
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valid <= outp_blk_valid(0);
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enable_in(0) <= not stall;
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end struct;
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