kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
371 wiersze
12 KiB
VHDL
371 wiersze
12 KiB
VHDL
-- (C) 2001-2018 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions and other
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-- software and tools, and its AMPP partner logic functions, and any output
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-- files from any of the foregoing (including device programming or simulation
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-- files), and any associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License Subscription
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-- Agreement, Intel FPGA IP License Agreement, or other applicable
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-- license agreement, including, without limitation, that your use is for the
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-- sole purpose of programming logic devices manufactured by Intel and sold by
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-- Intel or its authorized distributors. Please refer to the applicable
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-- agreement for further details.
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-- (C) 2001-2009 Altera Corporation. All rights reserved.
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-- Your use of Altera Corporation's design tools, logic functions and other
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-- software and tools, and its AMPP partner logic functions, and any output
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-- files any of the foregoing (including device programming or simulation
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-- files), and any associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License Subscription
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-- Agreement, Altera MegaCore Function License Agreement, or other applicable
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-- license agreement, including, without limitation, that your use is for the
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-- sole purpose of programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the applicable
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-- agreement for further details.
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-------------------------------------------------------------------------
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-------------------------------------------------------------------------
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--
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-- Revision Control Information
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--
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-- $Revision: #1 $
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-- $Date: 2009/07/29 $
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-- Check in by : $Author: max $
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-- Author : DSP_IP
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--
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-- Project : <project name>
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--
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-- Description :
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--
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-- Common functions for DSP_IP cores.
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--
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--
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-- ALTERA Confidential and Proprietary
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-- Copyright 2006 (c) Altera Corporation
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-- All rights reserved
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--
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-------------------------------------------------------------------------
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-------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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PACKAGE auk_dspip_math_pkg_hpfir IS
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-----------------------------------------------------------------------------
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-- NOTE that these log functions are not intended to synthesize directly
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-- into hardware, rather they are used to generate constants for
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-- synthesized hardware.
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-----------------------------------------------------------------------------
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---------------------------------------------------------------------------
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-- LOG2_CEIL Function.
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-- Effectively performs log2() followed by ceil()
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-- e.g. CEIL_LOG2(255) returns 8
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-- CEIL_LOG2(256) returns 8
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-- CEIL_LOG2(257) returns 9
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---------------------------------------------------------------------------
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function log2_ceil(arg : in integer) return integer;
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function log2_ceil_one(arg : in integer) return integer; -- log2_ceil(1)=0
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---------------------------------------------------------------------------
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-- LOG2_FLOOR Function.
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-- Effectively performs log2() followed by floor()
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-- e.g. CEIL_LOG2(255) returns 7
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-- CEIL_LOG2(256) returns 8
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-- CEIL_LOG2(257) returns 8
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---------------------------------------------------------------------------
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function log2_floor(arg : in integer) return integer;
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-----------------------------------------------------------------------------
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-- SIGN functions
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-----------------------------------------------------------------------------
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-- returns the sign bit of a vector
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function sign (arg : in signed) return std_logic;
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-- sign extends ARG to size SIZE.
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function sign_extend (arg : signed; size : positive) return signed;
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-- sign extend one bit
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function xt1 (arg : signed) return signed;
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---------------------------------------------------------------------------
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-- Arithmetic FUNCTIONs.
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---------------------------------------------------------------------------
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-- Check integer for odd-ness
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function is_odd(arg : integer) return boolean;
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-----------------------------------------------------------------------------
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-- Logical functions
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-----------------------------------------------------------------------------
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-- Result of and'ing all of the bits of the vector.
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function and_reduce(arg : std_logic_vector) return std_logic;
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function and_reduce(arg : unsigned) return std_logic;
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-- Result of or'ing all of the bits of the vector.
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function or_reduce(arg : std_logic_vector) return std_logic;
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function or_reduce(arg : unsigned) return std_logic;
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-- returns index+1 of the highest asserted bit.
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function highest_one(arg : unsigned) return natural;
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-- returns index+1 of the lowest asserted bit.
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function lowest_one(arg : unsigned) return natural;
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-- returns the count of number of ones.
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function count_ones(arg : unsigned) return natural;
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-- Bit reverse
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function bit_reverse(arg : unsigned) return unsigned;
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-- Invert the argument bitwise
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function invert(arg : unsigned) return unsigned;
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--Halve towards up
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function halve_ceil(arg:natural) return natural;
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function div_ceil(a:natural;b:natural) return natural;
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END PACKAGE auk_dspip_math_pkg_hpfir;
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package body auk_dspip_math_pkg_hpfir is
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---------------------------------------------------------------------------
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-- LOG2_CEIL Function.
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---------------------------------------------------------------------------
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function log2_ceil(arg : in integer) return integer is
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variable res : integer;
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begin
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res := 0;
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for i in 0 to 30 loop
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if (arg > (2**i)) then
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res := i+1;
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end if;
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end loop; -- i
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return res;
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end log2_ceil;
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---------------------------------------------------------------------------
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-- LOG2_CEIL_ONE Function.
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---------------------------------------------------------------------------
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function log2_ceil_one(arg : in integer) return integer is
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variable res : integer;
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begin
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res := 0;
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for i in 0 to 30 loop
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if (arg > (2**i)) then
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res := i+1;
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end if;
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end loop; -- i
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if res = 0 then
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res := 1;
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end if;
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return res;
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end log2_ceil_one;
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---------------------------------------------------------------------------
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-- LOG2_FLOOR Function.
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-----------------------------------------------------------------------------
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function log2_floor(arg : in integer) return integer is
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variable res : integer;
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begin
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res := 0;
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for i in 0 to 30 loop
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if (arg >= (2**i)) then
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res := i;
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end if;
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end loop; -- i
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return res;
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end log2_floor;
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-----------------------------------------------------------------------------
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-- SIGN Function
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-----------------------------------------------------------------------------
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function sign (arg : in signed) return std_logic is
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variable res : std_logic;
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begin
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res := arg(arg'left);
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return(res);
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end sign;
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-----------------------------------------------------------------------------
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-- SIGN_EXTEND Function
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-----------------------------------------------------------------------------
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function sign_extend (arg : signed; size : positive) return signed is
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variable res : signed(size-1 downto 0);
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begin
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if arg'length > size then
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assert arg'length < size report "WARNING, can't sign extend" severity warning;
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end if;
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for i in arg'length to size-1 loop
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res(i) := arg(arg'left);
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end loop; -- i
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res(arg'length-1 downto 0) := arg;
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return(res);
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end sign_extend;
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-----------------------------------------------------------------------------
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-- XT1 Function
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-----------------------------------------------------------------------------
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function xt1 (arg : signed) return signed is
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variable res : signed(arg'length downto 0);
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begin
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res := arg(arg'left) & arg;
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return(res);
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end xt1;
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-----------------------------------------------------------------------------
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-- IS_ODD Function
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-----------------------------------------------------------------------------
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function is_odd(arg : integer) return boolean is
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begin
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return ((arg mod 2) = 1);
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end is_odd;
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-----------------------------------------------------------------------------
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-- AND_REDUCE Function
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-----------------------------------------------------------------------------
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function and_reduce(arg : std_logic_vector) return std_logic is
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variable res : std_logic;
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begin
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res := '1';
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for i in arg'range loop
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res := res and arg(i);
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end loop;
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return res;
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end;
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function and_reduce(arg : unsigned) return std_logic is
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variable res : std_logic;
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begin
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res := '1';
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for i in arg'range loop
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res := res and arg(i);
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end loop;
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return res;
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end;
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-----------------------------------------------------------------------------
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-- OR_REDUCE Function
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-----------------------------------------------------------------------------
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function or_reduce(arg : unsigned) return std_logic is
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variable res : std_logic;
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begin
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res := '0';
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for i in arg'range loop
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res := res or arg(i);
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end loop;
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return res;
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end;
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function or_reduce(arg : std_logic_vector) return std_logic is
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variable res : std_logic;
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begin
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res := '0';
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for i in arg'range loop
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res := res or arg(i);
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end loop;
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return res;
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end;
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---------------------------------------------------------------------------
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-- HIGHEST_ONE Function.
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---------------------------------------------------------------------------
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-- Returns index+1 of the highest asserted bit, or 0 if no bit set.
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-- Vector is evaluated from left to right, not high to low!
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function highest_one(arg : unsigned) return natural is
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begin
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for i in arg'range loop
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if arg(i) = '1' then
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return i+1;
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end if;
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end loop;
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return 0;
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end;
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-----------------------------------------------------------------------------
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-- LOWEST_ONE Function
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-----------------------------------------------------------------------------
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-- Returns index+1 of the lowest asserted bit, or 0 if no bit set.
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-- Vector is evaluated from left to right, not high to low!
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function lowest_one(arg : unsigned) return natural is
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begin
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for i in 0 to arg'length-1 loop
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if (arg(i) = '1') then
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return(i+1);
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end if;
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end loop;
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return(0);
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end;
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-----------------------------------------------------------------------------
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-- COUNT_ONES
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---------------------------------------------------------------------------
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-- Returns the count of the number of ones.
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function count_ones(arg : unsigned) return natural is
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variable count : integer;
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begin
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count := 0;
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for i in 0 to arg'length-1 loop
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if (arg(i) = '1') then
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count := count + 1;
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end if;
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end loop;
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return count;
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end;
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-----------------------------------------------------------------------------
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-- BIT_REVERSE function
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-----------------------------------------------------------------------------
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function bit_reverse(arg : unsigned) return unsigned is
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variable res : unsigned(arg'range);
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begin
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for i in arg'range loop
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res(i) := arg(arg'high - i);
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end loop;
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return(res);
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end;
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-----------------------------------------------------------------------------
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-- INVERT Function
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-----------------------------------------------------------------------------
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function invert(arg : unsigned)
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return unsigned -- (word'high downto 0)
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is
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variable res : unsigned(arg'high downto 0);
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begin
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for i in arg'range loop
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res(i) := not arg(i);
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end loop;
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return (res);
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end invert;
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-----------------------------------------------------------------------------
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-- HALVE_CEIL Function
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-----------------------------------------------------------------------------
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function halve_ceil(arg : natural) return natural is
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variable res : natural;
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begin
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if is_odd(arg) then
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res := (arg+1)/2;
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else
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res := arg/2;
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end if;
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return (res);
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end halve_ceil;
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-------------------------------------------------------------------------------
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-- DIV_CEIL function
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-------------------------------------------------------------------------------
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function div_ceil(a : natural; b : natural) return natural is
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variable res : natural := a/b;
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begin
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if res*b /= a then
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res := res +1;
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end if;
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return res;
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end div_ceil;
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end package body auk_dspip_math_pkg_hpfir;
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