kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
29 wiersze
1.5 KiB
Groff
29 wiersze
1.5 KiB
Groff
Info: Starting: Create block symbol file (.bsf)
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Info: qsys-generate D:\Dropbox\Develop\Projects\UA3REO\FPGA\DEBUG2.qsys --block-symbol-file --output-directory=D:\Dropbox\Develop\Projects\UA3REO\FPGA\DEBUG2 --family="Cyclone IV E" --part=EP4CE22E22C8
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Progress: Loading FPGA/DEBUG2.qsys
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Progress: Reading input file
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Progress: Adding in_system_sources_probes_0 [altera_in_system_sources_probes 18.1]
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Progress: Parameterizing module in_system_sources_probes_0
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Info: qsys-generate succeeded.
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Info: Finished: Create block symbol file (.bsf)
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Info:
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Info: Starting: Create HDL design files for synthesis
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Info: qsys-generate D:\Dropbox\Develop\Projects\UA3REO\FPGA\DEBUG2.qsys --synthesis=VERILOG --output-directory=D:\Dropbox\Develop\Projects\UA3REO\FPGA\DEBUG2\synthesis --family="Cyclone IV E" --part=EP4CE22E22C8
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Progress: Loading FPGA/DEBUG2.qsys
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Progress: Reading input file
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Progress: Adding in_system_sources_probes_0 [altera_in_system_sources_probes 18.1]
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Progress: Parameterizing module in_system_sources_probes_0
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Info: DEBUG2: Generating DEBUG2 "DEBUG2" for QUARTUS_SYNTH
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Info: in_system_sources_probes_0: "DEBUG2" instantiated altera_in_system_sources_probes "in_system_sources_probes_0"
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Info: DEBUG2: Done "DEBUG2" with 2 modules, 2 files
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Info: qsys-generate succeeded.
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Info: Finished: Create HDL design files for synthesis
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