kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
41 wiersze
760 B
Verilog
41 wiersze
760 B
Verilog
module DAC_corrector(
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clk_in,
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DATA_IN,
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distance,
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DATA_OUT
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);
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parameter in_width = 32;
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parameter out_width = 14;
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input clk_in;
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input signed [31:0] DATA_IN;
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input unsigned [7:0] distance;
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output reg unsigned [13:0] DATA_OUT;
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reg signed [13:0] tmp=0;
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always @ (posedge clk_in)
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begin
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//получаем 14 бит
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if (distance<out_width)
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begin
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tmp[(out_width-1):0] = DATA_IN[(out_width-1):0];
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end
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if (distance>in_width)
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begin
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tmp[(out_width-1):0] = DATA_IN[(in_width-1) -: out_width];
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end
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else
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begin
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tmp[(out_width-1):0] = DATA_IN[(distance-1) -: out_width];
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end
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DATA_OUT[(out_width-1):0]={~tmp[(out_width-1)],tmp[(out_width-2):0]}; //инвертируем первый бит, получая unsigned из two's complement
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end
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endmodule
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