kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
610 wiersze
18 KiB
C
610 wiersze
18 KiB
C
#include "fpga.h"
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#include "main.h"
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#include "trx_manager.h"
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#include "rf_unit.h"
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// Public variables
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volatile uint32_t FPGA_samples = 0; // counter of the number of samples when exchanging with FPGA
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volatile bool FPGA_NeedSendParams = false; // flag of the need to send parameters to FPGA
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volatile bool FPGA_NeedGetParams = false; // flag of the need to get parameters from FPGA
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volatile bool FPGA_NeedRestart = true; // flag of necessity to restart FPGA modules
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volatile bool FPGA_Buffer_underrun = false; // flag of lack of data from FPGA
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uint_fast16_t FPGA_Audio_RXBuffer_Index = 0; // current index in FPGA buffers
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uint_fast16_t FPGA_Audio_TXBuffer_Index = 0; // current index in FPGA buffers
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bool FPGA_Audio_Buffer_State = true; // buffer state, half or full full true - compleate; false - half
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IRAM1 volatile float32_t FPGA_Audio_Buffer_RX_Q[FPGA_RX_IQ_BUFFER_SIZE] = {0}; // FPGA buffers
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IRAM1 volatile float32_t FPGA_Audio_Buffer_RX_I[FPGA_RX_IQ_BUFFER_SIZE] = {0};
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IRAM1 volatile float32_t FPGA_Audio_SendBuffer_Q[FPGA_TX_IQ_BUFFER_SIZE] = {0};
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IRAM1 volatile float32_t FPGA_Audio_SendBuffer_I[FPGA_TX_IQ_BUFFER_SIZE] = {0};
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// Private variables
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static GPIO_InitTypeDef FPGA_GPIO_InitStruct; // structure of GPIO ports
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static bool FPGA_bus_stop = false; // suspend the FPGA bus
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// Prototypes
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static inline void FPGA_clockFall(void); // remove CLK signal
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static inline void FPGA_clockRise(void); // raise the CLK signal
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static inline void FPGA_syncAndClockRiseFall(void); // raise CLK and SYNC signals, then release
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static void FPGA_fpgadata_sendiq(void); // send IQ data
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static void FPGA_fpgadata_getiq(void); // get IQ data
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static void FPGA_fpgadata_getparam(void); // get parameters
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static void FPGA_fpgadata_sendparam(void); // send parameters
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static void FPGA_setBusInput(void); // switch the bus to input
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static void FPGA_setBusOutput(void); // switch bus to pin
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// initialize exchange with FPGA
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void FPGA_Init(void)
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{
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FPGA_GPIO_InitStruct.Pin = FPGA_BUS_D0_Pin | FPGA_BUS_D1_Pin | FPGA_BUS_D2_Pin | FPGA_BUS_D3_Pin | FPGA_BUS_D4_Pin | FPGA_BUS_D5_Pin | FPGA_BUS_D6_Pin | FPGA_BUS_D7_Pin;
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FPGA_GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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FPGA_GPIO_InitStruct.Pull = GPIO_PULLUP;
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FPGA_GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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HAL_GPIO_Init(FPGA_BUS_D0_GPIO_Port, &FPGA_GPIO_InitStruct);
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FPGA_GPIO_InitStruct.Pin = FPGA_CLK_Pin | FPGA_SYNC_Pin;
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FPGA_GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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FPGA_GPIO_InitStruct.Pull = GPIO_PULLUP;
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FPGA_GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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HAL_GPIO_Init(FPGA_CLK_GPIO_Port, &FPGA_GPIO_InitStruct);
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FPGA_bus_stop = true;
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FPGA_setBusOutput();
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FPGA_writePacket(5); // RESET ON
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FPGA_syncAndClockRiseFall();
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HAL_Delay(100);
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FPGA_writePacket(6); // RESET OFF
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FPGA_syncAndClockRiseFall();
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FPGA_NeedRestart = false;
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FPGA_bus_stop = false;
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//test bus
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/*FPGA_setBusOutput();
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FPGA_writePacket(0);
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FPGA_syncAndClockRiseFall();
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for(uint8_t i = 0; i<8; i++)
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{
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FPGA_writePacket(1 << i);
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FPGA_clockRise();
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FPGA_writePacket(0);
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FPGA_clockFall();
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sendToDebug_uint8(FPGA_readPacket,false);
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}*/
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}
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// restart FPGA modules
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void FPGA_restart(void) // restart FPGA modules
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{
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static bool FPGA_restart_state = false;
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if(!FPGA_restart_state)
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{
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FPGA_setBusOutput();
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FPGA_writePacket(5); // RESET ON
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FPGA_syncAndClockRiseFall();
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}
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else
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{
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FPGA_writePacket(6); // RESET OFF
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FPGA_syncAndClockRiseFall();
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FPGA_NeedRestart = false;
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}
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FPGA_restart_state = !FPGA_restart_state;
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}
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// exchange parameters with FPGA
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void FPGA_fpgadata_stuffclock(void)
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{
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if (!FPGA_NeedSendParams && !FPGA_NeedGetParams && !FPGA_NeedRestart)
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return;
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if (FPGA_bus_stop)
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return;
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uint8_t FPGA_fpgadata_out_tmp8 = 0;
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//data exchange
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//STAGE 1
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//out
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if (FPGA_NeedSendParams) //send params
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FPGA_fpgadata_out_tmp8 = 1;
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else //get params
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FPGA_fpgadata_out_tmp8 = 2;
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FPGA_setBusOutput();
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FPGA_writePacket(FPGA_fpgadata_out_tmp8);
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FPGA_syncAndClockRiseFall();
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if (FPGA_NeedSendParams)
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{
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FPGA_fpgadata_sendparam();
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FPGA_NeedSendParams = false;
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}
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else if (FPGA_NeedGetParams)
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{
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FPGA_fpgadata_getparam();
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FPGA_NeedGetParams = false;
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}
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else if (FPGA_NeedRestart)
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{
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FPGA_restart();
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}
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}
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// exchange IQ data with FPGA
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void FPGA_fpgadata_iqclock(void)
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{
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if (FPGA_bus_stop)
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return;
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uint8_t FPGA_fpgadata_out_tmp8 = 4; //RX
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VFO *current_vfo = CurrentVFO();
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if (current_vfo->Mode == TRX_MODE_LOOPBACK)
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return;
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//data exchange
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//STAGE 1
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//out
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if (TRX_on_TX())
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FPGA_fpgadata_out_tmp8 = 3; //TX
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FPGA_setBusOutput();
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FPGA_writePacket(FPGA_fpgadata_out_tmp8);
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FPGA_syncAndClockRiseFall();
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if (TRX_on_TX())
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FPGA_fpgadata_sendiq();
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else
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FPGA_fpgadata_getiq();
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}
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// send parameters
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static inline void FPGA_fpgadata_sendparam(void)
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{
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uint8_t FPGA_fpgadata_out_tmp8 = 0;
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VFO *current_vfo = CurrentVFO();
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//STAGE 2
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//out PTT+PREAMP
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uint8_t att_val = (uint8_t)TRX.ATT_DB;
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bitWrite(FPGA_fpgadata_out_tmp8, 0, (!TRX_on_TX() && current_vfo->Mode != TRX_MODE_LOOPBACK)); //RX
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bitWrite(FPGA_fpgadata_out_tmp8, 1, TRX.ADC_Driver);
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if(TRX.ATT)
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{
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bitWrite(FPGA_fpgadata_out_tmp8, 2, 0); //att0.5
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bitWrite(FPGA_fpgadata_out_tmp8, 3, (att_val >> 0) & 0x1); //att1
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bitWrite(FPGA_fpgadata_out_tmp8, 4, (att_val >> 1) & 0x1); //att2
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bitWrite(FPGA_fpgadata_out_tmp8, 5, (att_val >> 2) & 0x1); //att4
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bitWrite(FPGA_fpgadata_out_tmp8, 6, (att_val >> 3) & 0x1); //att8
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bitWrite(FPGA_fpgadata_out_tmp8, 7, (att_val >> 4) & 0x1); //att16
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}
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FPGA_writePacket(FPGA_fpgadata_out_tmp8);
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FPGA_clockRise();
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FPGA_clockFall();
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//STAGE 3
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//out RX1-FREQ
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FPGA_writePacket(((TRX_freq_phrase & (0XFF << 16)) >> 16));
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FPGA_clockRise();
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FPGA_clockFall();
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//STAGE 4
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//OUT RX1-FREQ
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FPGA_writePacket(((TRX_freq_phrase & (0XFF << 8)) >> 8));
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FPGA_clockRise();
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FPGA_clockFall();
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//STAGE 5
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//OUT RX1-FREQ
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FPGA_writePacket(TRX_freq_phrase & 0XFF);
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FPGA_clockRise();
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FPGA_clockFall();
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//STAGE 9
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//OUT CIC-GAIN
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FPGA_writePacket(CALIBRATE.CIC_GAINER_val);
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FPGA_clockRise();
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FPGA_clockFall();
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//STAGE 10
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//OUT CICCOMP-GAIN
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FPGA_writePacket(CALIBRATE.CICFIR_GAINER_val);
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FPGA_clockRise();
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FPGA_clockFall();
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//STAGE 11
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//OUT TX-CICCOMP-GAIN
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FPGA_writePacket(CALIBRATE.TXCICFIR_GAINER_val);
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FPGA_clockRise();
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FPGA_clockFall();
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//STAGE 12
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//OUT DAC-GAIN
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FPGA_writePacket(CALIBRATE.DAC_GAINER_val);
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FPGA_clockRise();
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FPGA_clockFall();
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//STAGE 13
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//out TX-FREQ
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FPGA_writePacket(((TRX_freq_phrase_tx & (0XFF << 16)) >> 16));
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FPGA_clockRise();
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FPGA_clockFall();
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//STAGE 14
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//OUT TX-FREQ
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FPGA_writePacket(((TRX_freq_phrase_tx & (0XFF << 8)) >> 8));
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FPGA_clockRise();
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FPGA_clockFall();
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//STAGE 15
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//OUT TX-FREQ
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FPGA_writePacket(TRX_freq_phrase_tx & 0XFF);
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FPGA_clockRise();
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FPGA_clockFall();
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//STAGE 16
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//out BPF
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FPGA_fpgadata_out_tmp8 = 0;
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if(CurrentVFO()->Freq >= 1500000 && CurrentVFO()->Freq <= 2400000) //160m
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{
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bitWrite(FPGA_fpgadata_out_tmp8, 0, 0); //BPF_A
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bitWrite(FPGA_fpgadata_out_tmp8, 1, 0); //BPF_B
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bitWrite(FPGA_fpgadata_out_tmp8, 3, 1); //BPF_OE1
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bitWrite(FPGA_fpgadata_out_tmp8, 2, 0); //BPF_OE2
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bitWrite(FPGA_fpgadata_out_tmp8, 4, 0); //LPF1
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bitWrite(FPGA_fpgadata_out_tmp8, 5, 0); //LPF2
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bitWrite(FPGA_fpgadata_out_tmp8, 6, 0); //LPF3
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}
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else if(CurrentVFO()->Freq >= 2400000 && CurrentVFO()->Freq <= 4500000) //80m
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{
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bitWrite(FPGA_fpgadata_out_tmp8, 0, 1); //BPF_A
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bitWrite(FPGA_fpgadata_out_tmp8, 1, 0); //BPF_B
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bitWrite(FPGA_fpgadata_out_tmp8, 3, 1); //BPF_OE1
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bitWrite(FPGA_fpgadata_out_tmp8, 2, 0); //BPF_OE2
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bitWrite(FPGA_fpgadata_out_tmp8, 4, 1); //LPF1
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bitWrite(FPGA_fpgadata_out_tmp8, 5, 0); //LPF2
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bitWrite(FPGA_fpgadata_out_tmp8, 6, 0); //LPF3
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}
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else if(CurrentVFO()->Freq >= 4500000 && CurrentVFO()->Freq <= 7500000) //40m
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{
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bitWrite(FPGA_fpgadata_out_tmp8, 0, 0); //BPF_A
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bitWrite(FPGA_fpgadata_out_tmp8, 1, 1); //BPF_B
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bitWrite(FPGA_fpgadata_out_tmp8, 3, 1); //BPF_OE1
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bitWrite(FPGA_fpgadata_out_tmp8, 2, 0); //BPF_OE2
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bitWrite(FPGA_fpgadata_out_tmp8, 4, 0); //LPF1
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bitWrite(FPGA_fpgadata_out_tmp8, 5, 1); //LPF2
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bitWrite(FPGA_fpgadata_out_tmp8, 6, 0); //LPF3
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}
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else if(CurrentVFO()->Freq >= 7500000 && CurrentVFO()->Freq <= 12000000) //30m
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{
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bitWrite(FPGA_fpgadata_out_tmp8, 0, 1); //BPF_A
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bitWrite(FPGA_fpgadata_out_tmp8, 1, 1); //BPF_B
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bitWrite(FPGA_fpgadata_out_tmp8, 3, 1); //BPF_OE1
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bitWrite(FPGA_fpgadata_out_tmp8, 2, 0); //BPF_OE2
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bitWrite(FPGA_fpgadata_out_tmp8, 4, 1); //LPF1
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bitWrite(FPGA_fpgadata_out_tmp8, 5, 1); //LPF2
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bitWrite(FPGA_fpgadata_out_tmp8, 6, 0); //LPF3
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}
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else if(CurrentVFO()->Freq >= 12000000 && CurrentVFO()->Freq <= 14800000) //20m
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{
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bitWrite(FPGA_fpgadata_out_tmp8, 0, 0); //BPF_A
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bitWrite(FPGA_fpgadata_out_tmp8, 1, 0); //BPF_B
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bitWrite(FPGA_fpgadata_out_tmp8, 3, 0); //BPF_OE1
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bitWrite(FPGA_fpgadata_out_tmp8, 2, 1); //BPF_OE2
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bitWrite(FPGA_fpgadata_out_tmp8, 4, 0); //LPF1
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bitWrite(FPGA_fpgadata_out_tmp8, 5, 0); //LPF2
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bitWrite(FPGA_fpgadata_out_tmp8, 6, 1); //LPF3
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}
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else if(CurrentVFO()->Freq >= 14800000 && CurrentVFO()->Freq <= 22000000) //17,15m
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{
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bitWrite(FPGA_fpgadata_out_tmp8, 0, 1); //BPF_A
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bitWrite(FPGA_fpgadata_out_tmp8, 1, 0); //BPF_B
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bitWrite(FPGA_fpgadata_out_tmp8, 3, 0); //BPF_OE1
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bitWrite(FPGA_fpgadata_out_tmp8, 2, 1); //BPF_OE2
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bitWrite(FPGA_fpgadata_out_tmp8, 4, 1); //LPF1
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bitWrite(FPGA_fpgadata_out_tmp8, 5, 0); //LPF2
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bitWrite(FPGA_fpgadata_out_tmp8, 6, 1); //LPF3
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}
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else if(CurrentVFO()->Freq >= 22000000 && CurrentVFO()->Freq <= 32000000) //12,10m
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{
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bitWrite(FPGA_fpgadata_out_tmp8, 0, 0); //BPF_A
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bitWrite(FPGA_fpgadata_out_tmp8, 1, 1); //BPF_B
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bitWrite(FPGA_fpgadata_out_tmp8, 3, 0); //BPF_OE1
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bitWrite(FPGA_fpgadata_out_tmp8, 2, 1); //BPF_OE2
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bitWrite(FPGA_fpgadata_out_tmp8, 4, 0); //LPF1
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bitWrite(FPGA_fpgadata_out_tmp8, 5, 1); //LPF2
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bitWrite(FPGA_fpgadata_out_tmp8, 6, 1); //LPF3
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}
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else //if(CurrentVFO()->Freq >= 0 && CurrentVFO()->Freq <= 53000000) //6m
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{
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bitWrite(FPGA_fpgadata_out_tmp8, 0, 1); //BPF_A
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bitWrite(FPGA_fpgadata_out_tmp8, 1, 1); //BPF_B
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bitWrite(FPGA_fpgadata_out_tmp8, 3, 0); //BPF_OE1
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bitWrite(FPGA_fpgadata_out_tmp8, 2, 1); //BPF_OE2
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bitWrite(FPGA_fpgadata_out_tmp8, 4, 1); //LPF1
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bitWrite(FPGA_fpgadata_out_tmp8, 5, 1); //LPF2
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bitWrite(FPGA_fpgadata_out_tmp8, 6, 1); //LPF3
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}
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//bitWrite(FPGA_fpgadata_out_tmp8, 7, 0); //unused
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FPGA_writePacket(FPGA_fpgadata_out_tmp8);
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FPGA_clockRise();
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FPGA_clockFall();
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}
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// get parameters
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static inline void FPGA_fpgadata_getparam(void)
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{
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register uint8_t FPGA_fpgadata_in_tmp8 = 0;
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register int32_t FPGA_fpgadata_in_tmp32 = 0;
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FPGA_setBusInput();
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//STAGE 2
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FPGA_clockRise();
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FPGA_fpgadata_in_tmp8 = FPGA_readPacket;
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TRX_ADC_OTR = bitRead(FPGA_fpgadata_in_tmp8, 0);
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TRX_DAC_OTR = bitRead(FPGA_fpgadata_in_tmp8, 1);
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FPGA_clockFall();
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//STAGE 3
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FPGA_clockRise();
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FPGA_fpgadata_in_tmp8 = FPGA_readPacket;
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FPGA_clockFall();
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//STAGE 4
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FPGA_clockRise();
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TRX_ADC_MINAMPLITUDE = (int16_t)(((FPGA_fpgadata_in_tmp8 << 8) & 0xFF00) | FPGA_readPacket);
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bitWrite(TRX_ADC_MINAMPLITUDE, 15, bitRead(TRX_ADC_MINAMPLITUDE, 11)); //EXTEND 12 To 16 BITS
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bitWrite(TRX_ADC_MINAMPLITUDE, 14, bitRead(TRX_ADC_MINAMPLITUDE, 11));
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bitWrite(TRX_ADC_MINAMPLITUDE, 13, bitRead(TRX_ADC_MINAMPLITUDE, 11));
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bitWrite(TRX_ADC_MINAMPLITUDE, 12, bitRead(TRX_ADC_MINAMPLITUDE, 11));
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FPGA_clockFall();
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//STAGE 5
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FPGA_clockRise();
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FPGA_fpgadata_in_tmp8 = FPGA_readPacket;
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FPGA_clockFall();
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//STAGE 6
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FPGA_clockRise();
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TRX_ADC_MAXAMPLITUDE = (int16_t)(((FPGA_fpgadata_in_tmp8 << 8) & 0xFF00) | FPGA_readPacket);
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bitWrite(TRX_ADC_MAXAMPLITUDE, 15, bitRead(TRX_ADC_MAXAMPLITUDE, 11)); //EXTEND 12 To 16 BITS
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bitWrite(TRX_ADC_MAXAMPLITUDE, 14, bitRead(TRX_ADC_MAXAMPLITUDE, 11));
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bitWrite(TRX_ADC_MAXAMPLITUDE, 13, bitRead(TRX_ADC_MAXAMPLITUDE, 11));
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bitWrite(TRX_ADC_MAXAMPLITUDE, 12, bitRead(TRX_ADC_MAXAMPLITUDE, 11));
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FPGA_clockFall();
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}
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// get IQ data
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static inline void FPGA_fpgadata_getiq(void)
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{
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register int16_t FPGA_fpgadata_in_tmp16 = 0;
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float32_t* FFTInput_I_current = FFT_buff_current ? (float32_t*)&FFTInput_I_B : (float32_t*)&FFTInput_I_A;
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float32_t* FFTInput_Q_current = FFT_buff_current ? (float32_t*)&FFTInput_Q_B : (float32_t*)&FFTInput_Q_A;
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float32_t FPGA_fpgadata_in_float32 = 0;
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FPGA_samples++;
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FPGA_setBusInput();
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//Q RX
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//STAGE 2
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FPGA_clockRise();
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FPGA_fpgadata_in_tmp16 = (FPGA_readPacket << 8);
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FPGA_clockFall();
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//STAGE 3
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FPGA_clockRise();
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FPGA_fpgadata_in_tmp16 |= (FPGA_readPacket);
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/*static float32_t min = 0;
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static float32_t max = 0;
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if((float32_t)FPGA_fpgadata_in_tmp16 < min)
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min = (float32_t)FPGA_fpgadata_in_tmp16;
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if((float32_t)FPGA_fpgadata_in_tmp16 > max)
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max = (float32_t)FPGA_fpgadata_in_tmp16;
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if(FPGA_samples == 100)
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{
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sendToDebug_float32(min, false);
|
|
sendToDebug_float32(max, false);
|
|
sendToDebug_newline();
|
|
min = 0;
|
|
max = 0;
|
|
}*/
|
|
|
|
FPGA_fpgadata_in_float32 = (float32_t)FPGA_fpgadata_in_tmp16 / 32768.0f;
|
|
if (TRX_RX_IQ_swap)
|
|
{
|
|
FFTInput_I_current[FFT_buff_index] = FPGA_fpgadata_in_float32;
|
|
FPGA_Audio_Buffer_RX_I[FPGA_Audio_RXBuffer_Index] = FPGA_fpgadata_in_float32;
|
|
}
|
|
else
|
|
{
|
|
FFTInput_Q_current[FFT_buff_index] = FPGA_fpgadata_in_float32;
|
|
FPGA_Audio_Buffer_RX_Q[FPGA_Audio_RXBuffer_Index] = FPGA_fpgadata_in_float32;
|
|
}
|
|
FPGA_clockFall();
|
|
|
|
//I RX1
|
|
//STAGE 4
|
|
FPGA_clockRise();
|
|
FPGA_fpgadata_in_tmp16 = (FPGA_readPacket << 8);
|
|
FPGA_clockFall();
|
|
|
|
//STAGE 5
|
|
FPGA_clockRise();
|
|
FPGA_fpgadata_in_tmp16 |= (FPGA_readPacket);
|
|
|
|
FPGA_fpgadata_in_float32 = (float32_t)FPGA_fpgadata_in_tmp16 / 32768.0f;
|
|
if (TRX_RX_IQ_swap)
|
|
{
|
|
FFTInput_Q_current[FFT_buff_index] = FPGA_fpgadata_in_float32;
|
|
FPGA_Audio_Buffer_RX_Q[FPGA_Audio_RXBuffer_Index] = FPGA_fpgadata_in_float32;
|
|
}
|
|
else
|
|
{
|
|
FFTInput_I_current[FFT_buff_index] = FPGA_fpgadata_in_float32;
|
|
FPGA_Audio_Buffer_RX_I[FPGA_Audio_RXBuffer_Index] = FPGA_fpgadata_in_float32;
|
|
}
|
|
FPGA_clockFall();
|
|
|
|
FPGA_Audio_RXBuffer_Index++;
|
|
if (FPGA_Audio_RXBuffer_Index == FPGA_RX_IQ_BUFFER_SIZE)
|
|
FPGA_Audio_RXBuffer_Index = 0;
|
|
|
|
FFT_buff_index++;
|
|
if (FFT_buff_index >= FFT_SIZE)
|
|
{
|
|
FFT_buff_index = 0;
|
|
FFT_new_buffer_ready = true;
|
|
FFT_buff_current = !FFT_buff_current;
|
|
}
|
|
FPGA_clockFall();
|
|
}
|
|
|
|
// send IQ data
|
|
static inline void FPGA_fpgadata_sendiq(void)
|
|
{
|
|
q15_t FPGA_fpgadata_out_q_tmp16 = 0;
|
|
q15_t FPGA_fpgadata_out_i_tmp16 = 0;
|
|
q15_t FPGA_fpgadata_out_tmp_tmp16 = 0;
|
|
arm_float_to_q15((float32_t *)&FPGA_Audio_SendBuffer_Q[FPGA_Audio_TXBuffer_Index], &FPGA_fpgadata_out_q_tmp16, 1);
|
|
arm_float_to_q15((float32_t *)&FPGA_Audio_SendBuffer_I[FPGA_Audio_TXBuffer_Index], &FPGA_fpgadata_out_i_tmp16, 1);
|
|
FPGA_samples++;
|
|
|
|
if (TRX_TX_IQ_swap)
|
|
{
|
|
FPGA_fpgadata_out_tmp_tmp16 = FPGA_fpgadata_out_i_tmp16;
|
|
FPGA_fpgadata_out_i_tmp16 = FPGA_fpgadata_out_q_tmp16;
|
|
FPGA_fpgadata_out_q_tmp16 = FPGA_fpgadata_out_tmp_tmp16;
|
|
}
|
|
|
|
//out Q
|
|
//STAGE 2
|
|
FPGA_writePacket((FPGA_fpgadata_out_q_tmp16 >> 8) & 0xFF);
|
|
//clock
|
|
FPGA_clockRise();
|
|
//clock
|
|
FPGA_clockFall();
|
|
|
|
//STAGE 3
|
|
FPGA_writePacket((FPGA_fpgadata_out_q_tmp16 >> 0) & 0xFF);
|
|
//clock
|
|
FPGA_clockRise();
|
|
//clock
|
|
FPGA_clockFall();
|
|
|
|
//out I
|
|
//STAGE 4
|
|
FPGA_writePacket((FPGA_fpgadata_out_i_tmp16 >> 8) & 0xFF);
|
|
//clock
|
|
FPGA_clockRise();
|
|
//clock
|
|
FPGA_clockFall();
|
|
|
|
//STAGE 5
|
|
FPGA_writePacket((FPGA_fpgadata_out_i_tmp16 >> 0) & 0xFF);
|
|
//clock
|
|
FPGA_clockRise();
|
|
//clock
|
|
FPGA_clockFall();
|
|
|
|
FPGA_Audio_TXBuffer_Index++;
|
|
if (FPGA_Audio_TXBuffer_Index == FPGA_TX_IQ_BUFFER_SIZE)
|
|
{
|
|
if (Processor_NeedTXBuffer)
|
|
{
|
|
FPGA_Buffer_underrun = true;
|
|
FPGA_Audio_TXBuffer_Index--;
|
|
}
|
|
else
|
|
{
|
|
FPGA_Audio_TXBuffer_Index = 0;
|
|
FPGA_Audio_Buffer_State = true;
|
|
Processor_NeedTXBuffer = true;
|
|
}
|
|
}
|
|
else if (FPGA_Audio_TXBuffer_Index == FPGA_TX_IQ_BUFFER_HALF_SIZE)
|
|
{
|
|
if (Processor_NeedTXBuffer)
|
|
{
|
|
FPGA_Buffer_underrun = true;
|
|
FPGA_Audio_TXBuffer_Index--;
|
|
}
|
|
else
|
|
{
|
|
FPGA_Audio_Buffer_State = false;
|
|
Processor_NeedTXBuffer = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
// switch the bus to input
|
|
static inline void FPGA_setBusInput(void)
|
|
{
|
|
// Configure IO Direction mode (Input)
|
|
/*register uint32_t temp = GPIOA->MODER;
|
|
temp &= ~(GPIO_MODER_MODE0 << (0 * 2U));
|
|
temp |= ((GPIO_MODE_INPUT & 0x00000003U) << (0 * 2U));
|
|
temp &= ~(GPIO_MODER_MODE0 << (1 * 2U));
|
|
temp |= ((GPIO_MODE_INPUT & 0x00000003U) << (1 * 2U));
|
|
temp &= ~(GPIO_MODER_MODE0 << (2 * 2U));
|
|
temp |= ((GPIO_MODE_INPUT & 0x00000003U) << (2 * 2U));
|
|
temp &= ~(GPIO_MODER_MODE0 << (3 * 2U));
|
|
temp |= ((GPIO_MODE_INPUT & 0x00000003U) << (3 * 2U));
|
|
temp &= ~(GPIO_MODER_MODE0 << (4 * 2U));
|
|
temp |= ((GPIO_MODE_INPUT & 0x00000003U) << (4 * 2U));
|
|
temp &= ~(GPIO_MODER_MODE0 << (5 * 2U));
|
|
temp |= ((GPIO_MODE_INPUT & 0x00000003U) << (5 * 2U));
|
|
temp &= ~(GPIO_MODER_MODE0 << (6 * 2U));
|
|
temp |= ((GPIO_MODE_INPUT & 0x00000003U) << (6 * 2U));
|
|
temp &= ~(GPIO_MODER_MODE0 << (7 * 2U));
|
|
temp |= ((GPIO_MODE_INPUT & 0x00000003U) << (7 * 2U));
|
|
sendToDebug_uint32(temp,false);
|
|
GPIOA->MODER = temp;*/
|
|
GPIOA->MODER = -1431764992;
|
|
__asm("nop");__asm("nop");__asm("nop");
|
|
}
|
|
|
|
// switch bus to pin
|
|
static inline void FPGA_setBusOutput(void)
|
|
{
|
|
// Configure IO Direction mode (Output)
|
|
/*uint32_t temp = GPIOA->MODER;
|
|
temp &= ~(GPIO_MODER_MODE0 << (0 * 2U));
|
|
temp |= ((GPIO_MODE_OUTPUT_PP & 0x00000003U) << (0 * 2U));
|
|
temp &= ~(GPIO_MODER_MODE0 << (1 * 2U));
|
|
temp |= ((GPIO_MODE_OUTPUT_PP & 0x00000003U) << (1 * 2U));
|
|
temp &= ~(GPIO_MODER_MODE0 << (2 * 2U));
|
|
temp |= ((GPIO_MODE_OUTPUT_PP & 0x00000003U) << (2 * 2U));
|
|
temp &= ~(GPIO_MODER_MODE0 << (3 * 2U));
|
|
temp |= ((GPIO_MODE_OUTPUT_PP & 0x00000003U) << (3 * 2U));
|
|
temp &= ~(GPIO_MODER_MODE0 << (4 * 2U));
|
|
temp |= ((GPIO_MODE_OUTPUT_PP & 0x00000003U) << (4 * 2U));
|
|
temp &= ~(GPIO_MODER_MODE0 << (5 * 2U));
|
|
temp |= ((GPIO_MODE_OUTPUT_PP & 0x00000003U) << (5 * 2U));
|
|
temp &= ~(GPIO_MODER_MODE0 << (6 * 2U));
|
|
temp |= ((GPIO_MODE_OUTPUT_PP & 0x00000003U) << (6 * 2U));
|
|
temp &= ~(GPIO_MODER_MODE0 << (7 * 2U));
|
|
temp |= ((GPIO_MODE_OUTPUT_PP & 0x00000003U) << (7 * 2U));
|
|
sendToDebug_uint32(temp,false);
|
|
GPIOA->MODER = temp;*/
|
|
GPIOA->MODER = -1431743147;
|
|
__asm("nop");__asm("nop");__asm("nop");
|
|
}
|
|
|
|
// raise the CLK signal
|
|
static inline void FPGA_clockRise(void)
|
|
{
|
|
FPGA_CLK_GPIO_Port->BSRR = FPGA_CLK_Pin;
|
|
__asm("nop");__asm("nop");__asm("nop");
|
|
}
|
|
|
|
// remove CLK signal
|
|
static inline void FPGA_clockFall(void)
|
|
{
|
|
FPGA_CLK_GPIO_Port->BSRR = (FPGA_CLK_Pin << 16U);
|
|
__asm("nop");__asm("nop");__asm("nop");
|
|
}
|
|
|
|
// raise CLK and SYNC signal, then lower
|
|
static inline void FPGA_syncAndClockRiseFall(void)
|
|
{
|
|
FPGA_CLK_GPIO_Port->BSRR = FPGA_SYNC_Pin;
|
|
FPGA_CLK_GPIO_Port->BSRR = FPGA_CLK_Pin;
|
|
FPGA_CLK_GPIO_Port->BSRR = (FPGA_SYNC_Pin << 16U) | (FPGA_CLK_Pin << 16U);
|
|
__asm("nop");__asm("nop");__asm("nop");
|
|
}
|