kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
32 wiersze
330 B
Plaintext
32 wiersze
330 B
Plaintext
FPGA/db/*
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FPGA/output_files/*
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FPGA/greybox_tmp/*
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FPGA/incremental_db/*
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STM32/MDK-ARM/WOLF-Lite/*.htm
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STM32/MDK-ARM/WOLF-Lite/*.hex
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STM32/Debug/*
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Status Report.txt
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Design Rule Check*
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*~*.zip
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*.log
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*.o
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*.lnp
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*.bak
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*.uvguix.*
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*.d
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*.smsg
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*.rpt
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*.crf
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*._2i
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*.__i
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*._ia
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*.summary
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*.axf
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*.map
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*.dep
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*.jic
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*.pof
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*.rpt
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*.sof
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WOLF.uvguix.*
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