kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
23 wiersze
6.3 KiB
Plaintext
23 wiersze
6.3 KiB
Plaintext
Warning (10273): Verilog HDL warning at stm32_interface.v(93): extended using "x" or "z" File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/stm32_interface.v Line: 93
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Warning (10036): Verilog HDL or VHDL warning at tx_ciccomp_0002.vhd(54): object "coeff_in_read_sig" assigned a value but never read File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002.vhd Line: 54
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Warning (10541): VHDL Signal Declaration warning at tx_ciccomp_0002_ast.vhd(208): used implicit default value for signal "core_channel_out_core" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/tx_ciccomp/tx_ciccomp_0002_ast.vhd Line: 208
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Warning (10036): Verilog HDL or VHDL warning at rx_ciccomp_0002.vhd(54): object "coeff_in_read_sig" assigned a value but never read File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002.vhd Line: 54
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Warning (10541): VHDL Signal Declaration warning at rx_ciccomp_0002_ast.vhd(208): used implicit default value for signal "core_channel_out_core" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/rx_ciccomp/rx_ciccomp_0002_ast.vhd Line: 208
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Warning (12020): Port "counter_max" on the entity instantiation of "rate_cnt_inst" is connected to a signal of width 32. The formal width of the signal in the module is 11. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv Line: 486
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Warning (12020): Port "counter_max" on the entity instantiation of "channel_out_int_inst" is connected to a signal of width 32. The formal width of the signal in the module is 2. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv Line: 432
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Warning (12020): Port "counter_max" on the entity instantiation of "latency_cnt_inst" is connected to a signal of width 32. The formal width of the signal in the module is 4. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv Line: 419
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Warning (12020): Port "counter_max" on the entity instantiation of "counter_ch_inst" is connected to a signal of width 32. The formal width of the signal in the module is 1. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv Line: 79
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Warning (12020): Port "counter_max" on the entity instantiation of "counter_fs_inst" is connected to a signal of width 32. The formal width of the signal in the module is 11. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv Line: 50
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Warning (12020): Port "counter_max" on the entity instantiation of "rate_cnt_inst" is connected to a signal of width 32. The formal width of the signal in the module is 11. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv Line: 486
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Warning (12020): Port "counter_max" on the entity instantiation of "channel_out_int_inst" is connected to a signal of width 32. The formal width of the signal in the module is 2. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv Line: 432
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Warning (12020): Port "counter_max" on the entity instantiation of "latency_cnt_inst" is connected to a signal of width 32. The formal width of the signal in the module is 4. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/alt_cic_dec_siso.sv Line: 419
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Warning (12020): Port "counter_max" on the entity instantiation of "counter_ch_inst" is connected to a signal of width 32. The formal width of the signal in the module is 1. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv Line: 79
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Warning (12020): Port "counter_max" on the entity instantiation of "counter_fs_inst" is connected to a signal of width 32. The formal width of the signal in the module is 11. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/rx_cic/submodules/auk_dspip_downsample.sv Line: 50
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Warning (12020): Port "counter_max" on the entity instantiation of "counter_ch_inst" is connected to a signal of width 32. The formal width of the signal in the module is 1. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv Line: 313
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Warning (12020): Port "counter_max" on the entity instantiation of "counter_fs_inst" is connected to a signal of width 32. The formal width of the signal in the module is 12. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv Line: 298
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Warning (12020): Port "counter_max" on the entity instantiation of "latency_cnt_inst" is connected to a signal of width 32. The formal width of the signal in the module is 4. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv Line: 270
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Warning (12020): Port "counter_max" on the entity instantiation of "counter_ch_inst" is connected to a signal of width 32. The formal width of the signal in the module is 1. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv Line: 313
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Warning (12020): Port "counter_max" on the entity instantiation of "counter_fs_inst" is connected to a signal of width 32. The formal width of the signal in the module is 12. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv Line: 298
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Warning (12020): Port "counter_max" on the entity instantiation of "latency_cnt_inst" is connected to a signal of width 32. The formal width of the signal in the module is 4. The extra bits will be ignored. File: D:/Dropbox/Develop/Projects/WOLF-Lite/FPGA/db/ip/tx_cic/submodules/alt_cic_int_siso.sv Line: 270
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Warning (14284): Synthesized away the following node(s):
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