kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
64 wiersze
2.9 KiB
C
64 wiersze
2.9 KiB
C
#ifndef FPGA_h
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#define FPGA_h
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#include "stm32f4xx_hal.h"
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#include <stdbool.h>
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#include "fft.h"
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#include "audio_processor.h"
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#include "settings.h"
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#define FPGA_flash_size 0x200000
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#define FPGA_flash_file_offset (0xA0 - 1)
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#define FPGA_sector_size (64 * 1024)
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#define FPGA_page_size 256
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#define FPGA_FLASH_COMMAND_DELAY \
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for (uint32_t wait = 0; wait < 50; wait++) \
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__asm("nop"); //50
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#define FPGA_FLASH_WRITE_DELAY \
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for (uint32_t wait = 0; wait < 500; wait++) \
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__asm("nop"); //500
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#define FPGA_FLASH_READ_DELAY \
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for (uint32_t wait = 0; wait < 50; wait++) \
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__asm("nop"); //50
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#define FPGA_writePacket(value) (FPGA_BUS_D0_GPIO_Port->BSRR = (value) | 0xFF0000)
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#define FPGA_readPacket (FPGA_BUS_D0_GPIO_Port->IDR & 0xFF)
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//Micron M25P80 Serial Flash COMMANDS:
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#define M25P80_WRITE_ENABLE 0x06
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#define M25P80_WRITE_DISABLE 0x04
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#define M25P80_READ_IDENTIFICATION 0x9F
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#define M25P80_READ_IDENTIFICATION2 0x9E
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#define M25P80_READ_STATUS_REGISTER 0x05
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#define M25P80_WRITE_STATUS_REGISTER 0x01
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#define M25P80_READ_DATA_BYTES 0x03
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#define M25P80_READ_DATA_BYTES_at_HIGHER_SPEED 0x0B
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#define M25P80_PAGE_PROGRAM 0x02
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#define M25P80_SECTOR_ERASE 0xD8
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#define M25P80_BULK_ERASE 0xC7
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#define M25P80_DEEP_POWER_DOWN 0xB9
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#define M25P80_RELEASE_from_DEEP_POWER_DOWN 0xAB
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//Public variables
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extern volatile uint32_t FPGA_samples; // counter of the number of samples when exchanging with FPGA
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extern volatile bool FPGA_Buffer_underrun; // flag of lack of data from FPGA
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extern volatile bool FPGA_NeedSendParams; // flag of the need to send parameters to FPGA
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extern volatile bool FPGA_NeedGetParams; // flag of the need to get parameters from FPGA
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extern volatile bool FPGA_NeedRestart; // flag of necessity to restart FPGA modules
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extern volatile float32_t FPGA_Audio_Buffer_RX_Q[FPGA_RX_IQ_BUFFER_SIZE]; // FPGA buffers
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extern volatile float32_t FPGA_Audio_Buffer_RX_I[FPGA_RX_IQ_BUFFER_SIZE];
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extern volatile float32_t FPGA_Audio_SendBuffer_Q[FPGA_TX_IQ_BUFFER_SIZE];
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extern volatile float32_t FPGA_Audio_SendBuffer_I[FPGA_TX_IQ_BUFFER_SIZE];
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extern uint_fast16_t FPGA_Audio_RXBuffer_Index; // current index in FPGA buffers
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extern uint_fast16_t FPGA_Audio_TXBuffer_Index; // current index in FPGA buffers
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extern bool FPGA_Audio_Buffer_State; // buffer state, half or full full true - compleate; false - half
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//Public methods
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extern void FPGA_Init(void); // initialize exchange with FPGA
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extern void FPGA_fpgadata_iqclock(void); // exchange IQ data with FPGA
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extern void FPGA_fpgadata_stuffclock(void); // exchange parameters with FPGA
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extern void FPGA_restart(void); // restart FPGA modules
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extern uint8_t ADCDAC_OVR_StatusLatency;
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#endif
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