kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
436 wiersze
12 KiB
Verilog
436 wiersze
12 KiB
Verilog
// Copyright (C) 1988-2012 Altera Corporation
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// Any megafunction design, and related net list (encrypted or decrypted),
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// support information, device programming or simulation file, and any other
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// associated documentation or information provided by Altera or a partner
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// under Altera's Megafunction Partnership Program may be used only to
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// program PLD devices (but not masked PLD devices) from Altera. Any other
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// use of such megafunction design, net list, support information, device
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// programming or simulation file, or any other related documentation or
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// information is prohibited for any other purpose, including, but not
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// limited to modification, reverse engineering, de-compiling, or use with
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// any other silicon devices, unless such use is explicitly licensed under
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// a separate agreement with Altera or a megafunction partner. Title to
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// the intellectual property, including patents, copyrights, trademarks,
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// trade secrets, or maskworks, embodied in any such megafunction design,
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// net list, support information, device programming or simulation file, or
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// any other related documentation or information provided by Altera or a
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// megafunction partner, remains with Altera, the megafunction partner, or
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// their respective licensors. No other licenses, including any licenses
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// needed under any third party's intellectual property, are provided herein.
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module nco_nco_ii_0(clk, reset_n, clken, phi_inc_i, fsin_o, fcos_o, out_valid);
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parameter mpr = 12;
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parameter opr = 24;
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parameter apr = 22;
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parameter apri= 22;
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parameter aprf= 32;
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parameter aprp= 16;
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parameter aprid=27;
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parameter dpri= 10;
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parameter rdw = 12;
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parameter rawc = 11;
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parameter rnwc = 2048;
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parameter rawf = 11;
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parameter rnwf = 2048;
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parameter Pn = 1048576;
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parameter mxnbc = 24576;
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parameter mxnbf = 24576;
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parameter rsfc = "nco_nco_ii_0_sin_c.hex";
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parameter rsff = "nco_nco_ii_0_sin_f.hex";
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parameter rcfc = "nco_nco_ii_0_cos_c.hex";
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parameter rcff = "nco_nco_ii_0_cos_f.hex";
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parameter nc = 1;
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parameter log2nc =0;
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parameter outselinit = 0;
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parameter paci0= 0;
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parameter paci1= 0;
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parameter paci2= 0;
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parameter paci3= 0;
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parameter paci4= 0;
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parameter paci5= 0;
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parameter paci6= 0;
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parameter paci7= 0;
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//parameter numba = 1;
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//parameter log2numba = 0;
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input clk;
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input reset_n;
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input clken;
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input [apr-1:0] phi_inc_i;
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output [mpr-1:0] fsin_o;
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output [mpr-1:0] fcos_o;
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output out_valid;
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wire reset;
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assign reset = !reset_n;
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wire [apr-1:0] phi_inc_i_w;
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wire [apr-1:0] phi_acc_w;
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wire [mpr-1:0] rfx_s;
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wire [mpr-1:0] rcx_s;
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wire [mpr-1:0] rfx_c;
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wire [mpr-1:0] rcx_c;
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wire [mpr-1:0] rfy_s;
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wire [mpr-1:0] rcy_s;
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wire [mpr-1:0] rfy_c;
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wire [mpr-1:0] rcy_c;
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wire [rawc-1:0] raxxx001ms;
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wire [rawc-1:0] raxxx001mc;
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wire [rawc-1:0] raxxx000m;
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wire [rawf-1:0] raxxx000l;
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wire [rawc-1:0] raxxx001m;
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wire [rawf-1:0] raxxx001l;
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wire [opr-1:0] result_i;
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wire [opr-1:0] result_r;
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wire [mpr-1:0] fsin_o_w;
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wire [mpr-1:0] fcos_o_w;
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wire out_valid_w;
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//Pipelining for Hyper Retimer starts from here
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parameter hyper_pipeline = 0;
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integer i;
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reg [1-1:0] reset_reg [3-1:0];
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wire [1-1:0] reset_pipelined;
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reg [1-1:0] clken_reg [3-1:0];
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wire [1-1:0] clken_pipelined;
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reg [apr-1:0] phi_inc_i_reg [3-1:0];
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wire [apr-1:0] phi_inc_i_pipelined;
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reg [1-1:0] out_valid_w_reg [2-1:0];
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wire [1-1:0] out_valid_w_pipelined;
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reg [mpr-1:0] fsin_o_w_reg [2-1:0];
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wire [mpr-1:0] fsin_o_w_pipelined;
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reg [opr-1:0] result_i_reg [1-1:0];
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wire [opr-1:0] result_i_pipelined;
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reg [mpr-1:0] fcos_o_w_reg [2-1:0];
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wire [mpr-1:0] fcos_o_w_pipelined;
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reg [opr-1:0] result_r_reg [1-1:0];
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wire [opr-1:0] result_r_pipelined;
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reg [mpr-1:0] rcx_c_reg [2-1:0];
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wire [mpr-1:0] rcx_c_pipelined;
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reg [mpr-1:0] rfx_c_reg [2-1:0];
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wire [mpr-1:0] rfx_c_pipelined;
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reg [mpr-1:0] rcx_s_reg [2-1:0];
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wire [mpr-1:0] rcx_s_pipelined;
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reg [mpr-1:0] rfx_s_reg [2-1:0];
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wire [mpr-1:0] rfx_s_pipelined;
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// Pipeline block
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generate
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if (hyper_pipeline == 1) begin
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always @ (posedge clk) begin
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reset_reg[0] <= reset;
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for (i = 1; i < 3; i=i+1) begin
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reset_reg[i] <= reset_reg[i-1];
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end
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end
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assign reset_pipelined = reset_reg[3-1];
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end
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else begin
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assign reset_pipelined = reset; // pipeline for this signal is disabled
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end
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endgenerate
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// Pipeline block
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generate
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if (hyper_pipeline == 1) begin
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always @ (posedge clk) begin
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clken_reg[0] <= clken;
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for (i = 1; i < 3; i=i+1) begin
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clken_reg[i] <= clken_reg[i-1];
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end
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end
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assign clken_pipelined = clken_reg[3-1];
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end
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else begin
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assign clken_pipelined = clken; // pipeline for this signal is disabled
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end
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endgenerate
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// Pipeline block
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generate
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if (hyper_pipeline == 1) begin
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always @ (posedge clk) begin
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phi_inc_i_reg[0] <= phi_inc_i;
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for (i = 1; i < 3; i=i+1) begin
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phi_inc_i_reg[i] <= phi_inc_i_reg[i-1];
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end
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end
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assign phi_inc_i_pipelined = phi_inc_i_reg[3-1];
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end
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else begin
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assign phi_inc_i_pipelined = phi_inc_i; // pipeline for this signal is disabled
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end
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endgenerate
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// Pipeline block
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generate
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if (hyper_pipeline == 1) begin
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always @ (posedge clk) begin
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out_valid_w_reg[0] <= out_valid_w;
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for (i = 1; i < 2; i=i+1) begin
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out_valid_w_reg[i] <= out_valid_w_reg[i-1];
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end
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end
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assign out_valid_w_pipelined = out_valid_w_reg[2-1];
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end
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else begin
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assign out_valid_w_pipelined = out_valid_w; // pipeline for this signal is disabled
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end
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endgenerate
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// Pipeline block
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generate
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if (hyper_pipeline == 1) begin
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always @ (posedge clk) begin
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fsin_o_w_reg[0] <= fsin_o_w;
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for (i = 1; i < 2; i=i+1) begin
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fsin_o_w_reg[i] <= fsin_o_w_reg[i-1];
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end
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end
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assign fsin_o_w_pipelined = fsin_o_w_reg[2-1];
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end
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else begin
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assign fsin_o_w_pipelined = fsin_o_w; // pipeline for this signal is disabled
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end
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endgenerate
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// Pipeline block
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generate
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if (hyper_pipeline == 1) begin
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always @ (posedge clk) begin
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result_i_reg[0] <= result_i;
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end
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assign result_i_pipelined = result_i_reg[1-1];
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end
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else begin
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assign result_i_pipelined = result_i; // pipeline for this signal is disabled
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end
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endgenerate
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// Pipeline block
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generate
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if (hyper_pipeline == 1) begin
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always @ (posedge clk) begin
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fcos_o_w_reg[0] <= fcos_o_w;
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for (i = 1; i < 2; i=i+1) begin
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fcos_o_w_reg[i] <= fcos_o_w_reg[i-1];
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end
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end
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assign fcos_o_w_pipelined = fcos_o_w_reg[2-1];
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end
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else begin
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assign fcos_o_w_pipelined = fcos_o_w; // pipeline for this signal is disabled
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end
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endgenerate
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// Pipeline block
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generate
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if (hyper_pipeline == 1) begin
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always @ (posedge clk) begin
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result_r_reg[0] <= result_r;
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end
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assign result_r_pipelined = result_r_reg[1-1];
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end
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else begin
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assign result_r_pipelined = result_r; // pipeline for this signal is disabled
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end
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endgenerate
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// Pipeline block
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generate
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if (hyper_pipeline == 1) begin
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always @ (posedge clk) begin
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rcx_c_reg[0] <= rcx_c;
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for (i = 1; i < 2; i=i+1) begin
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rcx_c_reg[i] <= rcx_c_reg[i-1];
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end
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end
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assign rcx_c_pipelined = rcx_c_reg[2-1];
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end
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else begin
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assign rcx_c_pipelined = rcx_c; // pipeline for this signal is disabled
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end
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endgenerate
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// Pipeline block
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generate
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if (hyper_pipeline == 1) begin
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always @ (posedge clk) begin
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rfx_c_reg[0] <= rfx_c;
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for (i = 1; i < 2; i=i+1) begin
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rfx_c_reg[i] <= rfx_c_reg[i-1];
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end
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end
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assign rfx_c_pipelined = rfx_c_reg[2-1];
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end
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else begin
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assign rfx_c_pipelined = rfx_c; // pipeline for this signal is disabled
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end
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endgenerate
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// Pipeline block
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generate
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if (hyper_pipeline == 1) begin
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always @ (posedge clk) begin
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rcx_s_reg[0] <= rcx_s;
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for (i = 1; i < 2; i=i+1) begin
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rcx_s_reg[i] <= rcx_s_reg[i-1];
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end
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end
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assign rcx_s_pipelined = rcx_s_reg[2-1];
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end
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else begin
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assign rcx_s_pipelined = rcx_s; // pipeline for this signal is disabled
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end
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endgenerate
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// Pipeline block
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generate
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if (hyper_pipeline == 1) begin
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always @ (posedge clk) begin
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rfx_s_reg[0] <= rfx_s;
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for (i = 1; i < 2; i=i+1) begin
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rfx_s_reg[i] <= rfx_s_reg[i-1];
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end
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end
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assign rfx_s_pipelined = rfx_s_reg[2-1];
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end
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else begin
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assign rfx_s_pipelined = rfx_s; // pipeline for this signal is disabled
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end
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endgenerate
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assign phi_inc_i_w = phi_inc_i_pipelined;
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asj_altqmcpipe ux000 (.clk(clk),
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.reset(reset_pipelined),
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.clken(clken_pipelined),
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.phi_inc_int(phi_inc_i_w),
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.phi_acc_reg(phi_acc_w)
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);
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defparam ux000.nc = nc ;
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defparam ux000.apr = apr ;
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defparam ux000.lat = 1 ;
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defparam ux000.paci0 = paci0 ;
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defparam ux000.paci1 = paci1 ;
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defparam ux000.paci2 = paci2 ;
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defparam ux000.paci3 = paci3 ;
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defparam ux000.paci4 = paci4 ;
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defparam ux000.paci5 = paci5 ;
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defparam ux000.paci6 = paci6 ;
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defparam ux000.paci7 = paci7 ;
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asj_gam_dp ux008( .clk(clk),
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.reset(reset_pipelined),
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.clken(clken_pipelined),
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.phi_acc_w(phi_acc_w[apr-1:apr-rawc-rawf]),
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.rom_add_cs(raxxx001ms),
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.rom_add_cc(raxxx001mc),
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.rom_add_f(raxxx001l)
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);
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defparam ux008.rawc = rawc;
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defparam ux008.rawf = rawf;
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defparam ux008.apr = apri;
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asj_nco_as_m_dp_cen ux0220(.clk(clk),
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.clken (clken_pipelined),
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.raxx_a(raxxx001ms[rawc-1:0]),
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.raxx_b(raxxx001mc[rawc-1:0]),
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.q_a(rcx_s[mpr-1:0]),
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.q_b(rcx_c[mpr-1:0])
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);
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defparam ux0220.mpr = mpr;
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defparam ux0220.rdw = rdw;
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defparam ux0220.raw = rawc;
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defparam ux0220.rnw = rnwc;
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defparam ux0220.rf = rsfc;
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defparam ux0220.dev = "Cyclone IV E";
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asj_nco_as_m_cen ux0122(.clk(clk),
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.clken (clken_pipelined),
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.raxx(raxxx001l[rawf-1:0]),
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.srw_int_res(rfx_s[mpr-1:0])
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);
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defparam ux0122.mpr = mpr;
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defparam ux0122.rdw = rdw;
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defparam ux0122.raw = rawf;
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defparam ux0122.rnw = rnwf;
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defparam ux0122.rf = rsff;
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defparam ux0122.dev = "Cyclone IV E";
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asj_nco_as_m_cen ux0123(.clk(clk),
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.clken (clken_pipelined),
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.raxx(raxxx001l[rawf-1:0]),
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.srw_int_res(rfx_c[mpr-1:0])
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);
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defparam ux0123.mpr = mpr;
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defparam ux0123.rdw = rdw;
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defparam ux0123.raw = rawf;
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defparam ux0123.rnw = rnwf;
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defparam ux0123.rf = rcff;
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defparam ux0123.dev = "Cyclone IV E";
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asj_nco_madx_cen m1(
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.dataa_0(rcy_c),
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.dataa_1(rcy_s),
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.datab_0(rfy_c),
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.datab_1(rfy_s),
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.result(result_r),
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.clock0(clk),
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.clken(clken_pipelined));
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defparam m1.mpr = mpr;
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defparam m1.opr = opr;
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// Writing multiplier for 'Cyclone IV E'
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asj_nco_mady_cen m0(
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.dataa_0(rcy_s),
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.dataa_1(rfy_s),
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.datab_0(rfy_c),
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.datab_1(rcy_c),
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.result(result_i),
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.clock0(clk),
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.clken(clken_pipelined));
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defparam m0.mpr = mpr;
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defparam m0.opr = opr;
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// Writing multiplier for 'Cyclone IV E'
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asj_nco_derot ux0136(.crwx_rc(rcx_c_pipelined),
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.crwx_rf(rfx_c_pipelined),
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.srwx_rc(rcx_s_pipelined),
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.srwx_rf(rfx_s_pipelined),
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.crwy_rc(rcy_c),
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.crwy_rf(rfy_c),
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.srwy_rc(rcy_s),
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.srwy_rf(rfy_s)
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);
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defparam ux0136.mpr = mpr;
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defparam ux0136.rxt = rdw;
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asj_nco_mob_w blk0( .clk(clk),
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.reset(reset_pipelined),
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.clken(clken_pipelined),
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.data_in(result_i_pipelined),
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.data_out(fsin_o_w));
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defparam blk0.mpr = mpr;
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asj_nco_mob_w blk1( .clk(clk),
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.reset(reset_pipelined),
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.clken(clken_pipelined),
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.data_in(result_r_pipelined),
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.data_out(fcos_o_w));
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defparam blk1.mpr = mpr;
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assign fsin_o = fsin_o_w_pipelined;
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assign fcos_o = fcos_o_w_pipelined;
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asj_nco_isdr ux710isdr(.clk(clk),
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.reset(reset_pipelined),
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.clken(clken_pipelined),
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.data_ready(out_valid_w)
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);
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defparam ux710isdr.ctc=8;
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defparam ux710isdr.cpr=4;
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assign out_valid = out_valid_w_pipelined;
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endmodule
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