kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
132 wiersze
5.9 KiB
XML
132 wiersze
5.9 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<deploy
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date="2019.11.10.03:26:30"
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outputDirectory="D:/Dropbox/Develop/Projects/UA3REO/FPGA/clock_buffer/">
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<perimeter>
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<parameter
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name="AUTO_GENERATION_ID"
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type="Integer"
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defaultValue="0"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_UNIQUE_ID"
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type="String"
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defaultValue=""
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE_FAMILY"
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type="String"
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defaultValue="Cyclone IV E"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE"
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type="String"
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defaultValue="EP4CE22E22C8"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE_SPEEDGRADE"
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type="String"
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defaultValue="8"
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onHdl="0"
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affectsHdl="1" />
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<interface name="altclkctrl_input" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port name="inclk" direction="input" role="inclk" width="1" />
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</interface>
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<interface name="altclkctrl_output" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port name="outclk" direction="output" role="outclk" width="1" />
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</interface>
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</perimeter>
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<entity
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path=""
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parameterizationKey="clock_buffer:1.0:AUTO_DEVICE=EP4CE22E22C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1573341989,AUTO_UNIQUE_ID=(altclkctrl:18.1:CLOCK_TYPE=1,DEVICE_FAMILY=Cyclone IV E,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=1,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false)"
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instancePathKey="clock_buffer"
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kind="clock_buffer"
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version="1.0"
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name="clock_buffer">
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<parameter name="AUTO_GENERATION_ID" value="1573341989" />
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<parameter name="AUTO_DEVICE" value="EP4CE22E22C8" />
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<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
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<parameter name="AUTO_UNIQUE_ID" value="" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
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<generatedFiles>
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<file
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path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/clock_buffer/synthesis/clock_buffer.v"
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type="VERILOG" />
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</generatedFiles>
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<childGeneratedFiles>
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<file
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path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/clock_buffer/synthesis/submodules/clock_buffer_altclkctrl_0.v"
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type="VERILOG"
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attributes="" />
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</childGeneratedFiles>
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<sourceFiles>
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<file path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/clock_buffer.qsys" />
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</sourceFiles>
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<childSourceFiles>
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<file
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path="C:/intelfpga/18.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
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</childSourceFiles>
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<messages>
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<message level="Debug" culprit="clock_buffer">queue size: 0 starting:clock_buffer "clock_buffer"</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Debug">Transform: CustomInstructionTransform</message>
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<message level="Debug">No custom instruction connections, skipping transform </message>
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<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
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<message level="Debug">Transform: MMTransform</message>
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<message level="Debug">Transform: InterruptMapperTransform</message>
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<message level="Debug">Transform: InterruptSyncTransform</message>
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<message level="Debug">Transform: InterruptFanoutTransform</message>
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<message level="Debug">Transform: AvalonStreamingTransform</message>
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<message level="Debug">Transform: ResetAdaptation</message>
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<message level="Debug" culprit="clock_buffer"><![CDATA["<b>clock_buffer</b>" reuses <b>altclkctrl</b> "<b>submodules/clock_buffer_altclkctrl_0</b>"]]></message>
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<message level="Debug" culprit="clock_buffer">queue size: 0 starting:altclkctrl "submodules/clock_buffer_altclkctrl_0"</message>
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<message level="Info" culprit="altclkctrl_0">Generating top-level entity clock_buffer_altclkctrl_0.</message>
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<message level="Debug" culprit="altclkctrl_0">Current quartus bindir: C:/intelfpga/18.1/quartus/bin64/.</message>
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<message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clock_buffer</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
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</messages>
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</entity>
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<entity
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path="submodules/"
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parameterizationKey="altclkctrl:18.1:CLOCK_TYPE=1,DEVICE_FAMILY=Cyclone IV E,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=1,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false"
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instancePathKey="clock_buffer:.:altclkctrl_0"
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kind="altclkctrl"
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version="18.1"
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name="clock_buffer_altclkctrl_0">
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<parameter name="NUMBER_OF_CLOCKS" value="1" />
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<parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
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<parameter name="GUI_USE_ENA" value="false" />
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<parameter name="DEVICE_FAMILY" value="Cyclone IV E" />
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<parameter name="ENA_REGISTER_MODE" value="1" />
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<parameter name="CLOCK_TYPE" value="1" />
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<generatedFiles>
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<file
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path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/clock_buffer/synthesis/submodules/clock_buffer_altclkctrl_0.v"
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type="VERILOG"
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attributes="" />
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</generatedFiles>
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<childGeneratedFiles/>
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<sourceFiles>
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<file
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path="C:/intelfpga/18.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
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</sourceFiles>
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<childSourceFiles/>
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<instantiator instantiator="clock_buffer" as="altclkctrl_0" />
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<messages>
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<message level="Debug" culprit="clock_buffer">queue size: 0 starting:altclkctrl "submodules/clock_buffer_altclkctrl_0"</message>
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<message level="Info" culprit="altclkctrl_0">Generating top-level entity clock_buffer_altclkctrl_0.</message>
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<message level="Debug" culprit="altclkctrl_0">Current quartus bindir: C:/intelfpga/18.1/quartus/bin64/.</message>
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<message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clock_buffer</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
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</messages>
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</entity>
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</deploy>
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