kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
12 wiersze
222 B
VHDL
12 wiersze
222 B
VHDL
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component DEBUG2 is
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port (
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probe : in std_logic_vector(23 downto 0) := (others => 'X') -- probe
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);
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end component DEBUG2;
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u0 : component DEBUG2
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port map (
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probe => CONNECTED_TO_probe -- probes.probe
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);
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