kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
29 wiersze
1.6 KiB
Plaintext
29 wiersze
1.6 KiB
Plaintext
|
Info: Starting: Create block symbol file (.bsf)
|
||
|
Info: qsys-generate D:\Dropbox\Develop\Projects\WOLF-Lite\Scheme\FPGA\DEBUG.qsys --block-symbol-file --output-directory=D:\Dropbox\Develop\Projects\WOLF-Lite\Scheme\FPGA\DEBUG --family="Cyclone IV E" --part=EP4CE10E22C8
|
||
|
Progress: Loading FPGA/DEBUG.qsys
|
||
|
Progress: Reading input file
|
||
|
Progress: Adding in_system_sources_probes_0 [altera_in_system_sources_probes 18.1]
|
||
|
Progress: Parameterizing module in_system_sources_probes_0
|
||
|
Progress: Building connections
|
||
|
Progress: Parameterizing connections
|
||
|
Progress: Validating
|
||
|
Progress: Done reading input file
|
||
|
Info: qsys-generate succeeded.
|
||
|
Info: Finished: Create block symbol file (.bsf)
|
||
|
Info:
|
||
|
Info: Starting: Create HDL design files for synthesis
|
||
|
Info: qsys-generate D:\Dropbox\Develop\Projects\WOLF-Lite\Scheme\FPGA\DEBUG.qsys --synthesis=VERILOG --output-directory=D:\Dropbox\Develop\Projects\WOLF-Lite\Scheme\FPGA\DEBUG\synthesis --family="Cyclone IV E" --part=EP4CE10E22C8
|
||
|
Progress: Loading FPGA/DEBUG.qsys
|
||
|
Progress: Reading input file
|
||
|
Progress: Adding in_system_sources_probes_0 [altera_in_system_sources_probes 18.1]
|
||
|
Progress: Parameterizing module in_system_sources_probes_0
|
||
|
Progress: Building connections
|
||
|
Progress: Parameterizing connections
|
||
|
Progress: Validating
|
||
|
Progress: Done reading input file
|
||
|
Info: DEBUG: Generating DEBUG "DEBUG" for QUARTUS_SYNTH
|
||
|
Info: in_system_sources_probes_0: "DEBUG" instantiated altera_in_system_sources_probes "in_system_sources_probes_0"
|
||
|
Info: DEBUG: Done "DEBUG" with 2 modules, 2 files
|
||
|
Info: qsys-generate succeeded.
|
||
|
Info: Finished: Create HDL design files for synthesis
|