kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
17 wiersze
922 B
Plaintext
17 wiersze
922 B
Plaintext
|
component rx_cic is
|
||
|
port (
|
||
|
in_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error
|
||
|
in_valid : in std_logic := 'X'; -- valid
|
||
|
in_ready : out std_logic; -- ready
|
||
|
in_data : in std_logic_vector(22 downto 0) := (others => 'X'); -- in_data
|
||
|
out_data : out std_logic_vector(85 downto 0); -- out_data
|
||
|
out_error : out std_logic_vector(1 downto 0); -- error
|
||
|
out_valid : out std_logic; -- valid
|
||
|
out_ready : in std_logic := 'X'; -- ready
|
||
|
clken : in std_logic := 'X'; -- clken
|
||
|
clk : in std_logic := 'X'; -- clk
|
||
|
reset_n : in std_logic := 'X' -- reset_n
|
||
|
);
|
||
|
end component rx_cic;
|
||
|
|