kopia lustrzana https://gitlab.com/markol/Teathimble_Firmware
333 wiersze
8.9 KiB
C
333 wiersze
8.9 KiB
C
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/** \file
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\brief Timer management, AVR and simulator specific part.
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To be included from timer.c.
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Teacup uses timer1 to generate both step pulse clock and system clock.
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We achieve this by using the output compare registers to generate the two clocks while the timer free-runs.
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Teacup has tried numerous timer management methods, and this is the best so far.
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*/
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//#if defined TEACUP_C_INCLUDE && (defined __AVR__ || defined SIMULATOR)
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#include "config.h"
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#include "pinio.h"
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#ifdef MOTHERBOARD
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#include "queue.h"
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#endif
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/**
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Time until next step, as output compare register is too small for long
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step times.
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*/
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uint32_t next_step_time;
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/** System clock interrupt.
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Comparator B is the system clock, happens every TICK_TIME.
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*/
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ISR(TIMER1_COMPB_vect) {
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static volatile uint8_t busy = 0;
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// set output compare register to the next clock tick
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OCR1B = (OCR1B + TICK_TIME) & 0xFFFF;
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//clock_tick();
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/**
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Lengthy calculations ahead! Make sure we didn't re-enter, then allow
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nested interrupts.
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*/
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if ( ! busy) {
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busy = 1;
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sei();
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dda_clock();
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busy = 0;
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}
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}
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#ifdef MOTHERBOARD
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/** Step interrupt.
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Comparator A is the step timer. It has higher priority then B.
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*/
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ISR(TIMER1_COMPA_vect) {
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// Check if this is a real step, or just a next_step_time "overflow"
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if (next_step_time < 65536) {
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// step!
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#ifdef DEBUG_LED_PIN
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WRITE(DEBUG_LED_PIN, 1);
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#endif
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// disable this interrupt. if we set a new timeout, it will be re-enabled when appropriate
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#if defined (__AVR_ATmega32U4__) || defined (__AVR_ATmega32__) || \
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defined (__AVR_ATmega16__)
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TIMSK &= ~MASK(OCIE1A);
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#else
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TIMSK1 &= ~MASK(OCIE1A);
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#endif
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// stepper tick
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queue_step();
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// led off
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#ifdef DEBUG_LED_PIN
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WRITE(DEBUG_LED_PIN, 0);
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#endif
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return;
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}
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next_step_time -= 65536;
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// Similar algorithm as described in timer_set() below.
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if (next_step_time < 65536) {
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OCR1A = (OCR1A + next_step_time) & 0xFFFF;
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} else if(next_step_time < 75536){
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OCR1A = (OCR1A - 10000) & 0xFFFF;
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next_step_time += 10000;
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}
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// leave OCR1A as it was
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}
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#endif /* ifdef MOTHERBOARD */
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/** Timer initialisation.
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Initialise timer and enable system clock interrupt. Step interrupt is
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enabled later, when we start using it.
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*/
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void timer_init() {
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// no outputs
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TCCR1A = 0;
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// Normal Mode
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TCCR1B = MASK(CS10);
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// set up "clock" comparator for first tick
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OCR1B = TICK_TIME & 0xFFFF;
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// enable interrupt
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#if defined (__AVR_ATmega32U4__) || defined (__AVR_ATmega32__) || \
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defined (__AVR_ATmega16__)
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TIMSK = MASK(OCIE1B);
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#else
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TIMSK1 = MASK(OCIE1B);
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#endif
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#ifdef SIMULATOR
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// Tell simulator
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sim_timer_set();
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#endif
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}
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#ifdef MOTHERBOARD
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/** Specify how long until the step timer should fire.
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\param delay Delay for the next step interrupt, in CPU ticks.
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\param check_short Tell whether to check for impossibly short requests. This
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should be set to 1 for calls from the step interrupt. Short requests
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then return 1 and do not schedule a timer interrupt. The calling code
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usually wants to handle this case.
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Calls from elsewhere should set it to 0. In this case a timer
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interrupt is always scheduled.
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\return A flag whether the requested time was too short to allow scheduling
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an interrupt. This is meaningful for ACCELERATION_TEMPORAL, where
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requested delays can be zero or even negative. In this case, the
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calling code should repeat the stepping code immediately and also
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assume the timer to not change his idea of when the last step
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happened.
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Strategy of this timer is to schedule timer interrupts not starting at the
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time of the call, but starting at the time of the previous timer interrupt
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fired. This ignores the processing time taken in the step interrupt so far,
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offering smooth and even step distribution. Flipside of this coin is,
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one has to call timer_reset() before scheduling a step at an arbitrary time.
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This enables the step interrupt, but also disables interrupts globally.
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So, if you use it from inside the step interrupt, make sure to do so
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as late as possible. If you use it from outside the step interrupt,
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do a sei() after it to make the interrupt actually fire.
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*/
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uint8_t timer_set(int32_t delay, uint8_t check_short) {
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uint16_t step_start = 0;
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// An interrupt would make all our timing calculations invalid,
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// so stop that here.
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cli();
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CLI_SEI_BUG_MEMORY_BARRIER();
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// Assume all steps belong to one move. Within one move the delay is
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// from one step to the next one, which should be more or less the same
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// as from one step interrupt to the next one. The last step interrupt happend
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// at OCR1A, so start delay from there.
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step_start = OCR1A;
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next_step_time = delay;
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// From here on we assume the requested delay is long enough to allow
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// completion of the current interrupt before the next one is about to
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// happen.
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// Now we know how long we actually want to delay, so set the timer.
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if (next_step_time < 65536) {
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// set the comparator directly to the next real step
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OCR1A = (next_step_time + step_start) & 0xFFFF;
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}
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else if (next_step_time < 75536) {
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// Next comparator interrupt would have to trigger another
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// interrupt within a short time (possibly within 1 cycle).
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// Avoid the impossible by firing the interrupt earlier.
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OCR1A = (step_start - 10000) & 0xFFFF;
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next_step_time += 10000;
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}
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else {
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OCR1A = step_start;
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}
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// Enable this interrupt, but only do it after disabling
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// global interrupts (see above). This will cause push any possible
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// timer1a interrupt to the far side of the return, protecting the
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// stack from recursively clobbering memory.
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#if defined (__AVR_ATmega32U4__) || defined (__AVR_ATmega32__) || \
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defined (__AVR_ATmega16__)
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TIMSK |= MASK(OCIE1A);
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#else
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TIMSK1 |= MASK(OCIE1A);
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#endif
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#ifdef SIMULATOR
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// Tell simulator
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sim_timer_set();
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#endif
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return 0;
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}
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/** Timer reset.
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Reset the timer, so step interrupts scheduled at an arbitrary point in time
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don't lead to a full round through the timer counter.
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On AVR we simply do nothing, such a full round through the timer is just
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2^16 / F_CPU = 3 to 4 milliseconds.
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*/
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void timer_reset() {
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}
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/** Stop timers.
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This means to be an emergency stop.
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*/
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void timer_stop() {
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// disable all interrupts
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#if defined (__AVR_ATmega32U4__) || defined (__AVR_ATmega32__) || \
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defined (__AVR_ATmega16__)
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TIMSK = 0;
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#else
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TIMSK1 = 0;
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#endif
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#ifdef SIMULATOR
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// Tell simulator
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sim_timer_stop();
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#endif
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}
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#endif /* ifdef MOTHERBOARD */
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//#endif /* defined TEACUP_C_INCLUDE && (defined __AVR__ || defined SIMULATOR) */
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#include <avr/io.h>
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/** Initialise the CPU.
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This sets up the CPU the way we need it. It disables modules we don't use,
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so they don't mess on the I/O pins they're connected to.
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*/
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void cpu_init() {
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#ifdef PRR
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#if defined I2C && defined SPI
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PRR = MASK(PRADC);
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#elif defined SPI
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PRR = MASK(PRADC) | MASK(PRTWI);
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#elif defined I2C
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PRR = MASK(PRADC) | MASK(PRSPI);
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#else
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PRR = MASK(PRADC) | MASK(PRTWI) | MASK(PRSPI);
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#endif
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#elif defined PRR0
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#if defined I2C && defined SPI
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PRR0 = MASK(PRADC);
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#elif defined SPI
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PRR0 = MASK(PRADC) | MASK(PRTWI);
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#elif defined I2C
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PRR0 = MASK(PRADC) | MASK(PRSPI);
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#else
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PRR0 = MASK(PRADC) | MASK(PRTWI) | MASK(PRSPI);
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#endif
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#if defined(PRUSART3)
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// Don't use USART2 or USART3. Leave USART1 for GEN3 and derivatives.
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PRR1 |= MASK(PRUSART3) | MASK(PRUSART2);
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#endif
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#if defined(PRUSART2)
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// Don't use USART2 or USART3. Leave USART1 for GEN3 and derivatives.
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PRR1 |= MASK(PRUSART2);
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#endif
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#endif
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ACSR = MASK(ACD);
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}
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#include <util/delay_basic.h>
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#if F_CPU < 4000000UL
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#error Delay functions on AVR only work with F_CPU >= 4000000UL
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#endif
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/** Delay in microseconds.
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\param delay Time to wait in microseconds.
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Calibrated in SimulAVR.
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Accuracy on 20 MHz CPU clock: -1/+3 clock cycles over the whole range(!).
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Accuracy on 16 MHz CPU clock: delay is about 0.8% too short.
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Exceptions are delays of 0..2 on 20 MHz, which are all 0.75 us and delays
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of 0..3 on 16 MHz, which are all 0.93us.
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*/
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void delay_us(uint16_t delay) {
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// Compensate call overhead, as close as possible.
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#define OVERHEAD_CALL_CLOCKS 39 // clock cycles
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#define OVERHEAD_CALL_DIV ((OVERHEAD_CALL_CLOCKS / (F_CPU / 1000000)) + 1)
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#define OVERHEAD_CALL_REM ((OVERHEAD_CALL_DIV * (F_CPU / 1000000)) - \
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OVERHEAD_CALL_CLOCKS)
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if (delay > OVERHEAD_CALL_DIV) {
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delay -= OVERHEAD_CALL_DIV;
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if (OVERHEAD_CALL_REM >= 2)
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_delay_loop_2((OVERHEAD_CALL_REM + 2) / 4);
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}
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else {
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return;
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}
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while (delay > (65536L / (F_CPU / 4000000L))) {
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#define OVERHEAD_LOOP_CLOCKS 13
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_delay_loop_2(65536 - (OVERHEAD_LOOP_CLOCKS + 2) / 4);
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delay -= (65536L / (F_CPU / 4000000L));
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}
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if (delay)
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_delay_loop_2(delay * (F_CPU / 4000000L));
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}
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