kopia lustrzana https://github.com/SP8EBC/ParaTNC
121 wiersze
3.2 KiB
C
121 wiersze
3.2 KiB
C
#include "afsk_pr.h"
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#include "station_config_target_hw.h"
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#ifdef STM32F10X_MD_VL
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#include <stm32f10x.h>
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#include "antilib_adc.h"
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#endif
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#ifdef STM32L471xx
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#include <stm32l4xx.h>
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#include <stm32l4xx_ll_adc.h>
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#endif
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void ADCStartConfig(void) {
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#ifdef STM32F10X_MD_VL
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RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
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ADC1->CR2 |= ADC_CR2_ADON;
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ADC1->CR2 |= ADC_CR2_RSTCAL; // Reset calibration
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while(ADC1->CR2 & ADC_CR2_RSTCAL); // Wait for reset
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ADC1->CR2 |= ADC_CR2_CAL; // Start calibration
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while(ADC1->CR2 & ADC_CR2_CAL);
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ADC1->SQR1 = ADC_SEQUENCE_LENGTH(0); // odczyt tylko jednego kana<6E>u
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ADC1->SQR3 = ADC_SEQ1(11); // wyb<79>r kana<6E>u ADC -- 11 - napi<70>cie zasilania
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ADC1->SMPR1 = ADC_SAMPLE_TIME0(SAMPLE_TIME_7_5); // czas pr<70>bkowania
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// ADC1->CR1 = ADC_CR1_EOCIE; /// przerwanie na zako<6B>czenie konwersji
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// NVIC_EnableIRQ(ADC1_2_IRQn);
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// NVIC_SetPriority(ADC1_2_IRQn, 3);
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ADC1->CR2 |= ADC_CR2_CONT;
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ADC1->CR2 |= ADC_CR2_ADON;
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ADC1->DR;
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#endif
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#ifdef STM32L471xx
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/**
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* On STM32L47x/L48x devices each analog GPIO input pin must be connected
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* to respective ADC input channel by programming bit within GPIOx_ASCR register in the
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GPIO. This has to be done independely from configuring I/O in analog mode.
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*
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*/
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volatile int stupid_delay = 0;
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// reset the clock for ADC
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RCC->AHB2ENR &= (0xFFFFFFFF ^ RCC_AHB2ENR_ADCEN);
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RCC->AHB2ENR |= RCC_AHB2ENR_ADCEN;
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// the adc should be disabled now, but just to be sure that this is a case
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ADC1->CR &= (0xFFFFFFFF ^ ADC_CR_ADEN);
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// exit from deep-power-down mode
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ADC1->CR &= (0xFFFFFFFF ^ ADC_CR_DEEPPWD);
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// start ADC voltage regulator
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ADC1->CR |= ADC_CR_ADVREGEN;
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// wait for voltage regulator to start
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for (; stupid_delay < 0x1FFFF; stupid_delay++);
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// start the calibration
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ADC1->CR |= ADC_CR_ADCAL;
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// wait for calibration to finish
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while((ADC1->CR & ADC_CR_ADCAL) == ADC_CR_ADCAL);
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// set the first (and only channel in a conversion sequence)
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ADC1->SQR1 |= (2 << 6);
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// set the sampling rate to 12.5 ADC clock cycles
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ADC1->SMPR1 |= 0x2;
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// set continuous conversion
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ADC1->CFGR |= ADC_CFGR_CONT;
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// ignore overrun and overwrite data register content with new conversion result
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ADC1->CFGR |= ADC_CFGR_OVRMOD;
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// start ADC
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ADC1->CR |= ADC_CR_ADEN;
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// wait for startup
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while((ADC1->ISR & ADC_ISR_ADRDY) == 0);
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// start conversion
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ADC1->CR |= ADC_CR_ADSTART;
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ADC1->DR;
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#endif
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}
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void DACStartConfig(void) {
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#ifdef STM32F10X_MD_VL
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RCC->APB1ENR |= RCC_APB1ENR_DACEN; // wlanczenie zegara
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// rejestr CR przetownirka domyslnie ma same zera
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DAC->CR &= (0xFFFFFFFF ^ DAC_CR_WAVE1); // bez generowania przebiegu na wyjsciu
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DAC->CR |= DAC_CR_TSEL1; // programowe wyzwalanie przetwornika (przez flaga swtrig)
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DAC->CR |= DAC_CR_TEN1;
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DAC->CR |= DAC_CR_EN1;
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DAC->DHR8R1 = 10;
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DAC->SWTRIGR |= DAC_SWTRIGR_SWTRIG1;
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#endif
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#ifdef STM32L471xx
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// reset the clock for DAC
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RCC->APB1ENR1 &= (0xFFFFFFFF ^ RCC_APB1ENR1_DAC1EN);
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RCC->APB1ENR1 |= RCC_APB1ENR1_DAC1EN;
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DAC->CR |= DAC_CR_TSEL2;
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DAC->CR |= DAC_CR_TEN2;
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DAC->CR |= DAC_CR_EN2;
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DAC->SWTRIGR |= DAC_SWTRIGR_SWTRIG2;
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#endif
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}
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