kopia lustrzana https://github.com/SP8EBC/ParaTNC
spi expiremnts almost working
rodzic
7f5368ae08
commit
fd9ed99190
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@ -494,7 +494,6 @@
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</toolChain>
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</toolChain>
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</folderInfo>
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</folderInfo>
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<sourceEntries>
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<sourceEntries>
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<entry excluding="api" flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name="include"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="include/api"/>
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<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="include/api"/>
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<entry excluding="Timer.cpp" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src"/>
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<entry excluding="Timer.cpp" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="src"/>
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<entry excluding="src/newlib|src/drivers/f1|src/cmsis/vectors_stm32f10x.c|src/cmsis/system_stm32f10x.c|src/cortexm|src/stm32f1-stdperiph|src/stm32f1-stdperiph/stm32f10x_adc.c|src/stm32f1-stdperiph/stm32f10x_wwdg.c|src/drivers/tm_stm32fonewire/tm_stm32f1_onewire.c|src/stm32f1-stdperiph/stm32f10x_bkp.c|src/stm32f1-stdperiph/stm32f10x_dac.c|src/stm32f1-stdperiph/stm32f10x_can.c|src/stm32f1-stdperiph/stm32f10x_spi.c|src/stm32f1-stdperiph/stm32f10x_pwr.c|src/stm32f1-stdperiph/stm32f10x_sdio.c|src/stm32f1-stdperiph/stm32f10x_fsmc.c|src/stm32f1-stdperiph/stm32f10x_cec.c" flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name="system"/>
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<entry excluding="src/newlib|src/drivers/f1|src/cmsis/vectors_stm32f10x.c|src/cmsis/system_stm32f10x.c|src/cortexm|src/stm32f1-stdperiph|src/stm32f1-stdperiph/stm32f10x_adc.c|src/stm32f1-stdperiph/stm32f10x_wwdg.c|src/drivers/tm_stm32fonewire/tm_stm32f1_onewire.c|src/stm32f1-stdperiph/stm32f10x_bkp.c|src/stm32f1-stdperiph/stm32f10x_dac.c|src/stm32f1-stdperiph/stm32f10x_can.c|src/stm32f1-stdperiph/stm32f10x_spi.c|src/stm32f1-stdperiph/stm32f10x_pwr.c|src/stm32f1-stdperiph/stm32f10x_sdio.c|src/stm32f1-stdperiph/stm32f10x_fsmc.c|src/stm32f1-stdperiph/stm32f10x_cec.c" flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name="system"/>
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@ -105,7 +105,6 @@ void dallas_config_timer(void) {
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//NVIC_DisableIRQ( TIM3_IRQn ); // data transmission initializer
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//NVIC_DisableIRQ( TIM3_IRQn ); // data transmission initializer
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NVIC_DisableIRQ( TIM4_IRQn ); // data transmission initializer
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NVIC_DisableIRQ( TIM4_IRQn ); // data transmission initializer
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NVIC_DisableIRQ( TIM7_IRQn ); // data transmission initializer
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NVIC_DisableIRQ( TIM7_IRQn ); // data transmission initializer
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//NVIC_DisableIRQ( 25 ); // TODO: probably remainder of TX20 driver to be deleted
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dallas_delay_start();
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dallas_delay_start();
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@ -119,7 +118,6 @@ void dallas_deconfig_timer(void) {
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//NVIC_EnableIRQ( TIM3_IRQn ); // adc
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//NVIC_EnableIRQ( TIM3_IRQn ); // adc
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NVIC_EnableIRQ( TIM4_IRQn ); // data transmission initializer
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NVIC_EnableIRQ( TIM4_IRQn ); // data transmission initializer
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NVIC_EnableIRQ( TIM7_IRQn ); // data transmission initializer
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NVIC_EnableIRQ( TIM7_IRQn ); // data transmission initializer
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//NVIC_EnableIRQ( 25 ); // TODO: probably remainder of TX20 driver to be deleted
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dallas_delay_stop();
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dallas_delay_stop();
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//timm = 0;
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//timm = 0;
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@ -17,6 +17,7 @@
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#include <string.h>
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#include <string.h>
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#define SPI_CS_TO_SCLK_SETUP_DELAY 0x2FF
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#define SPI_BUFFER_LN 32
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#define SPI_BUFFER_LN 32
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/**
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/**
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@ -274,16 +275,18 @@ uint8_t spi_init_full_duplex_pio(spi_transfer_mode_t mode, spi_clock_polarity_st
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*
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*
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*
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*
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//#define SPI_CR1_CPHA_Pos (0U)
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//#define SPI_CR1_CPHA_Pos (0U)
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//#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
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//#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) //!< 0x00000001
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//#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
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//#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk //!<Clock Phase
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//#define SPI_CR1_CPOL_Pos (1U)
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//#define SPI_CR1_CPOL_Pos (1U)
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//#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
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//#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) //!< 0x00000002
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//#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
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//#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk //!<Clock Polarity
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uint8_t spi_rx_data(uint32_t slave_id, uint8_t * rx_buffer, uint16_t ln_to_rx) {
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uint8_t spi_rx_data(uint32_t slave_id, uint8_t * rx_buffer, uint16_t ln_to_rx) {
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return 0xFF;
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return 0xFF;
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}
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}
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*/
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/**
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/**
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* Initiate tx only transaction. Data will be sent to chosen slave, any receive data will be discarded
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* Initiate tx only transaction. Data will be sent to chosen slave, any receive data will be discarded
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*/
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*/
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@ -311,8 +314,6 @@ uint8_t spi_tx_data(uint32_t slave_id, uint8_t * tx_buffer, uint16_t ln_to_tx) {
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spi_current_slave = slave_id;
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spi_current_slave = slave_id;
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LL_GPIO_ResetOutputPin((GPIO_TypeDef *)spi_slaves_cfg[spi_current_slave - 1][1], spi_slaves_cfg[spi_current_slave - 1][2]);
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// if yes clear counter
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// if yes clear counter
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spi_current_tx_cntr = 0;
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spi_current_tx_cntr = 0;
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@ -345,7 +346,7 @@ uint8_t spi_tx_data(uint32_t slave_id, uint8_t * tx_buffer, uint16_t ln_to_tx) {
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spi_tx_bytes_rq = ln_to_tx;
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spi_tx_bytes_rq = ln_to_tx;
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}
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}
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spi_enable(0);
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spi_enable(1);
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}
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}
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}
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}
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else {
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else {
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@ -373,8 +374,6 @@ uint8_t spi_rx_tx_data(uint32_t slave_id, uint8_t * rx_buffer, uint8_t * tx_buff
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spi_current_slave = slave_id;
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spi_current_slave = slave_id;
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LL_GPIO_ResetOutputPin((GPIO_TypeDef *)spi_slaves_cfg[spi_current_slave - 1][1], spi_slaves_cfg[spi_current_slave - 1][2]);
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spi_current_rx_cntr = 0;
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spi_current_rx_cntr = 0;
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spi_current_tx_cntr = 0;
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spi_current_tx_cntr = 0;
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@ -443,7 +442,7 @@ uint8_t spi_rx_tx_data(uint32_t slave_id, uint8_t * rx_buffer, uint8_t * tx_buff
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spi_tx_state = SPI_TX_TXING;
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spi_tx_state = SPI_TX_TXING;
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// start trasmission
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// start trasmission
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spi_enable(0);
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spi_enable(1);
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}
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}
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else {
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else {
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// exit if either transmission or reception is ongoing
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// exit if either transmission or reception is ongoing
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@ -550,7 +549,10 @@ void spi_irq_handler(void) {
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SPI2->DR = spi_tx_buffer[spi_current_tx_cntr++];
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SPI2->DR = spi_tx_buffer[spi_current_tx_cntr++];
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}
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}
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else {
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else {
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while((SPI2->SR & SPI_SR_BSY) != 0); // blocking!!
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while((SPI2->SR & SPI_SR_BSY) != 0) { // blocking!!
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// clear RX fifo while rest of bytes are transmitted
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spi_garbage = SPI2->DR & 0xFF;
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}
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// finish transmission
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// finish transmission
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spi_tx_state = SPI_TX_DONE;
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spi_tx_state = SPI_TX_DONE;
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@ -650,6 +652,9 @@ void spi_timeout_handler(void) {
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void spi_enable(uint8_t cs_assert) {
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void spi_enable(uint8_t cs_assert) {
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// delay between asserting chip select and starting SPI
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volatile int delay = 0;
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SPI2->CR2 |= SPI_CR2_ERRIE;
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SPI2->CR2 |= SPI_CR2_ERRIE;
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SPI2->CR2 |= SPI_CR2_RXNEIE;
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SPI2->CR2 |= SPI_CR2_RXNEIE;
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SPI2->CR2 |= SPI_CR2_TXEIE;
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SPI2->CR2 |= SPI_CR2_TXEIE;
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@ -657,6 +662,8 @@ void spi_enable(uint8_t cs_assert) {
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if (cs_assert != 0) {
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if (cs_assert != 0) {
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LL_GPIO_ResetOutputPin((GPIO_TypeDef *)spi_slaves_cfg[spi_current_slave - 1][1], spi_slaves_cfg[spi_current_slave - 1][2]);
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LL_GPIO_ResetOutputPin((GPIO_TypeDef *)spi_slaves_cfg[spi_current_slave - 1][1], spi_slaves_cfg[spi_current_slave - 1][2]);
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// delay required by CS to SCLK Setup (MAX31865)
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for (delay = 0; delay < SPI_CS_TO_SCLK_SETUP_DELAY; delay++);
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}
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}
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LL_SPI_Enable(SPI2);
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LL_SPI_Enable(SPI2);
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