kopia lustrzana https://github.com/SP8EBC/ParaTNC
integration of hardffault logger
rodzic
5a0d2d666c
commit
a1d3cf6adc
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@ -12,6 +12,7 @@ C_SRCS += \
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../src/aprsis.c \
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../src/backup_registers.c \
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../src/button_parameteo.c \
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../src/debug_hardfault.c \
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../src/delay.c \
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../src/dummy.c \
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../src/event_log.c \
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@ -44,6 +45,7 @@ OBJS += \
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./src/aprsis.o \
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./src/backup_registers.o \
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./src/button_parameteo.o \
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./src/debug_hardfault.o \
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./src/delay.o \
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./src/dummy.o \
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./src/event_log.o \
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@ -76,6 +78,7 @@ C_DEPS += \
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./src/aprsis.d \
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./src/backup_registers.d \
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./src/button_parameteo.d \
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./src/debug_hardfault.d \
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./src/delay.d \
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./src/dummy.d \
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./src/event_log.d \
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@ -34,6 +34,16 @@
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#define MEMORY_MAP_EVENT_LOG_START 0x0805A800
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#define MEMORY_MAP_EVENT_LOG_END 0x0807CFFF
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#define MEMORY_MAP_FLASH_END FLASH_BANK1_END
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#define MEMORY_MAP_FLASH_END FLASH_BANK1_END
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#define MEMORY_MAP_SRAM1_NOINIT 0x10002000
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#define MEMORY_MAP_SRAM1_LOG_AREA_START MEMORY_MAP_SRAM1_NOINIT // RAM2_NOINIT (xrw) : ORIGIN = 0x10002000, LENGTH = 24K
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#define MEMORY_MAP_SRAM1_LOG_AREA_END (MEMORY_MAP_SRAM1_HFAULT_LOG_START - 1)
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#define MEMORY_MAP_SRAM1_HFAULT_LOG_32BWORDS_SIZE 12
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#define MEMORY_MAP_SRAM1_HFAULT_LOG_START (SRAM2_BASE + SRAM2_SIZE - sizeof(uint32_t) * MEMORY_MAP_SRAM1_HFAULT_LOG_32BWORDS_SIZE)
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#define MEMORY_MAP_SRAM1_HFAULT_LOG_END (SRAM2_BASE + SRAM2_SIZE - 1) // last byte, which could be read and write
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#endif /* MEMORY_MAP_H_ */
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@ -21,6 +21,7 @@
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/* Includes ------------------------------------------------------------------*/
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#include "main.h"
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#include "stm32l4xx_it.h"
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#include "debug_hardfault.h"
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/* Private includes ----------------------------------------------------------*/
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/* USER CODE BEGIN Includes */
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/* USER CODE END Includes */
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@ -87,6 +88,20 @@ void HardFault_Handler(void)
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{
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/* USER CODE BEGIN HardFault_IRQn 0 */
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__asm__("MOVS R0, #4");
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__asm__("MOV R1, LR");
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__asm__("TST R1, R0"); // Test LR (EXC_RETURN[2])
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__asm__("ITE NE");
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__asm__("MRSNE R1, PSP"); // EXC_RETURN[2] = 1
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__asm__("MRSEQ R1, MSP"); // EXC_RETURN[2] = 0
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__asm__("LDR R0, =debug_hardfault_stack_pointer_value");
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__asm__("STR R1, [R0]"); // Store PSP into stack_pointer
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DEBUG_STACKFRAME_STORE(debug_hardfault_stack_pointer_value, DEBUG_HARDFAULT_SOURCE_HFLT);
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DEBUG_STACKFRAME_CHECKSUM
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/* USER CODE END HardFault_IRQn 0 */
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while (1)
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{
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@ -103,6 +118,20 @@ void MemManage_Handler(void)
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{
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/* USER CODE BEGIN MemoryManagement_IRQn 0 */
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__asm__("MOVS R0, #4");
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__asm__("MOV R1, LR");
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__asm__("TST R1, R0"); // Test LR (EXC_RETURN[2])
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__asm__("ITE NE");
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__asm__("MRSNE R1, PSP"); // EXC_RETURN[2] = 1
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__asm__("MRSEQ R1, MSP"); // EXC_RETURN[2] = 0
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__asm__("LDR R0, =debug_hardfault_stack_pointer_value");
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__asm__("STR R1, [R0]"); // Store PSP into stack_pointer
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DEBUG_STACKFRAME_STORE(debug_hardfault_stack_pointer_value, DEBUG_HARDFAULT_SOURCE_MMUFLT);
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DEBUG_STACKFRAME_CHECKSUM
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/* USER CODE END MemoryManagement_IRQn 0 */
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while (1)
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{
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@ -119,6 +148,20 @@ void BusFault_Handler(void)
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{
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/* USER CODE BEGIN BusFault_IRQn 0 */
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__asm__("MOVS R0, #4");
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__asm__("MOV R1, LR");
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__asm__("TST R1, R0"); // Test LR (EXC_RETURN[2])
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__asm__("ITE NE");
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__asm__("MRSNE R1, PSP"); // EXC_RETURN[2] = 1
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__asm__("MRSEQ R1, MSP"); // EXC_RETURN[2] = 0
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__asm__("LDR R0, =debug_hardfault_stack_pointer_value");
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__asm__("STR R1, [R0]"); // Store PSP into stack_pointer
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DEBUG_STACKFRAME_STORE(debug_hardfault_stack_pointer_value, DEBUG_HARDFAULT_SOURCE_BUSFLT);
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DEBUG_STACKFRAME_CHECKSUM
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/* USER CODE END BusFault_IRQn 0 */
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while (1)
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{
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@ -135,6 +178,20 @@ void UsageFault_Handler(void)
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{
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/* USER CODE BEGIN UsageFault_IRQn 0 */
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__asm__("MOVS R0, #4");
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__asm__("MOV R1, LR");
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__asm__("TST R1, R0"); // Test LR (EXC_RETURN[2])
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__asm__("ITE NE");
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__asm__("MRSNE R1, PSP"); // EXC_RETURN[2] = 1
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__asm__("MRSEQ R1, MSP"); // EXC_RETURN[2] = 0
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__asm__("LDR R0, =debug_hardfault_stack_pointer_value");
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__asm__("STR R1, [R0]"); // Store PSP into stack_pointer
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DEBUG_STACKFRAME_STORE(debug_hardfault_stack_pointer_value, DEBUG_HARDFAULT_SOURCE_USAGEFLT);
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DEBUG_STACKFRAME_CHECKSUM
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/* USER CODE END UsageFault_IRQn 0 */
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while (1)
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{
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@ -222,6 +222,11 @@ void SystemInit(void)
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SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
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#endif
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/* Enable usage, bus and memory faults */
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SCB->SHCSR |= SCB_SHCSR_USGFAULTACT_Msk;
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SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk;
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SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set MSION bit */
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RCC->CR |= RCC_CR_MSION;
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