kopia lustrzana https://github.com/SP8EBC/ParaTNC
refactoring stop2 sleeping cycles to be handled in main loop in main function
Mateusz Lubecki
rodzic
b58f13a407
commit
6ca9151cae
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@ -48,7 +48,7 @@
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//#define INHIBIT_CUTOFF
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/**
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* Intermediate STOP2 cycle lenght within L7 or L6 mode.
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* Intermediate STOP2 cycle length within L7 or L6 mode.
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*/
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#define PWR_SAVE_STOP2_CYCLE_LENGHT_SEC 30u
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@ -117,7 +117,10 @@
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extern int8_t pwr_save_currently_cutoff;
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void pwr_save_init(config_data_powersave_mode_t mode);
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void pwr_save_enter_stop2(void);
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void pwr_save_after_stop2_rtc_wakeup_it(void);
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int pwr_save_check_stop2_cycles(void);
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void pwr_save_exit_after_last_stop2_cycle(void);
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int pwr_save_switch_mode_to_c0(void);
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int pwr_save_switch_mode_to_c1(void);
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void pwr_save_switch_mode_to_c2(void);
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@ -7,15 +7,15 @@
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#include "message.h"
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//!< Set immediately after waking up in RTC interrupt handler
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#define RTE_MAIN_WOKEN_UP_RTC_INTERRUPT 1u
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#define RTE_MAIN_WOKEN_UP_RTC_INTERRUPT 1u
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//!< Set after exiting from RTC interrupt, but before reinitializing clocks
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#define RTE_MAIN_WOKEN_UP_AFTER_RTC_IT 2u
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#define RTE_MAIN_WOKEN_UP_AFTER_LAST_SLEEP 2u
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//!< Set after everything was reinitialized from
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#define RTE_MAIN_WOKEN_UP_EXITED 4u
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#define RTE_MAIN_WOKEN_UP_EXITED 4u
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#define RTE_MAIN_GO_TO_SLEEP 8u
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#define RTE_MAIN_GO_TO_INTERMEDIATE_SLEEP 8u
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#define RTE_MAIN_REBOOT_SCHEDULED_APRSMSG 1u
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@ -45,6 +45,8 @@ extern uint8_t rte_main_trigger_radio_event_log;
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//!< Trigger some reinitialization after waking up from deep sleep
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extern uint8_t rte_main_woken_up;
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extern uint8_t rte_main_woken_up_for_telemetry;
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extern uint8_t rte_main_reboot_req;
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extern uint8_t rte_main_reboot_scheduled_diag;
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@ -8,8 +8,8 @@
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#ifndef SOFTWARE_VERSION_H_
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#define SOFTWARE_VERSION_H_
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#define SW_VER "EC03"
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#define SW_DATE "17102024"
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#define SW_VER "EC04"
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#define SW_DATE "21102024"
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#define SW_KISS_PROTO "C"
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extern const char software_version_str[5];
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45
src/main.c
45
src/main.c
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@ -7,7 +7,7 @@
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#include <drivers/f1/gpio_conf_stm32f1x.h>
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#endif
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#ifdef STM32L471xx
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#ifdef STM32L471xx /////////
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#include <stm32l4xx_hal_cortex.h>
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#include <stm32l4xx.h>
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#include <stm32l4xx_ll_iwdg.h>
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@ -37,7 +37,9 @@
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#include "ntp.h"
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#include "gsm_comm_state_handler.h"
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#endif
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#include "./etc/pwr_save_configuration.h"
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#endif ////////
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#include <delay.h>
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#include <LedConfig.h>
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@ -290,6 +292,8 @@ static uint8_t main_kiss_response_message[32];
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static io_vbat_state_t main_battery_measurement_res;
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static uint8_t main_continue_loop = 0;
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//!< Array to extract events from NVM into. *2 is applied to have more room for data sent to API
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static event_log_exposed_t main_exposed_events[MAIN_HOW_MANY_EVENTS_SEND_REPORT * 3];
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#endif
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@ -1521,13 +1525,29 @@ int main(int argc, char* argv[]){
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backup_reg_set_monitor(0);
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#if defined(PARAMETEO)
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if (rte_main_woken_up == RTE_MAIN_WOKEN_UP_RTC_INTERRUPT) {
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pwr_save_after_stop2_rtc_wakeup_it();
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}
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else if (rte_main_woken_up == RTE_MAIN_WOKEN_UP_AFTER_RTC_IT) {
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if (rte_main_woken_up == RTE_MAIN_GO_TO_INTERMEDIATE_SLEEP) {
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// this sleep is used by @link{pwr_save_after_stop2_rtc_wakeup_it} to
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// go to the intermediate sleep in L4 powersave mode, when xxx seconds
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// long sleep is divided into 'PWR_SAVE_STOP2_CYCLE_LENGHT_SEC' to
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// serwice IWDG in between
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system_clock_configure_auto_wakeup_l4(PWR_SAVE_STOP2_CYCLE_LENGHT_SEC);
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pwr_save_enter_stop2();
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}
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if (rte_main_woken_up == RTE_MAIN_WOKEN_UP_EXITED) {
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else if (rte_main_woken_up == RTE_MAIN_WOKEN_UP_RTC_INTERRUPT) {
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// controller is woken up from sleep in stop2 mode, now it must
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// be checked if this was the last sleep in the row, or micro
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// must go to sleep (stop2 mode) once again
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pwr_save_after_stop2_rtc_wakeup_it();
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}
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else if (rte_main_woken_up == RTE_MAIN_WOKEN_UP_AFTER_LAST_SLEEP) {
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system_clock_configure_l4();
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pwr_save_exit_after_last_stop2_cycle();
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rte_main_woken_up = RTE_MAIN_WOKEN_UP_EXITED;
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}
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else if (rte_main_woken_up == RTE_MAIN_WOKEN_UP_EXITED) {
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// restart ADCs
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io_vbat_meas_enable();
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@ -1555,6 +1575,8 @@ int main(int argc, char* argv[]){
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rte_main_woken_up = 0;
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rte_main_reset_gsm_modem = 1;
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main_check_adc = 1;
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// reinitialize UART used to communicate with GPRS modem
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@ -1562,9 +1584,6 @@ int main(int argc, char* argv[]){
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backup_reg_set_monitor(1);
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}
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else if (rte_main_woken_up == RTE_MAIN_GO_TO_SLEEP) {
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}
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else {
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#endif
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@ -2160,7 +2179,11 @@ int main(int argc, char* argv[]){
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// inhibit any power save switching when modem transmits data
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if (!main_afsk.sending && rte_main_woken_up == 0 && packet_tx_is_gsm_meteo_pending() == 0) {
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pwr_save_pooling_handler(main_config_data_mode, main_config_data_basic, packet_tx_get_minutes_to_next_wx(), rte_main_average_battery_voltage, rte_main_battery_voltage);
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pwr_save_pooling_handler(main_config_data_mode, main_config_data_basic, packet_tx_get_minutes_to_next_wx(), rte_main_average_battery_voltage, rte_main_battery_voltage, &main_continue_loop);
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}
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if (main_continue_loop == 0) {
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continue;
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}
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if ((main_config_data_mode->wx_dust_sensor & WX_DUST_SDS011_PWM) > 0) {
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298
src/pwr_save.c
298
src/pwr_save.c
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@ -132,11 +132,76 @@ static void pwr_save_clear_powersave_idication_bits() {
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pwr_save_lock_rtc_backup_regs();
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}
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/**
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* This function initializes everything related to power saving features
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* including programming Flash memory option bytes
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*/
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void pwr_save_init(config_data_powersave_mode_t mode) {
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// make a pointer to option byte
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uint32_t* option_byte = (uint32_t*)0x1FFF7800;
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// content of option byte read from the flash memory
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uint32_t option_byte_content = *option_byte;
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// definition of bitmask
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#define IWDG_STBY_STOP (0x3 << 17)
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// check if IWDG_STDBY and IWDG_STOP is set in ''User and read protection option bytes''
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// at 0x1FFF7800
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if ((option_byte_content & IWDG_STBY_STOP) != IWDG_STBY_STOP) {
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// unlock write/erase operations on flash memory
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FLASH->KEYR = 0x45670123;
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FLASH->KEYR = 0xCDEF89AB;
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// wait for any possible flash operation to finish (rather impossible here, but ST manual recommend doing this)
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while((FLASH->SR & FLASH_SR_BSY) != 0);
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// unlock operations on option bytes
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FLASH->OPTKEYR = 0x08192A3B;
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FLASH->OPTKEYR = 0x4C5D6E7F;
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// set the flash option register (in RAM!!)
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FLASH->OPTR |= FLASH_OPTR_IWDG_STDBY;
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FLASH->OPTR |= FLASH_OPTR_IWDG_STOP;
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// trigger an update of flash option bytes with values from RAM (from FLASH->OPTR)
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FLASH->CR |= FLASH_CR_OPTSTRT;
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// wait for option bytes to be updated
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while((FLASH->SR & FLASH_SR_BSY) != 0);
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// lock flash memory
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FLASH-> CR |= FLASH_CR_LOCK;
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// forcre reloading option bytes
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FLASH->CR |= FLASH_CR_OBL_LAUNCH;
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}
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// reset a status register
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backup_reg_reset_all_powersave_states();
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backup_reg_reset_inhibit_periodic_pwr_switch();
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// switch power switch handler inhibition if it is needed
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switch (mode) {
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case PWSAVE_NONE:
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break;
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case PWSAVE_NORMAL:
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case PWSAVE_AGGRESV:
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backup_reg_inhibit_periodic_pwr_switch();
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break;
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}
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}
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/**
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* Entering STOP2 power save mode. In this mode all clocks except LSI and LSE are disabled. StaticRAM content
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* is preserved, optionally GPIO and few other peripherals can be kept power up depending on configuration
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*/
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static void pwr_save_enter_stop2(void) {
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void pwr_save_enter_stop2(void) {
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// set 31st monitor bit
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backup_reg_set_monitor(31);
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@ -182,11 +247,89 @@ static void pwr_save_enter_stop2(void) {
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}
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/**
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* This function is called in two places within a pooler.
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* 1st: just after the micro wakes up from STOP2 deep sleep caused by low battery
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* voltage and returns from an interrupt
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* from RTC interrupt handler.
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* 2nd: just after the micro wakes up from STOP2 caues by aggressive powersave
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* configuration.
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*/
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void pwr_save_after_stop2_rtc_wakeup_it(void) {
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// if yes set curent state
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rte_main_woken_up = RTE_MAIN_WOKEN_UP_AFTER_LAST_SLEEP;
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// // check if this is an intermediate wakeup from STOP2
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// pwr_save_check_stop2_cycles();
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//
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// system_clock_configure_l4();
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//
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// pwr_save_exit_after_last_stop2_cycle();
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// reload internal watchdog
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main_reload_internal_wdg();
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// decrement stop2 cycles for current L7 or L6 powersave mode
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pwr_save_number_of_sleep_cycles--;
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// if there is time left to exit from depp sleep
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if (pwr_save_number_of_sleep_cycles > 0) {
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backup_reg_set_monitor(15);
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// // go back to sleep
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// // configure how long micro should sleep
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// system_clock_configure_auto_wakeup_l4(PWR_SAVE_STOP2_CYCLE_LENGHT_SEC);
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//
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// pwr_save_enter_stop2();
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rte_main_woken_up = RTE_MAIN_GO_TO_INTERMEDIATE_SLEEP;
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}
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else {
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backup_reg_set_monitor(14);
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rte_main_woken_up = RTE_MAIN_WOKEN_UP_AFTER_LAST_SLEEP;
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rte_main_woken_up_for_telemetry = 1;
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max31865_set_state_after_wkup(); // TODO: tatry variant
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}
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}
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/**
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* Used after each of 30 seconds long STOP2 sleep, to check
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* how many sleeps the micro must be put in, to complete
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* L6/L7 powersave mode
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*/
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//int pwr_save_check_stop2_cycles(void) {
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//
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// while(1) {
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// // decrement stop2 cycles for current L7 or L6 powersave mode
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// pwr_save_number_of_sleep_cycles--;
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//
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// // if there is time left to exit from depp sleep
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// if (pwr_save_number_of_sleep_cycles > 0) {
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// backup_reg_set_monitor(15);
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//
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// // go back to sleep
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// // configure how long micro should sleep
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// system_clock_configure_auto_wakeup_l4(PWR_SAVE_STOP2_CYCLE_LENGHT_SEC);
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//
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// pwr_save_enter_stop2();
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// }
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// else {
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// backup_reg_set_monitor(14);
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//
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// // we are done sleeping so exit from this loop
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// break;
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// }
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// }
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//}
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/**
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* This function has to be called after last 30 second long cycle of STOP2 sleep,
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* to bounce all frames transmission counters.
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*/
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static void pwr_save_exit_after_last_stop2_cycle(void) {
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void pwr_save_exit_after_last_stop2_cycle(void) {
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uint32_t counter = 0;
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@ -269,128 +412,6 @@ static void pwr_save_exit_after_last_stop2_cycle(void) {
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backup_reg_set_monitor(29);
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}
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/**
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* This function is called in two places within a pooler.
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* 1st: just after the micro wakes up from STOP2 deep sleep caused by low battery
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* voltage and returns from an interrupt
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* from RTC interrupt handler.
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* 2nd: just after the micro wakes up from STOP2 caues by aggressive powersave
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* configuration.
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*/
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static void pwr_save_after_stop2_rtc_wakeup_it(void) {
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// check if we are just after waking up from STOP2 mode
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if (rte_main_woken_up == RTE_MAIN_WOKEN_UP_RTC_INTERRUPT) {
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// if yes set curent state
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rte_main_woken_up = RTE_MAIN_WOKEN_UP_AFTER_RTC_IT;
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// check if this is an intermediate wakeup from STOP2
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pwr_save_check_stop2_cycles();
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system_clock_configure_l4();
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pwr_save_exit_after_last_stop2_cycle();
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rte_main_woken_up = RTE_MAIN_WOKEN_UP_EXITED;
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}
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}
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/**
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* This function initializes everything related to power saving features
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* including programming Flash memory option bytes
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*/
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void pwr_save_init(config_data_powersave_mode_t mode) {
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// make a pointer to option byte
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uint32_t* option_byte = (uint32_t*)0x1FFF7800;
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// content of option byte read from the flash memory
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uint32_t option_byte_content = *option_byte;
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// definition of bitmask
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#define IWDG_STBY_STOP (0x3 << 17)
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// check if IWDG_STDBY and IWDG_STOP is set in ''User and read protection option bytes''
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// at 0x1FFF7800
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if ((option_byte_content & IWDG_STBY_STOP) != IWDG_STBY_STOP) {
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// unlock write/erase operations on flash memory
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FLASH->KEYR = 0x45670123;
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FLASH->KEYR = 0xCDEF89AB;
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// wait for any possible flash operation to finish (rather impossible here, but ST manual recommend doing this)
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while((FLASH->SR & FLASH_SR_BSY) != 0);
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// unlock operations on option bytes
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FLASH->OPTKEYR = 0x08192A3B;
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FLASH->OPTKEYR = 0x4C5D6E7F;
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// set the flash option register (in RAM!!)
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FLASH->OPTR |= FLASH_OPTR_IWDG_STDBY;
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FLASH->OPTR |= FLASH_OPTR_IWDG_STOP;
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// trigger an update of flash option bytes with values from RAM (from FLASH->OPTR)
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FLASH->CR |= FLASH_CR_OPTSTRT;
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// wait for option bytes to be updated
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while((FLASH->SR & FLASH_SR_BSY) != 0);
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// lock flash memory
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FLASH-> CR |= FLASH_CR_LOCK;
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// forcre reloading option bytes
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FLASH->CR |= FLASH_CR_OBL_LAUNCH;
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}
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// reset a status register
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backup_reg_reset_all_powersave_states();
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backup_reg_reset_inhibit_periodic_pwr_switch();
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// switch power switch handler inhibition if it is needed
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switch (mode) {
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case PWSAVE_NONE:
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break;
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case PWSAVE_NORMAL:
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case PWSAVE_AGGRESV:
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backup_reg_inhibit_periodic_pwr_switch();
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break;
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}
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}
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/**
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* Used after each of 30 seconds long STOP2 sleep, to check
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* how many sleeps the micro must be put in, to complete
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* L6/L7 powersave mode
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*/
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int pwr_save_check_stop2_cycles(void) {
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while(1) {
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// decrement stop2 cycles for current L7 or L6 powersave mode
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pwr_save_number_of_sleep_cycles--;
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||||
|
||||
// if there is time left to exit from depp sleep
|
||||
if (pwr_save_number_of_sleep_cycles > 0) {
|
||||
backup_reg_set_monitor(15);
|
||||
|
||||
// go back to sleep
|
||||
// configure how long micro should sleep
|
||||
system_clock_configure_auto_wakeup_l4(PWR_SAVE_STOP2_CYCLE_LENGHT_SEC);
|
||||
|
||||
pwr_save_enter_stop2();
|
||||
}
|
||||
else {
|
||||
backup_reg_set_monitor(14);
|
||||
|
||||
// we are done sleeping so exit from this loop
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
int pwr_save_switch_mode_to_c0(void) {
|
||||
|
||||
|
|
@ -890,9 +911,11 @@ config_data_powersave_mode_t pwr_save_pooling_handler( const config_data_mode_t
|
|||
uint8_t * continue_loop) {
|
||||
// this function should be called from 10 seconds pooler
|
||||
|
||||
*continue_loop = 1;
|
||||
|
||||
int8_t reinit_sensors = 0;
|
||||
|
||||
int8_t reinit_gprs = 0;
|
||||
//int8_t reinit_gprs = 0;
|
||||
|
||||
packet_tx_counter_values_t counters;
|
||||
|
||||
|
|
@ -968,7 +991,8 @@ config_data_powersave_mode_t pwr_save_pooling_handler( const config_data_mode_t
|
|||
pwr_save_switch_mode_to_l7(60 * PWR_SAVE_CUTOFF_SLEEP_TIME_IN_MINUTES);
|
||||
|
||||
// RTC interrupt is between this call and previous one (switching to l7)
|
||||
pwr_save_after_stop2_rtc_wakeup_it();
|
||||
//pwr_save_after_stop2_rtc_wakeup_it();
|
||||
*continue_loop = 0;
|
||||
|
||||
return psave_mode;
|
||||
}
|
||||
|
|
@ -1117,8 +1141,10 @@ config_data_powersave_mode_t pwr_save_pooling_handler( const config_data_mode_t
|
|||
// if there is more than two minutes to send wx packet
|
||||
pwr_save_switch_mode_to_l7((timers->wx_transmit_period * 60) - (WAKEUP_PERIOD_BEFORE_WX_FRAME_IN_MINUTES * 60));
|
||||
|
||||
*continue_loop = 0;
|
||||
|
||||
// GSM module is kept turned on, but the connection must be reastablished
|
||||
reinit_gprs = 1;
|
||||
//reinit_gprs = 1;
|
||||
}
|
||||
else {
|
||||
// TODO: Workaround here for HW-RevB!!!
|
||||
|
|
@ -1163,7 +1189,9 @@ config_data_powersave_mode_t pwr_save_pooling_handler( const config_data_mode_t
|
|||
// if there is more than WAKEUP_PERIOD_BEFORE_WX_FRAME_IN_MINUTES minutes to wx packet
|
||||
pwr_save_switch_mode_to_l7((timers->wx_transmit_period * 60) - (WAKEUP_PERIOD_BEFORE_WX_FRAME_IN_MINUTES * 60)); // TODO: !!!
|
||||
|
||||
reinit_gprs = 1;
|
||||
*continue_loop = 0;
|
||||
|
||||
//reinit_gprs = 1;
|
||||
|
||||
}
|
||||
else {
|
||||
|
|
@ -1189,7 +1217,9 @@ config_data_powersave_mode_t pwr_save_pooling_handler( const config_data_mode_t
|
|||
// if there is more than WAKEUP_PERIOD_BEFORE_WX_FRAME_IN_MINUTES minutes to send wx packet
|
||||
pwr_save_switch_mode_to_l7((timers->wx_transmit_period * 60) - (WAKEUP_PERIOD_BEFORE_WX_FRAME_IN_MINUTES * 60));
|
||||
|
||||
reinit_gprs = 1;
|
||||
*continue_loop = 0;
|
||||
|
||||
//reinit_gprs = 1;
|
||||
}
|
||||
else {
|
||||
if (pwr_save_seconds_to_wx <= 30) {
|
||||
|
|
@ -1222,14 +1252,14 @@ config_data_powersave_mode_t pwr_save_pooling_handler( const config_data_mode_t
|
|||
|
||||
backup_reg_set_monitor(16);
|
||||
|
||||
pwr_save_after_stop2_rtc_wakeup_it();
|
||||
//pwr_save_after_stop2_rtc_wakeup_it();
|
||||
|
||||
backup_reg_set_monitor(13);
|
||||
|
||||
if (reinit_gprs != 0) {
|
||||
// reset GSM modem, internally this also check if GSM modem is inhibited or not
|
||||
rte_main_reset_gsm_modem = 1;
|
||||
}
|
||||
// if (reinit_gprs != 0) {
|
||||
// // reset GSM modem, internally this also check if GSM modem is inhibited or not
|
||||
// rte_main_reset_gsm_modem = 1;
|
||||
// }
|
||||
|
||||
if (reinit_sensors != 0) {
|
||||
// reinitialize all i2c sensors
|
||||
|
|
|
|||
|
|
@ -55,6 +55,8 @@ uint8_t rte_main_trigger_radio_event_log = 0;
|
|||
//!< Trigger some reinitialization after waking up from deep sleep
|
||||
uint8_t rte_main_woken_up = 0;
|
||||
|
||||
uint8_t rte_main_woken_up_for_telemetry = 0;
|
||||
|
||||
//!< Current battery voltage as 10mV increments
|
||||
uint16_t rte_main_battery_voltage;
|
||||
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue