kopia lustrzana https://github.com/pa3gsb/Radioberry-2.x
182 wiersze
7.0 KiB
Verilog
182 wiersze
7.0 KiB
Verilog
// megafunction wizard: %FIFO%
|
|
// GENERATION: STANDARD
|
|
// VERSION: WM1.0
|
|
// MODULE: dcfifo
|
|
|
|
// ============================================================
|
|
// File Name: rxLargeFIFO.v
|
|
// Megafunction Name(s):
|
|
// dcfifo
|
|
//
|
|
// Simulation Library Files(s):
|
|
// altera_mf
|
|
// ============================================================
|
|
// ************************************************************
|
|
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
|
//
|
|
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
|
|
// ************************************************************
|
|
|
|
|
|
//Copyright (C) 2017 Intel Corporation. All rights reserved.
|
|
//Your use of Intel Corporation's design tools, logic functions
|
|
//and other software and tools, and its AMPP partner logic
|
|
//functions, and any output files from any of the foregoing
|
|
//(including device programming or simulation files), and any
|
|
//associated documentation or information are expressly subject
|
|
//to the terms and conditions of the Intel Program License
|
|
//Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
//the Intel MegaCore Function License Agreement, or other
|
|
//applicable license agreement, including, without limitation,
|
|
//that your use is for the sole purpose of programming logic
|
|
//devices manufactured by Intel and sold by Intel or its
|
|
//authorized distributors. Please refer to the applicable
|
|
//agreement for further details.
|
|
|
|
|
|
// synopsys translate_off
|
|
`timescale 1 ps / 1 ps
|
|
// synopsys translate_on
|
|
module rxLargeFIFO (
|
|
aclr,
|
|
data,
|
|
rdclk,
|
|
rdreq,
|
|
wrclk,
|
|
wrreq,
|
|
q,
|
|
wrfull,
|
|
wrusedw);
|
|
|
|
input aclr;
|
|
input [47:0] data;
|
|
input rdclk;
|
|
input rdreq;
|
|
input wrclk;
|
|
input wrreq;
|
|
output [47:0] q;
|
|
output wrfull;
|
|
output [11:0] wrusedw;
|
|
`ifndef ALTERA_RESERVED_QIS
|
|
// synopsys translate_off
|
|
`endif
|
|
tri0 aclr;
|
|
`ifndef ALTERA_RESERVED_QIS
|
|
// synopsys translate_on
|
|
`endif
|
|
|
|
wire [47:0] sub_wire0;
|
|
wire sub_wire1;
|
|
wire [11:0] sub_wire2;
|
|
wire [47:0] q = sub_wire0[47:0];
|
|
wire wrfull = sub_wire1;
|
|
wire [11:0] wrusedw = sub_wire2[11:0];
|
|
|
|
dcfifo dcfifo_component (
|
|
.aclr (aclr),
|
|
.data (data),
|
|
.rdclk (rdclk),
|
|
.rdreq (rdreq),
|
|
.wrclk (wrclk),
|
|
.wrreq (wrreq),
|
|
.q (sub_wire0),
|
|
.wrfull (sub_wire1),
|
|
.wrusedw (sub_wire2),
|
|
.eccstatus (),
|
|
.rdempty (),
|
|
.rdfull (),
|
|
.rdusedw (),
|
|
.wrempty ());
|
|
defparam
|
|
dcfifo_component.intended_device_family = "Cyclone 10 LP",
|
|
dcfifo_component.lpm_numwords = 4096,
|
|
dcfifo_component.lpm_showahead = "OFF",
|
|
dcfifo_component.lpm_type = "dcfifo",
|
|
dcfifo_component.lpm_width = 48,
|
|
dcfifo_component.lpm_widthu = 12,
|
|
dcfifo_component.overflow_checking = "OFF",
|
|
dcfifo_component.rdsync_delaypipe = 11,
|
|
dcfifo_component.read_aclr_synch = "OFF",
|
|
dcfifo_component.underflow_checking = "OFF",
|
|
dcfifo_component.use_eab = "ON",
|
|
dcfifo_component.write_aclr_synch = "OFF",
|
|
dcfifo_component.wrsync_delaypipe = 11;
|
|
|
|
|
|
endmodule
|
|
|
|
// ============================================================
|
|
// CNX file retrieval info
|
|
// ============================================================
|
|
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
|
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
|
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
|
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
|
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
|
// Retrieval info: PRIVATE: Clock NUMERIC "4"
|
|
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
|
|
// Retrieval info: PRIVATE: Empty NUMERIC "0"
|
|
// Retrieval info: PRIVATE: Full NUMERIC "1"
|
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
|
|
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
|
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
|
|
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
|
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
|
|
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
|
|
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
|
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
|
|
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
|
// Retrieval info: PRIVATE: Width NUMERIC "48"
|
|
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
|
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
|
|
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
|
|
// Retrieval info: PRIVATE: output_width NUMERIC "48"
|
|
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
|
|
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
|
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
|
|
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
|
|
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
|
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
|
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
|
|
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
|
|
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
|
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
|
|
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
|
|
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
|
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
|
|
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "48"
|
|
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
|
|
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
|
|
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "11"
|
|
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
|
|
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
|
|
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
|
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
|
|
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "11"
|
|
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
|
|
// Retrieval info: USED_PORT: data 0 0 48 0 INPUT NODEFVAL "data[47..0]"
|
|
// Retrieval info: USED_PORT: q 0 0 48 0 OUTPUT NODEFVAL "q[47..0]"
|
|
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
|
|
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
|
|
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
|
|
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
|
|
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
|
|
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL "wrusedw[11..0]"
|
|
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
|
// Retrieval info: CONNECT: @data 0 0 48 0 data 0 0 48 0
|
|
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
|
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
|
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
|
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
|
// Retrieval info: CONNECT: q 0 0 48 0 @q 0 0 48 0
|
|
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
|
|
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL rxLargeFIFO.v TRUE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL rxLargeFIFO.inc FALSE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL rxLargeFIFO.cmp FALSE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL rxLargeFIFO.bsf FALSE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL rxLargeFIFO_inst.v FALSE
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL rxLargeFIFO_bb.v TRUE
|
|
// Retrieval info: LIB_FILE: altera_mf
|