kopia lustrzana https://github.com/pa3gsb/Radioberry-2.x
23 wiersze
402 B
Verilog
23 wiersze
402 B
Verilog
// create a pulse for the rising edge of a signal
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`timescale 1 ns/100 ps
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module pulsegen (
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input wire sig,
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input wire rst,
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input wire clk,
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output wire pulse);
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parameter TPD = 0.7;
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reg p1;
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always @(posedge clk)
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begin
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if (rst)
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p1 <= #TPD 1'b0;
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else
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p1 <= #TPD sig; // sig must be synchronous to clk
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end
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assign pulse = sig & !p1; // one clk wide signal at the rising edge of sig
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endmodule |