kopia lustrzana https://github.com/pa3gsb/Radioberry-2.x
197 wiersze
8.2 KiB
Plaintext
197 wiersze
8.2 KiB
Plaintext
VERSION: WM1.0
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MODULE: altpll
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PRIVATE: ACTIVECLK_CHECK STRING "0"
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PRIVATE: BANDWIDTH STRING "1.000"
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PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
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PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
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PRIVATE: BANDWIDTH_PRESET STRING "Low"
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PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
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PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
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PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
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PRIVATE: CLKLOSS_CHECK STRING "0"
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PRIVATE: CLKSWITCH_CHECK STRING "0"
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PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
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PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
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PRIVATE: CREATE_INCLK1_CHECK STRING "0"
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PRIVATE: CUR_DEDICATED_CLK STRING "c0"
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PRIVATE: CUR_FBIN_CLK STRING "c0"
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PRIVATE: DEVICE_SPEED_GRADE STRING "8"
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PRIVATE: DIV_FACTOR0 NUMERIC "1"
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PRIVATE: DIV_FACTOR1 NUMERIC "1"
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PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
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PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
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PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.192000"
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PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.030000"
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PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
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PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
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PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
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PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
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PRIVATE: GLOCKED_MODE_CHECK STRING "0"
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PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
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PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
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PRIVATE: INCLK0_FREQ_EDIT STRING "10.000"
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PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
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PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
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PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
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PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
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PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
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PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
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PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
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PRIVATE: LONG_SCAN_RADIO STRING "1"
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PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
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PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
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PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
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PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
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PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
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PRIVATE: MIRROR_CLK0 STRING "0"
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PRIVATE: MIRROR_CLK1 STRING "0"
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PRIVATE: MULT_FACTOR0 NUMERIC "1"
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PRIVATE: MULT_FACTOR1 NUMERIC "1"
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PRIVATE: NORMAL_MODE_RADIO STRING "1"
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PRIVATE: OUTPUT_FREQ0 STRING "0.19200000"
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PRIVATE: OUTPUT_FREQ1 STRING "0.03000000"
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PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
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PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
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PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
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PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
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PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
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PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
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PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
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PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
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PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
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PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
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PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
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PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
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PRIVATE: PLL_ARESET_CHECK STRING "0"
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PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
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PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
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PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
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PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
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PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
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PRIVATE: PLL_PFDENA_CHECK STRING "0"
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PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
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PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
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PRIVATE: RECONFIG_FILE STRING "PLL_IAMBIC.mif"
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PRIVATE: SACN_INPUTS_CHECK STRING "0"
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PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
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PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
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PRIVATE: SHORT_SCAN_RADIO STRING "0"
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PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
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PRIVATE: SPREAD_FREQ STRING "50.000"
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PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
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PRIVATE: SPREAD_PERCENT STRING "0.500"
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PRIVATE: SPREAD_USE STRING "0"
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PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
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PRIVATE: STICKY_CLK0 STRING "1"
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PRIVATE: STICKY_CLK1 STRING "1"
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PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
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PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
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PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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PRIVATE: USE_CLK0 STRING "1"
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PRIVATE: USE_CLK1 STRING "1"
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PRIVATE: USE_CLKENA0 STRING "0"
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PRIVATE: USE_CLKENA1 STRING "0"
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PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
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PRIVATE: ZERO_DELAY_RADIO STRING "0"
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LIBRARY: altera_mf altera_mf.altera_mf_components.all
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CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
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CONSTANT: CLK0_DIVIDE_BY NUMERIC "625"
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CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
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CONSTANT: CLK0_MULTIPLY_BY NUMERIC "12"
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CONSTANT: CLK0_PHASE_SHIFT STRING "0"
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CONSTANT: CLK1_DIVIDE_BY NUMERIC "1000"
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CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
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CONSTANT: CLK1_MULTIPLY_BY NUMERIC "3"
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CONSTANT: CLK1_PHASE_SHIFT STRING "0"
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CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
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CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "100000"
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CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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CONSTANT: LPM_TYPE STRING "altpll"
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CONSTANT: OPERATION_MODE STRING "NORMAL"
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CONSTANT: PLL_TYPE STRING "AUTO"
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CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
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CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
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CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
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CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
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CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
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CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
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CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
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CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
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CONSTANT: PORT_INCLK0 STRING "PORT_USED"
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CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
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CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
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CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
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CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
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CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
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CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
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CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
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CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
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CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
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CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
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CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
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CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
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CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
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CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
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CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
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CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
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CONSTANT: PORT_clk0 STRING "PORT_USED"
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CONSTANT: PORT_clk1 STRING "PORT_USED"
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CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
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CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
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CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
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CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
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CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
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CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
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CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
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CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
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CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
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CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
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CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
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CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
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CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
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CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
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CONSTANT: WIDTH_CLOCK NUMERIC "5"
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USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
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USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
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USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
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USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
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CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
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CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
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CONNECT: c0 0 0 0 0 @clk 0 0 1 0
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CONNECT: c1 0 0 0 0 @clk 0 0 1 1
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GEN_FILE: TYPE_NORMAL PLL_IAMBIC.v TRUE
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GEN_FILE: TYPE_NORMAL PLL_IAMBIC.ppf TRUE
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GEN_FILE: TYPE_NORMAL PLL_IAMBIC.inc FALSE
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GEN_FILE: TYPE_NORMAL PLL_IAMBIC.cmp FALSE
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GEN_FILE: TYPE_NORMAL PLL_IAMBIC.bsf FALSE
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GEN_FILE: TYPE_NORMAL PLL_IAMBIC_inst.v FALSE
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GEN_FILE: TYPE_NORMAL PLL_IAMBIC_bb.v TRUE
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LIB_FILE: altera_mf
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LICENSE_ID: "DEVICE_FAMILY_Cyclone 10 LP" 50816416A0382916223B
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LICENSE_ID: "DEVICE_FAMILY_Cyclone IV E" 50816416A0382916223A
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LICENSE_ID: "DEVICE_FAMILY_Cyclone V" 50816416I0382916223H
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LICENSE_ID: "DEVICE_FAMILY_Cyclone IV GX" 50816416A0382916223B
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LICENSE_ID: "FEATURE_STRATIXGX_DPA" 50816416O0382916223F
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LICENSE_ID: "FEATURE_STRATIXGX_BASIC" 50816416I0382916223H
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SUPPORTED_DEVICE_FAMILY: "Cyclone 10 LP"
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SUPPORTED_DEVICE_FAMILY: "Cyclone IV E"
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SUPPORTED_DEVICE_FAMILY: "Cyclone IV GX"
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SUPPORTED_DEVICE_FAMILY: "Cyclone III"
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WIZARD_TITLE: "ALTPLL"
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QUARTUS_VERSION: "Version 17.0"
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QUARTUS_SVERSION: "17.0.2 Build 602 07/19/2017 SJ Lite Edition:07/19/2017"
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QUARTUS_BUILD_DATE: "07/19/2017"
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ALTERA_COPYRIGHT: "Copyright (C) 2017 Intel Corporation. All rights reserved."
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HELP_MENU_ITEM: FALSE "IUG$altpll Megafunction User Guide$http://www.altera.com/literature/ug/ug_altpll.pdf"
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HELP_MENU_ITEM: FALSE "IUG$General-Purpose PLLs in Stratix (GX) Devices$http://www.altera.com/literature/hb/stx/ch_1_vol_2.pdf"
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HELP_MENU_ITEM: FALSE "IUG$PLLs in Stratix II Devices$http://www.altera.com/literature/hb/stx2/stx2_sii52001.pdf"
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HELP_MENU_ITEM: FALSE "IUG$Clock Networks and PLLs in Stratix III Devices$http://www.altera.com/literature/hb/stx3/stx3_siii51006.pdf "
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HELP_MENU_ITEM: FALSE "IUG$PLLs in Cyclone II Devices$http://www.altera.com/literature/hb/cyc2/cyc2_cii51007.pdf"
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