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wsprberry improvement

feature/ethernet
pa3gsb 2018-12-21 14:15:53 +01:00
rodzic 2e716135ac
commit cddb48d0ea
95 zmienionych plików z 18839 dodań i 3 usunięć
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8
WSPRBerry/WSPR/wsprberry.c
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@ -15,7 +15,7 @@
#include <unistd.h>
#define NRX 3 // number of wspr channels.
#define NRX 5 // number of wspr channels.
#define GAIN 2500 // Digital gain for input signals.
// UTC timing.... important for wspr mode! Starting at even minutes!
@ -24,6 +24,8 @@ struct tm *info;
//wsprnet.org
//Band Dial freq (MHz) Tx freq (MHz) Radioberry frequency (+ 1500)
// 0.136 0.137500
// 0.4742 0.475700
//160m 1.836600 1.838000 - 1.838200 1.838100
//80m 3.592600 3.594000 - 3.594200 3.594100
//60m 5.287200 5.288600 - 5.288800 5.288700
@ -35,7 +37,7 @@ struct tm *info;
//12m 24.924600 24.926000 - 24.926200 24.926100
//10m 28.124600 28.126000 - 28.126200 28.126100
int freqArray[4] = {7040100 , 3594100, 10140200 , 14097100 };
int freqArray[5] = {1838100, 3594100, 7040100 , 10140200 , 14097100 };
void record_WSPR_Channels(void);
static int spi_handler;
@ -117,7 +119,7 @@ void record_WSPR_Channels(void) {
if (nnrx % NRX == 0) {nnrx = 0;}
int freq = freqArray[nnrx];
iqdata[0] = (((nnrx << 2) & 0x0C) | (sampleSpeed & 0x03));
iqdata[0] = (((nnrx << 2) & 0x1C) | (sampleSpeed & 0x03));
iqdata[1] = (((rando << 6) & 0x40) | ((dither <<5) & 0x20) | (att & 0x1F));
iqdata[2] = ((freq >> 24) & 0xFF);
iqdata[3] = ((freq >> 16) & 0xFF);

14
WSPRBerry/readme.txt 100644
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The folder wsprberry-verilog-fpga contains the latest firmware for using wspr.
For the CL025 now it is possible to receive 5 channels
For the CL016 now it is possible to receive 3 channels
Pay attention :
HARDWARE MODIFICATION:
To make use of the new FIR filters which are working on double clock, reducing some FPGA resources a small hardware mod is required.
An additonal clock on pin 53 of the FPGA must be provided by connecting this to pin 69 of the FPGA (connected to the CLKOUT1 of the AD9866).
Using this clock a FPGA PLL circuit can be used to produce the right clock!
(required for the beta 2, 3 PCB, i will include the change in beta 4)

31
WSPRBerry/wsprberry-verilog-fpga/radioberry-10CL016.qpf 100644
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition
# Date created = 18:45:57 December 18, 2018
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "17.0"
DATE = "18:45:57 December 18, 2018"
# Revisions
PROJECT_REVISION = "radioberry-10CL016"

48
WSPRBerry/wsprberry-verilog-fpga/radioberry-10CL016.qsf 100644
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
# Date created = 18:38:26 August 16, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# radioberry_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files_cl_016
source ./tcl/general.tcl
set_global_assignment -name DEVICE 10CL016YE144C8G
source ./tcl/locations_radioberry_fd.tcl
source ./tcl/files.tcl
set_global_assignment -name TOP_LEVEL_ENTITY radioberry
set_global_assignment -name SDC_FILE sdc/radioberry.sdc
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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WSPRBerry/wsprberry-verilog-fpga/radioberry-10CL016.qws 100644
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WSPRBerry/wsprberry-verilog-fpga/radioberry.qpf 100644
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.2 Build 602 07/19/2017 SJ Lite Edition
# Date created = 18:53:52 October 16, 2018
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "17.0"
DATE = "18:53:52 October 16, 2018"
# Revisions
PROJECT_REVISION = "radioberry"

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WSPRBerry/wsprberry-verilog-fpga/radioberry.qsf 100644
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
# Date created = 18:38:26 August 16, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# radioberry_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name VERILOG_MACRO "wsprberry_cl025=1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files_cl_025
source ./tcl/general.tcl
set_global_assignment -name DEVICE 10CL025YE144C8G
source ./tcl/locations_radioberry_fd.tcl
source ./tcl/files.tcl
set_global_assignment -name TOP_LEVEL_ENTITY radioberry
set_global_assignment -name SDC_FILE sdc/radioberry.sdc
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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WSPRBerry/wsprberry-verilog-fpga/radioberry.qws 100644
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WSPRBerry/wsprberry-verilog-fpga/rtl/ad9866.v 100644
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//
// Hermes Lite
//
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// (C) Steve Haynal KF7O 2014, 2015, 2016
module ad9866 (
input reset,
input clk,
output reg sclk,
output sdio,
input sdo,
output reg sen_n,
output [7:0] dataout,
input ext_rx_rqst,
input [5:0] rx_gain,
input ext_tx_rqst,
input [5:0] tx_gain
);
parameter bit [0:19][8:0] initarray = {
// First bit is 1'b1 for write enable to that address
{1'b1,8'h80}, // Address 0x00, enable 4 wire SPI
{1'b0,8'h00}, // Address 0x01,
{1'b0,8'h00}, // Address 0x02,
{1'b0,8'h00}, // Address 0x03,
{1'b1,8'h36}, // Address 0x04,
{1'b0,8'h00}, // Address 0x05,
{1'b1,8'h14}, // Address 0x06,
{1'b1,8'h21}, // Address 0x07, Initiate DC offset calibration and RX filter on
{1'b1,8'h4b}, // Address 0x08, RX filter f-3db at ~34 MHz after scaling
{1'b1,8'h40}, // Address 0x09,
{1'b1,8'h40}, // Address 0x0a,
{1'b1,8'h00}, // Address 0x0b, RX gain only on PGA
{1'b1,8'h43}, // Address 0x0c, TX twos complement and interpolation factor
{1'b1,8'h03}, // Address 0x0d, RT twos complement
{1'b0,8'h01}, // Address 0x0e, Enable/Disable IAMP
{1'b0,8'h00}, // Address 0x0f,
{1'b0,8'h84}, // Address 0x10, Select TX gain
{1'b1,8'h00}, // Address 0x11, Select TX gain
{1'b0,8'h00}, // Address 0x12,
{1'b0,8'h00} // Address 0x13
};
reg [15:0] datain;
reg start;
reg [3:0] dut2_bitcount;
reg [0:0] dut2_state;
reg [15:0] dut2_data;
reg [5:0] dut1_pc;
logic [8:0] initarrayv;
// Init program counter
always @(posedge clk, posedge reset) begin: AD9866_DUT1_FSM
if (reset == 1'b1) begin
dut1_pc <= 6'h00;
end
else begin
if ((dut1_pc != 6'h3f) & sen_n) begin
dut1_pc <= (dut1_pc + 6'h01);
end
// Toggle LSB
else if ((dut1_pc == 6'h3f) & sen_n) begin
dut1_pc <= 6'h3e;
end
end
end
//(sen_n, dut1_pc, rx_gain, ext_rx_rqst, tx_gain, ext_tx_rqst)
always @(sen_n, dut1_pc, rx_gain, ext_rx_rqst, tx_gain, ext_tx_rqst) begin: AD9866_DUT1_COMB
if (ext_rx_rqst) begin
initarrayv = {2'b01,rx_gain};
datain = {8'h09,initarrayv[7:0]};
end
if (ext_tx_rqst) begin
initarrayv = {2'b01,tx_gain};
datain = {8'h0a,initarrayv[7:0]};
end
start = 1'b0;
if (sen_n) begin
if (dut1_pc[5:1] <= 6'h13) begin
if (dut1_pc[0] == 1'b0) begin
initarrayv = initarray[dut1_pc[5:1]];
datain = {3'h0,dut1_pc[5:1],initarrayv[7:0]};
start = initarrayv[8];
end
end else begin
// Send rx_gain code or tx_gain code
start = ext_rx_rqst || ext_tx_rqst;
end
end
end
assign dataout = dut2_data[8-1:0];
assign sdio = dut2_data[15];
// SPI state machine
always @(posedge clk, posedge reset) begin: AD9866_DUT2_FSM
if (reset == 1) begin
sen_n <= 1;
sclk <= 0;
dut2_state <= 1'b0;
dut2_data <= 0;
dut2_bitcount <= 0;
end
else begin
case (dut2_state)
1'b0: begin
sclk <= 0;
dut2_bitcount <= 15;
if (start) begin
dut2_data <= datain;
sen_n <= 0;
dut2_state <= 1'b1;
end
else begin
sen_n <= 1;
end
end
1'b1: begin
if ((!sclk)) begin
sclk <= 1;
end
else begin
dut2_data <= {dut2_data[15-1:0], sdo};
dut2_bitcount <= (dut2_bitcount - 1);
sclk <= 0;
if ((dut2_bitcount == 0)) begin
dut2_state <= 1'b0;
end
end
end
endcase
end
end
endmodule

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/ad9866pll.ppf 100644
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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone 10 LP" variation_name="ad9866pll" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="c2" direction="output" scope="external" source="clock" />
<pin name="c3" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/ad9866pll.qip 100644
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ad9866pll.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ad9866pll_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ad9866pll.ppf"]

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/ad9866pll.v 100644
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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: ad9866pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ad9866pll (
inclk0,
c0,
c1,
c2,
c3,
locked);
input inclk0;
output c0;
output c1;
output c2;
output c3;
output locked;
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire8;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [3:3] sub_wire7 = sub_wire3[3:3];
wire [2:2] sub_wire6 = sub_wire3[2:2];
wire [1:1] sub_wire5 = sub_wire3[1:1];
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire c1 = sub_wire5;
wire c2 = sub_wire6;
wire c3 = sub_wire7;
wire locked = sub_wire8;
altpll altpll_component (
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire8),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 2,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 5,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 16,
altpll_component.clk2_phase_shift = "0",
altpll_component.clk3_divide_by = 192,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 25,
altpll_component.clk3_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 13020,
altpll_component.intended_device_family = "Cyclone 10 LP",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=ad9866pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "76.800003"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "153.600006"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "245.759995"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "10.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "76.800"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "76.80000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "153.60000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "245.76000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "10.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "ad9866pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "16"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "192"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "13020"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ad9866pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ad9866pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ad9866pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ad9866pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ad9866pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ad9866pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ad9866pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

266
WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/ad9866pll_bb.v 100644
Wyświetl plik

@ -0,0 +1,266 @@
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: ad9866pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module ad9866pll (
inclk0,
c0,
c1,
c2,
c3,
locked);
input inclk0;
output c0;
output c1;
output c2;
output c3;
output locked;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "76.800003"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "153.600006"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "245.759995"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "10.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "76.800"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "76.80000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "153.60000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "245.76000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "10.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "ad9866pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "16"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "192"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "13020"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ad9866pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ad9866pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ad9866pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ad9866pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ad9866pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ad9866pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ad9866pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/commandFIFO.qip 100644
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set_global_assignment -name IP_TOOL_NAME "FIFO"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "commandFIFO.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "commandFIFO_bb.v"]

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/commandFIFO.v 100644
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// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: commandFIFO.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module commandFIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty);
input aclr;
input [47:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [47:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] sub_wire0;
wire sub_wire1;
wire [47:0] q = sub_wire0[47:0];
wire rdempty = sub_wire1;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.eccstatus (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone 10 LP",
dcfifo_component.lpm_numwords = 4,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 48,
dcfifo_component.lpm_widthu = 2,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 11,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 11;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "48"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "48"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "48"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "2"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "11"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "11"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 48 0 INPUT NODEFVAL "data[47..0]"
// Retrieval info: USED_PORT: q 0 0 48 0 OUTPUT NODEFVAL "q[47..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 48 0 data 0 0 48 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 48 0 @q 0 0 48 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL commandFIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL commandFIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL commandFIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL commandFIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL commandFIFO_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL commandFIFO_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/commandFIFO_bb.v 100644
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// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: commandFIFO.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module commandFIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty);
input aclr;
input [47:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [47:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "48"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "48"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "48"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "2"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "11"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "11"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 48 0 INPUT NODEFVAL "data[47..0]"
// Retrieval info: USED_PORT: q 0 0 48 0 OUTPUT NODEFVAL "q[47..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 48 0 data 0 0 48 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 48 0 @q 0 0 48 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL commandFIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL commandFIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL commandFIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL commandFIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL commandFIFO_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL commandFIFO_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/counter.qip 100644
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set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "counter.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "counter_bb.v"]

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/counter.v 100644
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// megafunction wizard: %LPM_COUNTER%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COUNTER
// ============================================================
// File Name: counter.v
// Megafunction Name(s):
// LPM_COUNTER
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module counter (
clock,
q);
input clock;
output [10:0] q;
wire [10:0] sub_wire0;
wire [10:0] q = sub_wire0[10:0];
lpm_counter LPM_COUNTER_component (
.clock (clock),
.q (sub_wire0),
.aclr (1'b0),
.aload (1'b0),
.aset (1'b0),
.cin (1'b1),
.clk_en (1'b1),
.cnt_en (1'b1),
.cout (),
.data ({11{1'b0}}),
.eq (),
.sclr (1'b0),
.sload (1'b0),
.sset (1'b0),
.updown (1'b1));
defparam
LPM_COUNTER_component.lpm_direction = "UP",
LPM_COUNTER_component.lpm_modulus = 1024,
LPM_COUNTER_component.lpm_port_updown = "PORT_UNUSED",
LPM_COUNTER_component.lpm_type = "LPM_COUNTER",
LPM_COUNTER_component.lpm_width = 11;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Direction NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
// Retrieval info: PRIVATE: ModulusValue NUMERIC "1024"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: nBit NUMERIC "11"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
// Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: q 0 0 11 0 OUTPUT NODEFVAL "q[10..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 11 0 @q 0 0 11 0
// Retrieval info: GEN_FILE: TYPE_NORMAL counter.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bb.v TRUE
// Retrieval info: LIB_FILE: lpm

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// megafunction wizard: %LPM_COUNTER%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COUNTER
// ============================================================
// File Name: counter.v
// Megafunction Name(s):
// LPM_COUNTER
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module counter (
clock,
q);
input clock;
output [10:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Direction NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
// Retrieval info: PRIVATE: ModulusValue NUMERIC "1024"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: nBit NUMERIC "11"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
// Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: q 0 0 11 0 OUTPUT NODEFVAL "q[10..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 11 0 @q 0 0 11 0
// Retrieval info: GEN_FILE: TYPE_NORMAL counter.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bb.v TRUE
// Retrieval info: LIB_FILE: lpm

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/rxFIFO.qip 100644
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set_global_assignment -name IP_TOOL_NAME "FIFO"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rxFIFO.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "rxFIFO_bb.v"]

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/rxFIFO.v 100644
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// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: rxFIFO.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rxFIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrempty);
input aclr;
input [47:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [47:0] q;
output wrempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [47:0] sub_wire0;
wire sub_wire1;
wire [47:0] q = sub_wire0[47:0];
wire wrempty = sub_wire1;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.wrempty (sub_wire1),
.eccstatus (),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone 10 LP",
dcfifo_component.lpm_numwords = 16,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 48,
dcfifo_component.lpm_widthu = 4,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 11,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 11;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "48"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "48"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "48"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "11"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "11"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 48 0 INPUT NODEFVAL "data[47..0]"
// Retrieval info: USED_PORT: q 0 0 48 0 OUTPUT NODEFVAL "q[47..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 48 0 data 0 0 48 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 48 0 @q 0 0 48 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/rxFIFO_bb.v 100644
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// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: rxFIFO.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module rxFIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrempty);
input aclr;
input [47:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [47:0] q;
output wrempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "48"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "48"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "48"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "11"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "11"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 48 0 INPUT NODEFVAL "data[47..0]"
// Retrieval info: USED_PORT: q 0 0 48 0 OUTPUT NODEFVAL "q[47..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 48 0 data 0 0 48 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 48 0 @q 0 0 48 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/sqroot.qip 100644
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set_global_assignment -name IP_TOOL_NAME "ALTSQRT"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sqroot.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sqroot_bb.v"]

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/sqroot.v 100644
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// megafunction wizard: %ALTSQRT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTSQRT
// ============================================================
// File Name: sqroot.v
// Megafunction Name(s):
// ALTSQRT
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sqroot (
clk,
radical,
q,
remainder);
input clk;
input [31:0] radical;
output [15:0] q;
output [16:0] remainder;
wire [15:0] sub_wire0;
wire [16:0] sub_wire1;
wire [15:0] q = sub_wire0[15:0];
wire [16:0] remainder = sub_wire1[16:0];
altsqrt ALTSQRT_component (
.clk (clk),
.radical (radical),
.q (sub_wire0),
.remainder (sub_wire1)
// synopsys translate_off
,
.aclr (),
.ena ()
// synopsys translate_on
);
defparam
ALTSQRT_component.pipeline = 100,
ALTSQRT_component.q_port_width = 16,
ALTSQRT_component.r_port_width = 17,
ALTSQRT_component.width = 32;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: PIPELINE NUMERIC "100"
// Retrieval info: CONSTANT: Q_PORT_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: R_PORT_WIDTH NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH NUMERIC "32"
// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: radical 0 0 32 0 INPUT NODEFVAL "radical[31..0]"
// Retrieval info: USED_PORT: remainder 0 0 17 0 OUTPUT NODEFVAL "remainder[16..0]"
// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0
// Retrieval info: CONNECT: @radical 0 0 32 0 radical 0 0 32 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: remainder 0 0 17 0 @remainder 0 0 17 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sqroot.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqroot.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqroot.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqroot.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqroot_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqroot_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

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// megafunction wizard: %ALTSQRT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTSQRT
// ============================================================
// File Name: sqroot.v
// Megafunction Name(s):
// ALTSQRT
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module sqroot (
clk,
radical,
q,
remainder);
input clk;
input [31:0] radical;
output [15:0] q;
output [16:0] remainder;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: PIPELINE NUMERIC "100"
// Retrieval info: CONSTANT: Q_PORT_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: R_PORT_WIDTH NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH NUMERIC "32"
// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: radical 0 0 32 0 INPUT NODEFVAL "radical[31..0]"
// Retrieval info: USED_PORT: remainder 0 0 17 0 OUTPUT NODEFVAL "remainder[16..0]"
// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0
// Retrieval info: CONNECT: @radical 0 0 32 0 radical 0 0 32 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: remainder 0 0 17 0 @remainder 0 0 17 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sqroot.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqroot.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqroot.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqroot.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqroot_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sqroot_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/square.qip 100644
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set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "square.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "square_bb.v"]

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/square.v 100644
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// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsquare
// ============================================================
// File Name: square.v
// Megafunction Name(s):
// altsquare
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module square (
clock,
dataa,
result);
input clock;
input [15:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
altsquare altsquare_component (
.clock (clock),
.data (dataa),
.result (sub_wire0),
.aclr (1'b0),
.ena (1'b1),
.sclr (1'b0));
defparam
altsquare_component.data_width = 16,
altsquare_component.lpm_type = "ALTSQUARE",
altsquare_component.pipeline = 100,
altsquare_component.representation = "SIGNED",
altsquare_component.result_width = 32;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "100"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "0"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "16"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "32"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: DATA_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "ALTSQUARE"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "100"
// Retrieval info: CONSTANT: REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: RESULT_WIDTH NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL square.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL square.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL square.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL square.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL square_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL square_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

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// megafunction wizard: %LPM_MULT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsquare
// ============================================================
// File Name: square.v
// Megafunction Name(s):
// altsquare
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module square (
clock,
dataa,
result);
input clock;
input [15:0] dataa;
output [31:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "100"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "0"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "16"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "32"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: DATA_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "ALTSQUARE"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "100"
// Retrieval info: CONSTANT: REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: RESULT_WIDTH NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL square.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL square.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL square.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL square.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL square_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL square_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/txFIFO.qip 100644
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set_global_assignment -name IP_TOOL_NAME "FIFO"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "txFIFO.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "txFIFO_bb.v"]

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/txFIFO.v 100644
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// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: txFIFO.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module txFIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output rdfull;
output [11:0] rdusedw;
output wrempty;
output wrfull;
output [11:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [11:0] sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire [11:0] sub_wire6;
wire [31:0] q = sub_wire0[31:0];
wire rdempty = sub_wire1;
wire rdfull = sub_wire2;
wire [11:0] rdusedw = sub_wire3[11:0];
wire wrempty = sub_wire4;
wire wrfull = sub_wire5;
wire [11:0] wrusedw = sub_wire6[11:0];
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdfull (sub_wire2),
.rdusedw (sub_wire3),
.wrempty (sub_wire4),
.wrfull (sub_wire5),
.wrusedw (sub_wire6),
.eccstatus ());
defparam
dcfifo_component.intended_device_family = "Cyclone 10 LP",
dcfifo_component.lpm_numwords = 4096,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 12,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 11,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 11;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "11"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "11"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL "rdusedw[11..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL "wrusedw[11..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL txFIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL txFIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL txFIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL txFIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL txFIFO_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL txFIFO_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

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WSPRBerry/wsprberry-verilog-fpga/rtl/cyclone_ip/txFIFO_bb.v 100644
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// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: txFIFO.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module txFIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull,
wrusedw);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output rdfull;
output [11:0] rdusedw;
output wrempty;
output wrfull;
output [11:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "11"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "11"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL "rdusedw[11..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL "wrusedw[11..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL txFIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL txFIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL txFIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL txFIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL txFIFO_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL txFIFO_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

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WSPRBerry/wsprberry-verilog-fpga/rtl/ddr_mux.v 100644
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//------------------------------------------------------------------------------
// Copyright (c) 2018 Johan Maas, PA3GSB
//
// With special thanks to Rene Meerman PA3GUQ!
//
// The input data (IQ sample 48 bits) is requested from the FIFO ; after each edge controlled
// by the firmware the data (8 bits) is provided to the output.
//------------------------------------------------------------------------------
module ddr_mux(
clk,
reset,
rd_req,
in_data,
out_data);
input clk;
input reset;
output rd_req;
input [47:0] in_data;
output [7:0] out_data;
reg[15:0] mux16;
reg[1:0] mux_sel;
reg[7:0] data_p;
reg[7:0] data_n;
always @(negedge clk)
begin
if (reset) begin
mux_sel <= 0;
rd_req <= 0;
end else begin
rd_req <= 0;
mux_sel <= mux_sel +1;
if (mux_sel == 2) begin
mux_sel <= 0;
rd_req <= 1;
end;
end
end
always @(mux_sel)
begin
case (mux_sel)
0: begin mux16 <= in_data[47:32]; end
1: begin mux16 <= in_data[31:16]; end
2: begin mux16 <= in_data[15: 0]; end
default:
mux16 <= 0;
endcase
end
always @(posedge clk)
begin
if (reset) begin
data_p <= 0;
end else begin
data_p <= mux16[15:8];
end
end
always @(negedge clk)
begin
if (reset) begin
data_n <= 0;
end else begin
data_n <= mux16[7:0];
end
end
assign out_data = (clk == 1) ? data_p : data_n;
endmodule

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WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/CicInterpM5.v 100644
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//
// HPSDR - High Performance Software Defined Radio
//
// Hermes code.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// Based on code by James Ahlstrom, N2ADR, (C) 2011
// Modified for use with HPSDR by Phil Harman, VK6PH, (C) 2013
// Interpolating CIC filter, order 5.
// Produce an output when clock_en is true. Output a strobe on req
// to request an input from the next filter.
module CicInterpM5(
input clock,
input clock_en, // enable an output sample
output reg req, // request the next input sample
input signed [IBITS-1:0] x_real, // input samples
input signed [IBITS-1:0] x_imag,
output signed [OBITS-1:0] y_real, // output samples
output signed [OBITS-1:0] y_imag
);
parameter RRRR = 320; // interpolation; limited by size of counter
parameter IBITS = 20; // input bits
parameter OBITS = 16; // output bits
parameter GBITS = 34; //log2(RRRR ** 4); // growth bits: growth is R**M / R
// Note: log2() rounds UP to the next integer - Not available in Verilog!
localparam CBITS = IBITS + GBITS; // calculation bits
reg [8:0] counter; // increase for higher maximum RRRR **** was [7:0]
reg signed [CBITS-1:0] x0, x1, x2, x3, x4, x5, dx0, dx1, dx2, dx3, dx4; // variables for comb, real
reg signed [CBITS-1:0] y1, y2, y3, y4, y5; // variables for integrator, real
reg signed [CBITS-1:0] q0, q1, q2, q3, q4, q5, dq0, dq1, dq2, dq3, dq4; // variables for comb, imag
reg signed [CBITS-1:0] s1, s2, s3, s4, s5; // variables for integrator, imag
wire signed [CBITS-1:0] sxtxr, sxtxi;
assign sxtxr = {{(CBITS - IBITS){x_real[IBITS-1]}}, x_real}; // sign extended
assign sxtxi = {{(CBITS - IBITS){x_imag[IBITS-1]}}, x_imag};
assign y_real = y5[CBITS-1 -:OBITS] + y5[(CBITS-1)-OBITS]; // output data with truncation to remove DC spur
assign y_imag = s5[CBITS-1 -:OBITS] + s5[(CBITS-1)-OBITS];
initial
begin
counter = 0;
req = 0;
end
always @(posedge clock)
begin
if (clock_en)
begin
// (x0, q0) -> comb -> (x5, q5) -> interpolate -> integrate -> (y5, s5)
if (counter == RRRR - 1)
begin // Process the sample (x0, q0) to get (x5, q5)
counter <= 1'd0;
x0 <= sxtxr;
q0 <= sxtxi;
req <= 1'd1;
// Comb for real data
x1 <= x0 - dx0;
x2 <= x1 - dx1;
x3 <= x2 - dx2;
x4 <= x3 - dx3;
x5 <= x4 - dx4;
dx0 <= x0;
dx1 <= x1;
dx2 <= x2;
dx3 <= x3;
dx4 <= x4;
// Comb for imaginary data
q1 <= q0 - dq0;
q2 <= q1 - dq1;
q3 <= q2 - dq2;
q4 <= q3 - dq3;
q5 <= q4 - dq4;
dq0 <= q0;
dq1 <= q1;
dq2 <= q2;
dq3 <= q3;
dq4 <= q4;
end
else
begin
counter <= counter + 1'd1;
x5 <= 0; // stuff a zero for (x5, q5)
q5 <= 0;
req <= 1'd0;
end
// Integrate the sample (x5, q5) to get the output (y5, s5)
// Integrator for real data; input is x5
y1 <= y1 + x5;
y2 <= y2 + y1;
y3 <= y3 + y2;
y4 <= y4 + y3;
y5 <= y5 + y4;
// Integrator for imaginary data; input is q5
s1 <= s1 + q5;
s2 <= s2 + s1;
s3 <= s3 + s2;
s4 <= s4 + s3;
s5 <= s5 + s4;
end
else
begin
req <= 1'd0;
end
end
endmodule

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WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/FirInterp5_1025_EER.v 100644
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//
// HPSDR - High Performance Software Defined Radio
//
// Hermes code.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// Based on code by James Ahlstrom, N2ADR, (C) 2011
// Modified for use with HPSDR by Phil Harman, VK6PH, (C) 2013
// Interpolate by 5 Polyphase FIR filter. Used by the EER code since no CIC compensation required.
// Produce an output when calc is strobed true. Output a strobe on req to request a new input sample.
// Input sample bits are 16 bits wide, outputs are 20 bits wide.
/*
Interpolate by 5 Polyphase filter.
The classic method of increasing the sampling rate of a system is to insert zeros between input samples.
In the case of interpolating by 5 the input data would look as follows:
X0,0,0,0,0,X1,0,0,0,0,X2....
Where Xn represents an input sample. The effect of adding the zero samples is to cause the output to
contain images centered on multiples of the original sample rate. So, we must also
filter this result down to the original bandwidth. Once we have done this, we have a signal at the
higher sample rate that only has frequency content within the original bandwidth.
Note that when we multiply the coefficients by the zero samples, they make zero contribution to the result.
Only the actual input samples, when multiplied by coefficients, contribute to the result. In which case these
are the only input samples that we need to process.
Let's call the coefficients C0, C1, C2, C3, .... So, when we enter an actual input sample,
the input samples (spaced 5 apart) get multiplied by C0, C5, C10, C15, ... to generate the first result ...
everything else is just zero. When we enter the next data sample, the existing input samples have shifted and
the non-zero results are generated by C1, C6, C11 ..... and so on.
The format of the Polyphase filter is as follows:
Input
+----+----+-----+ ........+
---|->| C0 | C5 | C10 | ........|----0 <------ Output
| +----+----+-----+ ........+
|
| +----+----+-----+ ........+
|->| C1 | C6 | C11 | ........|----0
| +----+----+-----+ ........+
|
| +----+----+-----+ ........+
|->| C2 | C7 | C12 | ........|----0
| +----+----+-----+ ........+
|
| +----+----+-----+ ........+
|->| C3 | C8 | C13 | ........|----0
| +----+----+-----+ ........+
|
| +----+----+-----+ ........+
|->| C4 | C9 | C14 | ........|----0
+----+----+-----+ ........+
Conceptually the filter operates as follows. Each input sample at 48ksps is fed to each FIR. When an output sample is
requested the input samples are mutlipled by the coefficients the output is pointing to. Hence for
each input sample there are 5 outputs.
As implemented, the input samples are stored in RAM. Each new sample is saved at the next RAM address. When an output
value is requested (by strobing calc) the samples in RAM are multiplied by the coefficients held in ROM. After each sample and coefficient
multiplication the RAM address is decremented and the ROM address incremented by 5. This is repeated until all the samples
have been multiplied by a coefficient.
Prior to the next request for an output value the ROM starting address is incremented by one. Hence for the first output
coefficients C0, C5, C10.... are used, for the second output coefficients C1, C6, C11....are used etc.
Once all 5 sets of coefficients have been processed a new input sample is requested.
*/
module FirInterp5_1025_EER(
input clock,
input calc, // calculate an output sample
output reg req, // request the next input sample
input signed [15:0] x_real, // input samples
input signed [15:0] x_imag,
output reg signed [OBITS-1:0] y_real, // output samples
output reg signed [OBITS-1:0] y_imag
);
parameter OBITS = 20; // output bits
parameter ABITS = 24; // adder bits
parameter NTAPS = 11'd1025; // number of filter taps, even by 5
parameter NTAPS_BITS = 11; // number of address bits for coefficient memory
reg [3:0] rstate; // state machine
parameter rWait = 0;
parameter rAddr = 1;
parameter rAddrA = 2;
parameter rAddrB = 3;
parameter rRun = 4;
parameter rDone = 5;
parameter rEnd1 = 6;
parameter rEnd2 = 7;
parameter rEnd3 = 8;
parameter rEnd4 = 9;
// We need memory for NTAPS / 5 = 205 samples saved in memory
reg [7:0] waddr, raddr; // write and read sample memory address
reg we; // write enable for samples
reg signed [ABITS-1:0] Raccum, Iaccum; // accumulators
wire [35:0] q; // I/Q sample read from memory
reg [35:0] reg_q;
wire signed [17:0] q_real, q_imag;
assign q_real = reg_q[35:18];
assign q_imag = reg_q[17:0];
reg [NTAPS_BITS-1:0] caddr; // read address for coefficient
wire signed [17:0] coef; // 18-bit coefficient read from memory
reg signed [17:0] reg_coef;
reg signed [35:0] Rmult, Imult; // multiplier result, 18 * 18
reg [2:0] phase; // count 0, 1, 2, 3, 4
reg [8:0] counter; // count NTAPS/5 samples + latency = 1025/5 + 1 = 206
initial
begin
rstate = rWait;
waddr = 0;
req = 0;
phase = 0;
end
//defparam rom.MifFile = "coefI5_1025_EER.mif"; Specified in MegaFunction.
firrom1_1025 rom (caddr, clock, coef); // coefficient ROM 18 bits X NTAPS
// sample RAM 36 bits X 205; 36 bit == 18 bits I and 18 bits Q
// sign extend the input samples; they remain at 16 bits
wire [35:0] sx_input;
assign sx_input = {x_real[15], x_real[15], x_real, x_imag[15], x_imag[15], x_imag};
firram36I_205 ramEER (clock, sx_input, raddr, waddr, we, q);
task next_addr; // increment address and register the next sample and coef
raddr <= raddr - 1'd1; // move to prior sample
caddr <= caddr + 11'd5; // move to next coefficient. Note caddr never gets to 1025, 1024 is the max
reg_q <= q;
reg_coef <= coef;
endtask
always @(posedge clock)
begin
case (rstate)
rWait:
begin
if (calc) // Wait until a new result is requested
begin
rstate <= rAddr;
raddr <= waddr; // read address -> newest sample
caddr <= phase; // start coefficient
counter <= NTAPS / 11'd5 + 11'd1; // count samples and pipeline latency
Raccum <= 1'd0;
Iaccum <= 1'd0;
Rmult <= 1'd0;
Imult <= 1'd0;
end
end
rAddr: // prime the memory pipeline
begin
rstate <= rAddrA;
next_addr;
end
rAddrA:
begin
rstate <= rAddrB;
next_addr;
end
rAddrB:
begin
rstate <= rRun;
next_addr;
end
rRun:
begin // main pipeline here
next_addr;
Rmult <= q_real * reg_coef;
Imult <= q_imag * reg_coef;
Raccum <= Raccum + Rmult[35:12] + Rmult[11]; // Add the most significant bits
Iaccum <= Iaccum + Imult[35:12] + Imult[11];
counter <= counter - 1'd1;
if (counter == 0) // count == 0 is never applied
begin
rstate <= rDone;
end
end
rDone:
begin
// Input samples were 16 bits in 18
// Coefficients were multiplied by 8
y_real <= Raccum[20:1] + Raccum[1]; // truncate to 20 bits to eliminate DC component
y_imag <= Iaccum[20:1] + Iaccum[1];
if (phase == 3'b100) begin // once we reach 4 restart
phase <= 3'd0;
rstate <= rEnd1;
end
else begin
rstate <= rWait;
phase <= phase + 1'd1;
end
end
rEnd1: // This was the last output sample for this input sample
begin
rstate <= rEnd2;
waddr <= waddr + 1'd1; // next write address
end
rEnd2:
begin
rstate <= rEnd3;
we <= 1'd1; // write current new sample at new address
end
rEnd3:
begin
rstate <= rEnd4;
we <= 1'd0;
req <= 1'd1; // request next sample
end
rEnd4:
begin
rstate <= rWait;
req <= 1'd0;
end
endcase
end
endmodule

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WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/FirInterp8_1024.v 100644
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//
// HPSDR - High Performance Software Defined Radio
//
// Hermes code.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// Based on code by James Ahlstrom, N2ADR, (C) 2011
// Modified for use with HPSDR by Phil Harman, VK6PH, (C) 2013
// Interpolate by 8 Polyphase FIR filter.
// Produce an output when calc is strobed true. Output a strobe on req
// to request a new input sample.
// Input sample bits are 16 bits wide.
/*
Interpolate by 8 Polyphase filter.
The classic method of increasing the sampling rate of a system is to insert zeros between input samples.
In the case of interpolating by 8 the input data would look as follows:
X0,0,0,0,0,0,0,0,X1,0,0,0,0,0,0,0,X2....
Where Xn represents an input sample. The effect of adding the zero samples is to cause the output to
contain images centered on multiples of the original sample rate. So, we must also
filter this result down to the original bandwidth. Once we have done this, we have a signal at the
higher sample rate that only has frequency content within the original bandwidth.
Note that when we multiply the coefficients by the zero samples, they make zero contribution to the result.
Only the actual input samples, when multiplied by coefficients, contribute to the result. In which case these
are the only input samples that we need to process.
Let's call the coefficients C0, C1, C2, C3, .... So, when we enter an actual input sample,
the input samples (spaced 8 apart) get multiplied by C0, C8, C16, C24, ... to generate the first result ...
everything else is just zero. When we enter the next data sample, the existing input samples have shifted and
the non-zero results are generated by C1, C9, C17 ..... and so on.
The format of the Polyphase filter is as follows:
Input
+----+----+-----+ ........+
---|->| C0 | C8 | C16 | ........|----0 <------ Output
| +----+----+-----+ ........+
|
| +----+----+-----+ ........+
|->| C1 | C9 | C17 | ........|----0
| +----+----+-----+ ........+
|
| +----+----+-----+ ........+
|->| C2 | C10| C18 | ........|----0
| +----+----+-----+ ........+
etc
| +----+----+-----+ ........+
|->| C7 | C15| C23 | ........|----0
| +----+----+-----+ ........+
Conceptually the filter operates as follows. Each input sample at 48ksps is fed to each FIR. When an output sample is
requested the input samples are mutlipled by the coefficients the output is pointing to. Hence for
each input sample there are 8 outputs.
As implemented, the input samples are stored in RAM. Each new sample is saved at the next RAM address. When an output
value is requested (by strobing calc) the samples in RAM are multiplied by the coefficients held in ROM. After each sample and coefficient
multiplication the RAM address is decremented and the ROM address incremented by 8. This is repeated until all the samples
have been multiplied by a coefficient.
Prior to the next request for an output value the ROM starting address is incremented by one. Hence for the first output
coefficients C0, C8, C16.... are used, for the second output coefficients C1, C9, C18....are used etc.
Once all 8 sets of coefficients have been processed a new input sample is requested.
*/
module FirInterp8_1024(
input clock,
input calc, // calculate an output sample
output reg req, // request the next input sample
input signed [15:0] x_real, // input samples
input signed [15:0] x_imag,
output reg signed [OBITS-1:0] y_real, // output samples
output reg signed [OBITS-1:0] y_imag
);
parameter OBITS = 20; // output bits
parameter ABITS = 24; // adder bits
parameter NTAPS = 11'd1024; // number of filter taps, even by 8, 1024-8 max
parameter NTAPS_BITS = 10; // number of address bits for coefficient memory
reg [3:0] rstate; // state machine
parameter rWait = 0;
parameter rAddr = 1;
parameter rAddrA = 2;
parameter rAddrB = 3;
parameter rRun = 4;
parameter rDone = 5;
parameter rEnd1 = 6;
parameter rEnd2 = 7;
parameter rEnd3 = 8;
parameter rEnd4 = 9;
// We need memory for NTAPS / 8 samples saved in memory
reg [6:0] waddr, raddr; // write and read sample memory address
reg we; // write enable for samples
reg signed [ABITS-1:0] Raccum, Iaccum; // accumulators
wire [35:0] q; // I/Q sample read from memory
reg [35:0] reg_q;
wire signed [17:0] q_real, q_imag;
assign q_real = reg_q[35:18];
assign q_imag = reg_q[17:0];
reg [NTAPS_BITS-1:0] caddr; // read address for coefficient
wire signed [17:0] coef; // 18-bit coefficient read from memory
reg signed [17:0] reg_coef;
reg signed [35:0] Rmult, Imult; // multiplier result
reg [2:0] phase; // count 0, 1, ..., 7
reg [9:0] counter; // count NTAPS/8 samples + latency
initial
begin
rstate = rWait;
waddr = 0;
req = 0;
phase = 0;
end
//`ifdef USE_ALTSYNCRAM
firromI_1024 #(.init_file("coefI8_1024.mif")) rom (caddr, clock, coef); // coefficient ROM 18 bits X NTAPS
//`else
// firromI_1024 #(.init_file("coefI8_1024.txt")) rom (caddr, clock, coef); // coefficient ROM 18 bits X NTAPS
//`endif
// sample RAM 36 bits X 128; 36 bit == 18 bits I and 18 bits Q
// sign extend the input samples; they remain at 16 bits
wire [35:0] sx_input;
assign sx_input = {x_real[15], x_real[15], x_real, x_imag[15], x_imag[15], x_imag};
firram36I_1024 ram (clock, sx_input, raddr, waddr, we, q);
task next_addr; // increment address and register the next sample and coef
raddr <= raddr - 1'd1; // move to prior sample
caddr <= caddr + 4'd8; // move to next coefficient
reg_q <= q;
reg_coef <= coef;
endtask
always @(posedge clock)
begin
case (rstate)
rWait:
begin
if (calc) // Wait until a new result is requested
begin
rstate <= rAddr;
raddr <= waddr; // read address -> newest sample
caddr <= phase; // start coefficient
counter <= NTAPS / 11'd8 + 1'd1; // count samples and pipeline latency
Raccum <= 1'd0;
Iaccum <= 1'd0;
Rmult <= 1'd0;
Imult <= 1'd0;
end
end
rAddr: // prime the memory pipeline
begin
rstate <= rAddrA;
next_addr;
end
rAddrA:
begin
rstate <= rAddrB;
next_addr;
end
rAddrB:
begin
rstate <= rRun;
next_addr;
end
rRun:
begin // main pipeline here
next_addr;
Rmult <= q_real * reg_coef;
Imult <= q_imag * reg_coef;
Raccum <= Raccum + Rmult[35:12] + Rmult[11]; // Add the most significant bits
Iaccum <= Iaccum + Imult[35:12] + Imult[11];
counter <= counter - 1'd1;
if (counter == 0)
begin
rstate <= rDone;
end
end
rDone:
begin
// Input samples were 16 bits in 18
// Coefficients were multiplied by 8
//y_real <= Raccum[(ABITS-1-3) -: OBITS];
//y_imag <= Iaccum[(ABITS-1-3) -: OBITS];
y_real <= Raccum[20:1] + Raccum[1]; // truncate to 20 bits to eliminate DC component
y_imag <= Iaccum[20:1] + Iaccum[1];
if (phase == 3'b111)
rstate <= rEnd1;
else
rstate <= rWait;
phase <= phase + 1'd1;
end
rEnd1: // This was the last output sample for this input sample
begin
rstate <= rEnd2;
waddr <= waddr + 1'd1; // next write address
end
rEnd2:
begin
rstate <= rEnd3;
we <= 1'd1; // write current new sample at new address
end
rEnd3:
begin
rstate <= rEnd4;
we <= 1'd0;
req <= 1'd1; // request next sample
end
rEnd4:
begin
rstate <= rWait;
req <= 1'd0;
end
endcase
end
endmodule

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WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/cic.v 100644
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/*
--------------------------------------------------------------------------------
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
License as published by the Free Software Foundation; either
version 2 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Library General Public License for more details.
You should have received a copy of the GNU Library General Public
License along with this library; if not, write to the
Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
Boston, MA 02110-1301, USA.
--------------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Copyright (c) 2008 Alex Shovkoplyas, VE3NEA
//------------------------------------------------------------------------------
// 2015 Jan 31 - udated for Hermes-Lite 12bit Steve Haynal KF7O
module cic( clock, in_strobe, out_strobe, in_data, out_data );
//design parameters
parameter STAGES = 3;
parameter DECIMATION = 10;
parameter IN_WIDTH = 18;
//computed parameters
//ACC_WIDTH = IN_WIDTH + Ceil(STAGES * Log2(DECIMATION))
//OUT_WIDTH = IN_WIDTH + Ceil(Log2(DECIMATION) / 2)
parameter ACC_WIDTH = IN_WIDTH + 10;
parameter OUT_WIDTH = IN_WIDTH + 2; // Hermes only uses ADC input width plus 2 here
input clock;
input in_strobe;
output reg out_strobe;
input signed [IN_WIDTH-1:0] in_data;
output signed [OUT_WIDTH-1:0] out_data;
//------------------------------------------------------------------------------
// control
//------------------------------------------------------------------------------
reg [15:0] sample_no = 0;
always @(posedge clock)
if (in_strobe)
begin
if (sample_no == (DECIMATION-1))
begin
sample_no <= 0;
out_strobe <= 1;
end
else
begin
sample_no <= sample_no + 8'd1;
out_strobe <= 0;
end
end
else
out_strobe <= 0;
//------------------------------------------------------------------------------
// stages
//------------------------------------------------------------------------------
wire signed [ACC_WIDTH-1:0] integrator_data [0:STAGES];
wire signed [ACC_WIDTH-1:0] comb_data [0:STAGES];
assign integrator_data[0] = in_data;
assign comb_data[0] = integrator_data[STAGES];
genvar i;
generate
for (i=0; i<STAGES; i=i+1)
begin : cic_stages
cic_integrator #(ACC_WIDTH) cic_integrator_inst(
.clock(clock),
.strobe(in_strobe),
.in_data(integrator_data[i]),
.out_data(integrator_data[i+1])
);
cic_comb #(ACC_WIDTH) cic_comb_inst(
.clock(clock),
.strobe(out_strobe),
.in_data(comb_data[i]),
.out_data(comb_data[i+1])
);
end
endgenerate
//------------------------------------------------------------------------------
// output rounding
//------------------------------------------------------------------------------
assign out_data = comb_data[STAGES][ACC_WIDTH-1:ACC_WIDTH-OUT_WIDTH] +
{{(OUT_WIDTH-1){1'b0}}, comb_data[STAGES][ACC_WIDTH-OUT_WIDTH-1]};
//assign out_data = comb_data[STAGES][36:19] + comb_data[STAGES][18];
endmodule

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WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/cic_comb.v 100644
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/*
--------------------------------------------------------------------------------
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
License as published by the Free Software Foundation; either
version 2 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Library General Public License for more details.
You should have received a copy of the GNU Library General Public
License along with this library; if not, write to the
Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
Boston, MA 02110-1301, USA.
--------------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Copyright (c) 2008 Alex Shovkoplyas, VE3NEA
//------------------------------------------------------------------------------
module cic_comb( clock, strobe, in_data, out_data );
parameter WIDTH = 64;
input clock;
input strobe;
input signed [WIDTH-1:0] in_data;
output reg signed [WIDTH-1:0] out_data;
reg signed [WIDTH-1:0] prev_data = 0;
always @(posedge clock)
if (strobe)
begin
out_data <= in_data - prev_data;
prev_data <= in_data;
end
endmodule

37
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/cic_integrator.v 100644
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/*
--------------------------------------------------------------------------------
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
License as published by the Free Software Foundation; either
version 2 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Library General Public License for more details.
You should have received a copy of the GNU Library General Public
License along with this library; if not, write to the
Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
Boston, MA 02110-1301, USA.
--------------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Copyright (c) 2008 Alex Shovkoplyas, VE3NEA
//------------------------------------------------------------------------------
module cic_integrator( clock, strobe, in_data, out_data );
parameter WIDTH = 64;
input clock;
input strobe;
input signed [WIDTH-1:0] in_data;
output reg signed [WIDTH-1:0] out_data = 0;
always @(posedge clock)
if (strobe) out_data <= out_data + in_data;
endmodule

1042
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/coefI5_1025_EER.mif 100644
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Plik diff jest za duży Load Diff

230
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/cordic.v 100644
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/*
--------------------------------------------------------------------------------
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
License as published by the Free Software Foundation; either
version 2 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Library General Public License for more details.
You should have received a copy of the GNU Library General Public
License along with this library; if not, write to the
Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
Boston, MA 02110-1301, USA.
--------------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Algorithm by Darrell Harmon modified by Cathy Moss
// Code Copyright (c) 2008 Alex Shovkoplyas, VE3NEA
//------------------------------------------------------------------------------
// 2015 Jan 31 - updated for Hermes-Lite 12bit Steve Haynal KF7O
module cordic( clock, frequency, in_data, out_data_I, out_data_Q );
parameter IN_WIDTH = 12; //ADC bitwidth
parameter EXTRA_BITS = 6; //spur reduction 6 dB per bit
//internal params
localparam WR = IN_WIDTH + EXTRA_BITS + 1; //18-bit data regs
localparam OUT_WIDTH = 18; //18-bit output width
localparam WZ = IN_WIDTH + EXTRA_BITS - 1; //16-bit angle regs
localparam STG = IN_WIDTH + EXTRA_BITS - 2; //15 stages
localparam WO = OUT_WIDTH;
localparam WF = 32; //NCO freq, -Pi..Pi per clock cycle
localparam WP = WF; //NCO phase, 0..2*Pi
input clock;
input signed [WF-1:0] frequency;
input signed [IN_WIDTH-1:0] in_data;
output signed [WO-1:0] out_data_I;
output signed [WO-1:0] out_data_Q;
//------------------------------------------------------------------------------
// arctan table
//------------------------------------------------------------------------------
localparam WT = 32;
wire signed [WT-1:0] atan_table [1:WT-1];
// atan_table[00] = 32'b01000000000000000000000000000000; //1073741824 FYI
assign atan_table[01] = 32'b00100101110010000000101000111011; //633866811
assign atan_table[02] = 32'b00010011111101100111000010110111; //334917815
assign atan_table[03] = 32'b00001010001000100010001110101000; //170009512
assign atan_table[04] = 32'b00000101000101100001101010000110; //85334662
assign atan_table[05] = 32'b00000010100010111010111111000011; //42708931
assign atan_table[06] = 32'b00000001010001011110110000111101; //21359677
assign atan_table[07] = 32'b00000000101000101111100010101010; //10680490
assign atan_table[08] = 32'b00000000010100010111110010100111; //5340327
assign atan_table[09] = 32'b00000000001010001011111001011101; //2670173
assign atan_table[10] = 32'b00000000000101000101111100110000; //1335088
assign atan_table[11] = 32'b00000000000010100010111110011000; //667544
assign atan_table[12] = 32'b00000000000001010001011111001100; //333772
assign atan_table[13] = 32'b00000000000000101000101111100110; //166886
assign atan_table[14] = 32'b00000000000000010100010111110011; //83443
assign atan_table[15] = 32'b00000000000000001010001011111010; //41722
assign atan_table[16] = 32'b00000000000000000101000101111101; //20861
assign atan_table[17] = 32'b00000000000000000010100010111110; //10430
assign atan_table[18] = 32'b00000000000000000001010001011111; //5215
assign atan_table[19] = 32'b00000000000000000000101000110000; //2608
assign atan_table[20] = 32'b00000000000000000000010100011000; //1304
assign atan_table[21] = 32'b00000000000000000000001010001100; //652
assign atan_table[22] = 32'b00000000000000000000000101000110; //326
assign atan_table[23] = 32'b00000000000000000000000010100011; //163
assign atan_table[24] = 32'b00000000000000000000000001010001; //81
assign atan_table[25] = 32'b00000000000000000000000000101001; //41
assign atan_table[26] = 32'b00000000000000000000000000010100; //20
assign atan_table[27] = 32'b00000000000000000000000000001010; //10
assign atan_table[28] = 32'b00000000000000000000000000000101; //5
assign atan_table[29] = 32'b00000000000000000000000000000011; //3
assign atan_table[30] = 32'b00000000000000000000000000000001; //1
assign atan_table[31] = 32'b00000000000000000000000000000001; //1
//------------------------------------------------------------------------------
// registers
//------------------------------------------------------------------------------
//NCO
reg [WP-1:0] phase = 0;
//stage outputs
reg signed [WR-1:0] X [0:STG-1];
reg signed [WR-1:0] Y [0:STG-1];
reg signed [WZ-1:0] Z [0:STG-1];
//------------------------------------------------------------------------------
// stage 0
//------------------------------------------------------------------------------
//input word sign-extended by 1 bit, padded at the right with EXTRA_BITS of zeros
wire signed [WR-1:0] in_data_ext = {in_data[IN_WIDTH-1], in_data, {EXTRA_BITS{1'b0}}};
wire [1:0] quadrant = phase[WP-1:WP-2];
always @(posedge clock)
begin
//rotate to the required quadrant, pre-rotate by +Pi/4. Gain = Sqrt(2)
case (quadrant)
0: begin X[0] <= in_data_ext; Y[0] <= in_data_ext; end
1: begin X[0] <= -in_data_ext; Y[0] <= in_data_ext; end
2: begin X[0] <= -in_data_ext; Y[0] <= -in_data_ext; end
3: begin X[0] <= in_data_ext; Y[0] <= -in_data_ext; end
endcase
//subtract quadrant and Pi/4 from the angle
Z[0] <= {~phase[WP-3], ~phase[WP-3], phase[WP-4:WP-WZ-1]};
if (frequency == 1'b0)
// For zero frequency, synchronize phase to other cordics.
phase <= 1'b0;
else
//advance NCO
phase <= phase + frequency;
end
//------------------------------------------------------------------------------
// stages 1 to STG-1
//------------------------------------------------------------------------------
genvar n;
generate
for (n=0; n<=(STG-2); n=n+1)
begin : stages
//data from prev stage, shifted
wire signed [WR-1:0] X_shr = {{(n+1){X[n][WR-1]}}, X[n][WR-1:n+1]};
wire signed [WR-1:0] Y_shr = {{(n+1){Y[n][WR-1]}}, Y[n][WR-1:n+1]};
//rounded arctan
wire [WZ-2-n:0] atan = atan_table[n+1][WT-2-n:WT-WZ] + atan_table[n+1][WT-WZ-1];
//the sign of the residual
wire Z_sign = Z[n][WZ-1-n];
always @(posedge clock)
begin
//add/subtract shifted and rounded data
X[n+1] <= Z_sign ? X[n] + Y_shr + Y[n][n] : X[n] - Y_shr - Y[n][n];
Y[n+1] <= Z_sign ? Y[n] - X_shr - X[n][n] : Y[n] + X_shr + X[n][n];
//update angle
if (n < STG-2)
begin : angles
Z[n+1][WZ-2-n:0] <= Z_sign ? Z[n][WZ-2-n:0] + atan : Z[n][WZ-2-n:0] - atan;
end
end
end
endgenerate
//------------------------------------------------------------------------------
// output
//------------------------------------------------------------------------------
generate
if (OUT_WIDTH == WR)
begin
assign out_data_I = X[STG-1];
assign out_data_Q = Y[STG-1];
end
else
begin
reg signed [WR-1:0] rounded_I = 0;
reg signed [WR-1:0] rounded_Q = 0;
always @(posedge clock)
begin
// rounded_I <= X[STG-1][WR-1 : WR-WO] +{{(WO-1){1'b0}}, X[STG-1][WR-1-WO]};
// rounded_Q <= Y[STG-1][WR-1 : WR-WO] +{{(WO-1){1'b0}}, Y[STG-1][WR-1-WO]};
// rounding from http://zipcpu.com/dsp/2017/07/22/rounding.html
rounded_I <= X[STG-1][WR-1 :0]
+ {{(WO){1'b0}},
X[STG-1][WR-WO],
{(WR-WO-1){!X[STG-1][WR-WO]}}};
rounded_Q <= Y[STG-1][WR-1 :0]
+ {{(WO){1'b0}},
Y[STG-1][WR-WO],
{(WR-WO-1){!Y[STG-1][WR-WO]}}};
end
assign out_data_I = rounded_I[WR-1:WR-WO];
assign out_data_Q = rounded_Q[WR-1:WR-WO];
end
endgenerate
endmodule

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/*
--------------------------------------------------------------------------------
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
License as published by the Free Software Foundation; either
version 2 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Library General Public License for more details.
You should have received a copy of the GNU Library General Public
License along with this library; if not, write to the
Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
Boston, MA 02110-1301, USA.
--------------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Algorithm by Darrell Harmon modified by Cathy Moss
// Code Copyright (c) 2009 Alex Shovkoplyas, VE3NEA
//------------------------------------------------------------------------------
module cpl_cordic(
input clock,
input signed [WF-1:0] frequency,
input signed [IN_WIDTH-1:0] in_data_I,
input signed [IN_WIDTH-1:0] in_data_Q,
output signed [WO-1:0] out_data_I,
output signed [WO-1:0] out_data_Q
);
parameter IN_WIDTH = 16; //ADC bitwidth
parameter EXTRA_BITS = 5; //spur reduction 6 dB per bit
parameter OUT_WIDTH = WR; //23-bit output width
//internal params
localparam WR = IN_WIDTH + EXTRA_BITS + 2; //23-bit data regs
localparam WZ = IN_WIDTH + EXTRA_BITS - 1; //20-bit angle regs
localparam STG = IN_WIDTH + EXTRA_BITS - 2; //19 stages
localparam WO = OUT_WIDTH;
localparam WF = 32; //NCO freq, -Pi..Pi per clock cycle
localparam WP = 32; //NCO phase, 0..2*Pi
//------------------------------------------------------------------------------
// arctan table
//------------------------------------------------------------------------------
localparam WT = 32;
wire signed [WT-1:0] atan_table [1:WT-1];
// atan_table[00] = 32'b01000000000000000000000000000000; //1073741824 FYI
assign atan_table[01] = 32'b00100101110010000000101000111011; //633866811
assign atan_table[02] = 32'b00010011111101100111000010110111; //334917815
assign atan_table[03] = 32'b00001010001000100010001110101000; //170009512
assign atan_table[04] = 32'b00000101000101100001101010000110; //85334662
assign atan_table[05] = 32'b00000010100010111010111111000011; //42708931
assign atan_table[06] = 32'b00000001010001011110110000111101; //21359677
assign atan_table[07] = 32'b00000000101000101111100010101010; //10680490
assign atan_table[08] = 32'b00000000010100010111110010100111; //5340327
assign atan_table[09] = 32'b00000000001010001011111001011101; //2670173
assign atan_table[10] = 32'b00000000000101000101111100110000; //1335088
assign atan_table[11] = 32'b00000000000010100010111110011000; //667544
assign atan_table[12] = 32'b00000000000001010001011111001100; //333772
assign atan_table[13] = 32'b00000000000000101000101111100110; //166886
assign atan_table[14] = 32'b00000000000000010100010111110011; //83443
assign atan_table[15] = 32'b00000000000000001010001011111010; //41722
assign atan_table[16] = 32'b00000000000000000101000101111101; //20861
assign atan_table[17] = 32'b00000000000000000010100010111110; //10430
assign atan_table[18] = 32'b00000000000000000001010001011111; //5215
assign atan_table[19] = 32'b00000000000000000000101000110000; //2608
assign atan_table[20] = 32'b00000000000000000000010100011000; //1304
assign atan_table[21] = 32'b00000000000000000000001010001100; //652
assign atan_table[22] = 32'b00000000000000000000000101000110; //326
assign atan_table[23] = 32'b00000000000000000000000010100011; //163
assign atan_table[24] = 32'b00000000000000000000000001010001; //81
assign atan_table[25] = 32'b00000000000000000000000000101001; //41
assign atan_table[26] = 32'b00000000000000000000000000010100; //20
assign atan_table[27] = 32'b00000000000000000000000000001010; //10
assign atan_table[28] = 32'b00000000000000000000000000000101; //5
assign atan_table[29] = 32'b00000000000000000000000000000011; //3
assign atan_table[30] = 32'b00000000000000000000000000000001; //1
assign atan_table[31] = 32'b00000000000000000000000000000001; //1
//------------------------------------------------------------------------------
// registers
//------------------------------------------------------------------------------
//NCO
reg [WP-1:0] phase = 0;
wire [1:0] quadrant = phase[WP-1:WP-2];
//stage outputs
reg signed [WR-1:0] X [0:STG-1];
reg signed [WR-1:0] Y [0:STG-1];
reg signed [WZ-1:0] Z [0:STG-1];
//------------------------------------------------------------------------------
// stage 0
//------------------------------------------------------------------------------
//input word sign-extended by 2 bits, padded at the right with EXTRA_BITS of zeros
wire signed [WR-1:0] in_data_I_ext = {{2{in_data_I[IN_WIDTH-1]}}, in_data_I, {EXTRA_BITS{1'b0}}};
wire signed [WR-1:0] in_data_Q_ext = {{2{in_data_Q[IN_WIDTH-1]}}, in_data_Q, {EXTRA_BITS{1'b0}}};
always @(posedge clock)
begin
//rotate to the required quadrant, pre-rotate by +Pi/4.
//the gain of this stage is 2.0, overall cordic gain is Sqrt(2)*1.647
case (quadrant)
0: begin X[0] <= in_data_I_ext - in_data_Q_ext; Y[0] <= in_data_I_ext + in_data_Q_ext; end
1: begin X[0] <= -in_data_I_ext - in_data_Q_ext; Y[0] <= in_data_I_ext - in_data_Q_ext; end
2: begin X[0] <= -in_data_I_ext + in_data_Q_ext; Y[0] <= -in_data_I_ext - in_data_Q_ext; end
3: begin X[0] <= in_data_I_ext + in_data_Q_ext; Y[0] <= -in_data_I_ext + in_data_Q_ext; end
endcase
//subtract quadrant and Pi/4 from the angle
Z[0] <= {~phase[WP-3], ~phase[WP-3], phase[WP-4:WP-WZ-1]};
//advance NCO
if (frequency == 1'b0)
// For zero frequency, synchronize phase to other cordics.
phase <= 1'b0;
else
//advance NCO
phase <= phase + frequency;
end
//------------------------------------------------------------------------------
// stages 1 to STG-1
//------------------------------------------------------------------------------
genvar n;
generate
for (n=0; n<=(STG-2); n=n+1)
begin : stages
//data from prev stage, shifted
wire signed [WR-1:0] X_shr = {{(n+1){X[n][WR-1]}}, X[n][WR-1:n+1]};
wire signed [WR-1:0] Y_shr = {{(n+1){Y[n][WR-1]}}, Y[n][WR-1:n+1]};
//rounded arctan
wire [WZ-2-n:0] atan = atan_table[n+1][WT-2-n:WT-WZ] + atan_table[n+1][WT-WZ-1];
//the sign of the residual
wire Z_sign = Z[n][WZ-1-n];
always @(posedge clock)
begin
//add/subtract shifted and rounded data
X[n+1] <= Z_sign ? X[n] + Y_shr + Y[n][n] : X[n] - Y_shr - Y[n][n];
Y[n+1] <= Z_sign ? Y[n] - X_shr - X[n][n] : Y[n] + X_shr + X[n][n];
//update angle
if (n < STG-2)
begin : angles
Z[n+1][WZ-2-n:0] <= Z_sign ? Z[n][WZ-2-n:0] + atan : Z[n][WZ-2-n:0] - atan;
end
end
end
endgenerate
//------------------------------------------------------------------------------
// output
//------------------------------------------------------------------------------
generate
if (OUT_WIDTH == WR)
begin
assign out_data_I = X[STG-1];
assign out_data_Q = Y[STG-1];
end
else
begin
reg signed [WO-1:0] rounded_I =0;
reg signed [WO-1:0] rounded_Q =0;
always @(posedge clock)
begin
rounded_I <= X[STG-1][WR-1 : WR-WO] + X[STG-1][WR-1-WO];
rounded_Q <= Y[STG-1][WR-1 : WR-WO] + Y[STG-1][WR-1-WO];
end
assign out_data_I = rounded_I;
assign out_data_Q = rounded_Q;
end
endgenerate
endmodule

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WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firfilt.v 100644
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//
// HPSDR - High Performance Software Defined Radio
//
// Hermes code.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// Polyphase decimating filter
// Based on firX8R8 by James Ahlstrom, N2ADR, (C) 2011
// Modified for use with HPSDR and DC spur removed by Phil Harman, VK6APH, (C) 2013
// This is a decimate by 8 Polyphase FIR filter. Since it decimates by 8 the output signal
// level will be 1/8 the input level. The filter coeficients are distributed between the 8
// FIR filters such that the first FIR receives coeficients 0, 7, 15... the second 1, 8, 16.. the
// third 2, 9, 17.. etc. The coeficients are calculated as per normal but there is no need to
// compensate for the sinx/x shape of the preceeding CIC filters. This is because the filter
// decimates by 8 and the droop of the CIC at 1/8th its fs/2 is neglibible.
// The filter coefficients are in the file "coefL8.txt". This is split into 8 individual
// Quartus ROM *.mif files.
// The filter coefficients are also attenuated such that the result of the multiply and accumalate
// does not exceed 24 bits.
// Note: Gain is higher than previous filter code by 6dB so reduce outside this module.
// FIR filters
//
// ROM init file: REQUIRED, with 256 or 512 coefficients. See below.
// Number of taps: NTAPS.
// Input bits: 18 fixed.
// Output bits: OBITS, default 24.
// Adder bits: ABITS, default 24.
// This requires eight MifFile's.
// Maximum NTAPS is 8 * (previous and current decimation) less overhead.
// Maximum NTAPS is 2048 (or less).
module firX8R8 (
input clock,
input clock_2x,
input x_avail, // new sample is available
input signed [MBITS-1:0] x_real, // x is the sample input
input signed [MBITS-1:0] x_imag,
output reg y_avail, // new output is available
output wire signed [OBITS-1:0] y_real, // y is the filtered output
output wire signed [OBITS-1:0] y_imag);
localparam ADDRBITS = 7; // Address bits for 18/36 X 256 rom/ram blocks
localparam MBITS = 18; // multiplier bits == input bits
parameter
TAPS = NTAPS / 8, // Must be even by 8
ABITS = 24, // adder bits
OBITS = 24, // output bits
NTAPS = 976; // number of filter taps, even by 8
reg [4:0] wstate; // state machine for write samples
reg [ADDRBITS-1:0] waddr; // write sample memory address
reg weA, weB, weC, weD, weE, weF, weG, weH;
reg signed [ABITS-1:0] Racc, Iacc;
wire signed [ABITS-1:0] RaccA, RaccB, RaccC, RaccD;
wire signed [ABITS-1:0] IaccA, IaccB, IaccC, IaccD;
wire banksel;
// Output is the result of adding 8 by 24 bit results so Racc and Iacc need to be
// 24 + log2(8) = 24 + 3 = 27 bits wide to prevent DC spur.
// However, since we decimate by 8 the output will be 1/8 the input. Hence we
// use 24 bits for the Accumulators.
assign y_real = Racc[ABITS-1:0];
assign y_imag = Iacc[ABITS-1:0];
initial
begin
wstate = 0;
waddr = 0;
end
always @(posedge clock)
begin
if (wstate == 8) wstate <= wstate + 1'd1; // used to set y_avail
if (wstate == 9) begin
wstate <= 0; // reset state machine and increment RAM write address
waddr <= waddr + 1'd1;
end
if (x_avail)
begin
wstate <= wstate + 1'd1;
case (wstate)
0: begin // wait for the first x input
Racc <= RaccA; // add accumulators
Iacc <= IaccA;
end
1: begin // wait for the next x input
Racc <= Racc + RaccB;
Iacc <= Iacc + IaccB;
end
2: begin
Racc <= Racc + RaccC;
Iacc <= Iacc + IaccC;
end
3: begin
Racc <= Racc + RaccD;
Iacc <= Iacc + IaccD;
end
4: begin
Racc <= Racc + RaccA;
Iacc <= Iacc + IaccA;
end
5: begin
Racc <= Racc + RaccB;
Iacc <= Iacc + IaccB;
end
6: begin
Racc <= Racc + RaccC;
Iacc <= Iacc + IaccC;
end
7: begin // wait for the last x input
Racc <= Racc + RaccD;
Iacc <= Iacc + IaccD;
end
endcase
end
end
// Enable each FIR in sequence
assign weA = (x_avail && wstate == 0);
assign weB = (x_avail && wstate == 1);
assign weC = (x_avail && wstate == 2);
assign weD = (x_avail && wstate == 3);
assign weE = (x_avail && wstate == 4);
assign weF = (x_avail && wstate == 5);
assign weG = (x_avail && wstate == 6);
assign weH = (x_avail && wstate == 7);
assign banksel = ~wstate[2];
// at end of sequence indicate new data is available
assign y_avail = (wstate == 8);
fir256 #(.ifile("coefL4AE.mif"), .ABITS(ABITS), .TAPS(TAPS)) AE (
.clock(clock_2x),
.waddr(waddr),
.ebanksel(banksel),
.ewe(weA|weE),
.x_real(x_real),
.x_imag(x_imag),
.Raccum(RaccA),
.Iaccum(IaccA)
);
fir256 #(.ifile("coefL4BF.mif"), .ABITS(ABITS), .TAPS(TAPS)) BF (
.clock(clock_2x),
.waddr(waddr),
.ebanksel(banksel),
.ewe(weB|weF),
.x_real(x_real),
.x_imag(x_imag),
.Raccum(RaccB),
.Iaccum(IaccB)
);
fir256 #(.ifile("coefL4CG.mif"), .ABITS(ABITS), .TAPS(TAPS)) CG (
.clock(clock_2x),
.waddr(waddr),
.ebanksel(banksel),
.ewe(weC|weG),
.x_real(x_real),
.x_imag(x_imag),
.Raccum(RaccC),
.Iaccum(IaccC)
);
fir256 #(.ifile("coefL4DH.mif"), .ABITS(ABITS), .TAPS(TAPS)) DH (
.clock(clock_2x),
.waddr(waddr),
.ebanksel(banksel),
.ewe(weD|weH),
.x_real(x_real),
.x_imag(x_imag),
.Raccum(RaccD),
.Iaccum(IaccD)
);
endmodule
// This filter waits until a new sample is written to memory at waddr. Then
// it starts by multiplying that sample by coef[0], the next prior sample
// by coef[1], (etc.) and accumulating. For R=8 decimation, coef[1] is the
// coeficient 8 prior to coef[0].
// When reading from the RAM we need to allow 3 clock pulses from presenting the
// read address until the data is available.
module fir256(
input clock,
input [ADDRBITS-1:0] waddr, // memory write address
input ebanksel,
input ewe, // memory write enable
input signed [MBITS-1:0] x_real, // sample to write
input signed [MBITS-1:0] x_imag,
output signed [ABITS-1:0] Raccum,
output signed [ABITS-1:0] Iaccum
);
localparam ADDRBITS = 7; // Address bits for 18/36 X 256 rom/ram blocks
localparam MBITS = 18; // multiplier bits == input bits
parameter ifile = "missing.txt"; // ROM coefficients
parameter ABITS = 0; // adder bits
parameter TAPS = 0; // number of filter taps, max 2**ADDRBITS
reg [ADDRBITS-1:0] raddr, caddr; // read address for sample and coef
wire [MBITS*2-1:0] q; // I/Q sample read from memory
reg [MBITS*2-1:0] reg_q;
wire signed [MBITS-1:0] q_real, q_imag; // I/Q sample read from memory
wire signed [MBITS-1:0] coef; // coefficient read from memory
reg signed [MBITS-1:0] reg_coef;
reg signed [MBITS*2-1:0] Rmult, Imult; // multiplier result
reg signed [MBITS*2-1:0] RmultSum, ImultSum; // multiplier result
reg [ADDRBITS:0] counter; // count TAPS samples
reg we = 1'b0; // Internal we on fast clock
reg banksel = 1'b0;
//wire [ADDRBITS-1:0] addr;
//reg fir_step; // Pipeline register for fir
always @(posedge clock) begin
if (ewe & ~we) begin
we <= 1'b1;
banksel <= ebanksel;
end
else we <= 1'b0;
end
assign q_real = reg_q[MBITS*2-1:MBITS];
assign q_imag = reg_q[MBITS-1:0];
firromH #(.init_file(ifile)) rom ( {banksel,caddr}, clock, coef); // coefficient ROM 18 X 256
//assign addr = we ? waddr : raddr;
firram36 ram (
.clock(clock),
.data({x_real, x_imag}),
.rdaddress({banksel,raddr}),
.wraddress({banksel,waddr}),
.wren(we),
.q(q)
);
always @(posedge clock)
begin
if (we) // Wait until a new sample is written to memory
begin
counter = TAPS[ADDRBITS:0] + 4; // count samples and pipeline latency (delay of 3 clocks from address being presented)
raddr = waddr; // read address -> newest sample
caddr = 1'd0; // start at coefficient zero
Raccum <= 0;
Iaccum <= 0;
Rmult <= 0;
Imult <= 0;
//fir_step <= 1'b1;
end
else
begin // main pipeline here
if (counter < (TAPS[ADDRBITS:0] + 2))
begin
//if (fir_step)
//begin
Rmult <= q_real * reg_coef;
Raccum <= Raccum + Rmult[35:12] + Rmult[11]; // truncate 36 bits down to 24 bits to prevent DC spur
//fir_step <= 1'b0;
//end
//else
//begin
Imult <= q_imag * reg_coef;
Iaccum <= Iaccum + Imult[35:12] + Imult[11];
//fir_step <= 1'b1;
//end
end
//if (~fir_step & (counter > 0))
if (counter > 0)
begin
counter <= counter - 1'd1;
raddr <= raddr - 1'd1; // move to prior sample
caddr <= caddr + 1'd1; // move to next coefficient
reg_q <= q;
reg_coef <= coef;
end
end
end
endmodule

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WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firram36.qip 100644
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set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "firram36.v"]

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WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firram36.v 100644
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// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: firram36.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module firram36 (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [35:0] data;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [35:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [35:0] sub_wire0;
wire [35:0] q = sub_wire0[35:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({36{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone 10 LP",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 36,
altsyncram_component.width_b = 36,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "9216"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "36"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "36"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "36"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "36"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "36"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 36 0 INPUT NODEFVAL "data[35..0]"
// Retrieval info: USED_PORT: q 0 0 36 0 OUTPUT NODEFVAL "q[35..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 36 0 data 0 0 36 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 36 0 @q_b 0 0 36 0
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

0
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firram36I_1024.qip 100644
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WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firram36I_1024.v 100644
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// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: firram36I_1024.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module firram36I_1024 (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [35:0] data;
input [6:0] rdaddress;
input [6:0] wraddress;
input wren;
output [35:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [35:0] sub_wire0;
wire [35:0] q = sub_wire0[35:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({36{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone 10 LP",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 128,
altsyncram_component.numwords_b = 128,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 7,
altsyncram_component.widthad_b = 7,
altsyncram_component.width_a = 36,
altsyncram_component.width_b = 36,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4608"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "36"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "36"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "36"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "36"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "36"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 36 0 INPUT NODEFVAL "data[35..0]"
// Retrieval info: USED_PORT: q 0 0 36 0 OUTPUT NODEFVAL "q[35..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 7 0 INPUT NODEFVAL "rdaddress[6..0]"
// Retrieval info: USED_PORT: wraddress 0 0 7 0 INPUT NODEFVAL "wraddress[6..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 7 0 wraddress 0 0 7 0
// Retrieval info: CONNECT: @address_b 0 0 7 0 rdaddress 0 0 7 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 36 0 data 0 0 36 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 36 0 @q_b 0 0 36 0
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36I_1024.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36I_1024.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36I_1024.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36I_1024.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36I_1024_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36I_1024_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

4
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firram36I_205.qip 100644
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@ -0,0 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "17.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "firram36I_205.v"]

214
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firram36I_205.v 100644
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// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: firram36I_205.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module firram36I_205 (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [35:0] data;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [35:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [35:0] sub_wire0;
wire [35:0] q = sub_wire0[35:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({36{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone 10 LP",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 205,
altsyncram_component.numwords_b = 205,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 36,
altsyncram_component.width_b = 36,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "7380"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "36"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "36"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "36"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "36"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "205"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "205"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "36"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 36 0 INPUT NODEFVAL "data[35..0]"
// Retrieval info: USED_PORT: q 0 0 36 0 OUTPUT NODEFVAL "q[35..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 36 0 data 0 0 36 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 36 0 @q_b 0 0 36 0
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36I_205.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36I_205.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36I_205.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36I_205.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36I_205_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firram36I_205_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

1031
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefI8_1024.mif 100644
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Plik diff jest za duży Load Diff

1057
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefI8_1024.py 100644
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Plik diff jest za duży Load Diff

1024
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefI8_1024.txt 100644
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Plik diff jest za duży Load Diff

1037
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL4.py 100644
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Plik diff jest za duży Load Diff

263
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL4AE.mif 100644
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DEPTH = 256;
WIDTH = 18;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT
BEGIN
00 : 3FFE5; -- -27 -26.86
01 : 3FF54; -- -172 -171.9
02 : 3FFE9; -- -23 -23.23
03 : 00030; -- 48 48.15
04 : 3FFCC; -- -52 -51.78
05 : 00034; -- 52 52.4
06 : 3FFCA; -- -54 -54.12
07 : 00039; -- 57 57.33
08 : 3FFC2; -- -62 -62.03
09 : 00044; -- 68 67.89
0A : 3FFB5; -- -75 -74.85
0B : 00053; -- 83 82.65
0C : 3FFA5; -- -91 -91.2
0D : 00064; -- 100 100.39
0E : 3FF92; -- -110 -110.22
0F : 00079; -- 121 120.59
10 : 3FF7D; -- -131 -131.45
11 : 0008F; -- 143 142.73
12 : 3FF66; -- -154 -154.43
13 : 000A6; -- 166 166.48
14 : 3FF4D; -- -179 -178.84
15 : 000BF; -- 191 191.44
16 : 3FF34; -- -204 -204.26
17 : 000D9; -- 217 217.25
18 : 3FF1A; -- -230 -230.35
19 : 000F3; -- 243 243.48
1A : 3FEFF; -- -257 -256.58
1B : 0010E; -- 270 269.6
1C : 3FEE6; -- -282 -282.48
1D : 00127; -- 295 295.08
1E : 3FECD; -- -307 -307.32
1F : 0013F; -- 319 319.1
20 : 3FEB6; -- -330 -330.35
21 : 00155; -- 341 340.96
22 : 3FEA1; -- -351 -350.84
23 : 00168; -- 360 359.87
24 : 3FE90; -- -368 -367.93
25 : 00177; -- 375 374.85
26 : 3FE84; -- -380 -380.43
27 : 00180; -- 384 384.48
28 : 3FE7D; -- -387 -386.85
29 : 00183; -- 387 387.31
2A : 3FE7E; -- -386 -385.61
2B : 0017D; -- 381 381.42
2C : 3FE8A; -- -374 -374.34
2D : 0016C; -- 364 363.85
2E : 3FEA3; -- -349 -349.37
2F : 0014A; -- 330 330.2
30 : 3FECF; -- -305 -305.44
31 : 00112; -- 274 273.75
32 : 3FF17; -- -233 -233.21
33 : 000B5; -- 181 181.19
34 : 3FF8E; -- -114 -113.89
35 : 00019; -- 25 25.43
36 : 0005E; -- 94 94.35
37 : 3FEF9; -- -263 -263.41
38 : 00205; -- 517 517.3
39 : 3FC57; -- -937 -937.39
3A : 006E5; -- 1765 1764.83
3B : 3EFCF; -- -4145 -4145.21
3C : 1428F; -- 82575 82574.73
3D : 0189C; -- 6300 6299.88
3E : 3F29F; -- -3425 -3425.2
3F : 009C6; -- 2502 2501.72
40 : 3F806; -- -2042 -2041.67
41 : 006E3; -- 1763 1763.3
42 : 3F9DA; -- -1574 -1573.96
43 : 0059B; -- 1435 1434.79
44 : 3FAD1; -- -1327 -1326.55
45 : 004D7; -- 1239 1238.71
46 : 3FB73; -- -1165 -1164.75
47 : 0044D; -- 1101 1100.62
48 : 3FBEC; -- -1044 -1043.73
49 : 003E0; -- 992 992.38
4A : 3FC4F; -- -945 -945.3
4B : 00385; -- 901 901.49
4C : 3FCA4; -- -860 -860.24
4D : 00335; -- 821 821.08
4E : 3FCF0; -- -784 -783.69
4F : 002EC; -- 748 747.8
50 : 3FD37; -- -713 -713.21
51 : 002A8; -- 680 679.73
52 : 3FD79; -- -647 -647.25
53 : 00268; -- 616 615.63
54 : 3FDB7; -- -585 -584.84
55 : 0022B; -- 555 554.86
56 : 3FDF2; -- -526 -525.69
57 : 001F1; -- 497 497.3
58 : 3FE2A; -- -470 -469.66
59 : 001BB; -- 443 442.76
5A : 3FE5F; -- -417 -416.6
5B : 00187; -- 391 391.17
5C : 3FE92; -- -366 -366.49
5D : 00157; -- 343 342.59
5E : 3FEC0; -- -320 -319.51
5F : 00129; -- 297 297.25
60 : 3FEEC; -- -276 -275.81
61 : 000FF; -- 255 255.19
62 : 3FF15; -- -235 -235.44
63 : 000D9; -- 217 216.54
64 : 3FF39; -- -199 -198.52
65 : 000B5; -- 181 181.34
66 : 3FF5B; -- -165 -165.03
67 : 00096; -- 150 149.6
68 : 3FF79; -- -135 -135.09
69 : 00079; -- 121 121.45
6A : 3FF93; -- -109 -108.71
6B : 00061; -- 97 96.9
6C : 3FFAA; -- -86 -86.06
6D : 0004C; -- 76 76.14
6E : 3FFBD; -- -67 -67.22
6F : 0003B; -- 59 59.32
70 : 3FFCB; -- -53 -52.57
71 : 0002F; -- 47 46.89
72 : 3FFD6; -- -42 -42.32
73 : 00026; -- 38 38.4
74 : 3FFDE; -- -34 -33.9
75 : 00017; -- 23 23.45
76 : 0000B; -- 11 11.29
77 : 3FF4E; -- -178 -178.04
78 : 3FFD7; -- -41 -41.39
79 : 00004; -- 4 4.08
7A : 00000;
7B : 00000;
7C : 00000;
7D : 00000;
7E : 00000;
7F : 00000;
80 : 00001; -- 1 1.17
81 : 3FF9C; -- -100 -100.32
82 : 3FF6A; -- -150 -149.71
83 : 00050; -- 80 80.21
84 : 3FFD0; -- -48 -47.8
85 : 00020; -- 32 32.01
86 : 3FFE8; -- -24 -24.03
87 : 00013; -- 19 19.3
88 : 3FFF0; -- -16 -15.93
89 : 0000D; -- 13 12.83
8A : 3FFF6; -- -10 -9.59
8B : 00006; -- 6 5.77
8C : 3FFFF; -- -1 -1.25
8D : 3FFFC; -- -4 -4.14
8E : 0000A; -- 10 10.44
8F : 3FFEE; -- -18 -17.82
90 : 0001A; -- 26 26.35
91 : 3FFDC; -- -36 -36.13
92 : 0002F; -- 47 47.19
93 : 3FFC4; -- -60 -59.68
94 : 0004A; -- 74 73.67
95 : 3FFA7; -- -89 -89.26
96 : 0006B; -- 107 106.52
97 : 3FF82; -- -126 -125.56
98 : 00093; -- 147 146.52
99 : 3FF56; -- -170 -169.53
9A : 000C3; -- 195 194.66
9B : 3FF22; -- -222 -222.08
9C : 000FC; -- 252 251.91
9D : 3FEE4; -- -284 -284.37
9E : 00140; -- 320 319.58
9F : 3FE9A; -- -358 -357.72
A0 : 0018F; -- 399 398.98
A1 : 3FE44; -- -444 -443.58
A2 : 001EC; -- 492 491.77
A3 : 3FDE0; -- -544 -543.86
A4 : 00258; -- 600 600.19
A5 : 3FD6B; -- -661 -661.2
A6 : 002D7; -- 727 727.32
A7 : 3FCE1; -- -799 -799.08
A8 : 0036D; -- 877 877.08
A9 : 3FC3E; -- -962 -962.12
AA : 0041F; -- 1055 1055.14
AB : 3FB7B; -- -1157 -1157.33
AC : 004F6; -- 1270 1270.15
AD : 3FA8D; -- -1395 -1395.45
AE : 00600; -- 1536 1535.52
AF : 3F963; -- -1693 -1693.34
B0 : 00751; -- 1873 1872.92
B1 : 3F7E0; -- -2080 -2079.75
B2 : 00911; -- 2321 2321.41
B3 : 3F5D0; -- -2608 -2608.46
B4 : 00B8C; -- 2956 2956.46
B5 : 3F2C3; -- -3389 -3389.32
B6 : 00F6A; -- 3946 3945.82
B7 : 3EDAC; -- -4692 -4692.33
B8 : 01679; -- 5753 5753.43
B9 : 3E31E; -- -7394 -7393.55
BA : 02833; -- 10291 10291.22
BB : 3BE24; -- -16860 -16859.67
BC : 0B656; -- 46678 46678.12
BD : 0E922; -- 59682 59681.81
BE : 3B99A; -- -18022 -18022.23
BF : 0291A; -- 10522 10521.57
C0 : 3E337; -- -7369 -7368.52
C1 : 015F9; -- 5625 5624.58
C2 : 3EE60; -- -4512 -4512.2
C3 : 00E9A; -- 3738 3737.57
C4 : 3F3A3; -- -3165 -3164.82
C5 : 00AA3; -- 2723 2722.5
C6 : 3F6BF; -- -2369 -2369.26
C7 : 00820; -- 2080 2079.8
C8 : 3F8D2; -- -1838 -1837.76
C9 : 00660; -- 1632 1632.02
CA : 3FA51; -- -1455 -1454.65
CB : 00514; -- 1300 1299.93
CC : 3FB74; -- -1164 -1163.7
CD : 00413; -- 1043 1042.86
CE : 3FC59; -- -935 -935.01
CF : 00346; -- 838 838.22
D0 : 3FD11; -- -751 -750.96
D1 : 002A0; -- 672 671.99
D2 : 3FDA8; -- -600 -600.31
D3 : 00217; -- 535 535.1
D4 : 3FE24; -- -476 -475.72
D5 : 001A6; -- 422 421.61
D6 : 3FE8C; -- -372 -372.28
D7 : 00147; -- 327 327.27
D8 : 3FEE2; -- -286 -286.21
D9 : 000F9; -- 249 248.75
DA : 3FF29; -- -215 -214.65
DB : 000B8; -- 184 183.64
DC : 3FF64; -- -156 -155.52
DD : 00082; -- 130 130.09
DE : 3FF95; -- -107 -107.18
DF : 00057; -- 87 86.58
E0 : 3FFBC; -- -68 -68.12
E1 : 00034; -- 52 51.65
E2 : 3FFDB; -- -37 -37.06
E3 : 00018; -- 24 24.2
E4 : 3FFF3; -- -13 -12.93
E5 : 00003; -- 3 3.12
E6 : 00005; -- 5 5.29
E7 : 3FFF4; -- -12 -12.43
E8 : 00012; -- 18 18.39
E9 : 3FFE9; -- -23 -23.31
EA : 0001B; -- 27 27.25
EB : 3FFE2; -- -30 -30.3
EC : 00021; -- 33 32.56
ED : 3FFDE; -- -34 -34.22
EE : 00023; -- 35 35.32
EF : 3FFDC; -- -36 -36.05
F0 : 00025; -- 37 36.59
F1 : 3FFDB; -- -37 -37.37
F2 : 00027; -- 39 38.81
F3 : 3FFD6; -- -42 -41.94
F4 : 00030; -- 48 48.33
F5 : 3FFC3; -- -61 -61.32
F6 : 00056; -- 86 85.67
F7 : 3FF83; -- -125 -124.78
F8 : 3FF86; -- -122 -121.96
F9 : 3FFFE; -- -2 -1.94
FA : 00000;
FB : 00000;
FC : 00000;
FD : 00000;
FE : 00000;
FF : 00000;
END;

256
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL4AE.txt 100644
Wyświetl plik

@ -0,0 +1,256 @@
111111111111100101 // -27 -26.86
111111111101010100 // -172 -171.9
111111111111101001 // -23 -23.23
000000000000110000 // 48 48.15
111111111111001100 // -52 -51.78
000000000000110100 // 52 52.4
111111111111001010 // -54 -54.12
000000000000111001 // 57 57.33
111111111111000010 // -62 -62.03
000000000001000100 // 68 67.89
111111111110110101 // -75 -74.85
000000000001010011 // 83 82.65
111111111110100101 // -91 -91.2
000000000001100100 // 100 100.39
111111111110010010 // -110 -110.22
000000000001111001 // 121 120.59
111111111101111101 // -131 -131.45
000000000010001111 // 143 142.73
111111111101100110 // -154 -154.43
000000000010100110 // 166 166.48
111111111101001101 // -179 -178.84
000000000010111111 // 191 191.44
111111111100110100 // -204 -204.26
000000000011011001 // 217 217.25
111111111100011010 // -230 -230.35
000000000011110011 // 243 243.48
111111111011111111 // -257 -256.58
000000000100001110 // 270 269.6
111111111011100110 // -282 -282.48
000000000100100111 // 295 295.08
111111111011001101 // -307 -307.32
000000000100111111 // 319 319.1
111111111010110110 // -330 -330.35
000000000101010101 // 341 340.96
111111111010100001 // -351 -350.84
000000000101101000 // 360 359.87
111111111010010000 // -368 -367.93
000000000101110111 // 375 374.85
111111111010000100 // -380 -380.43
000000000110000000 // 384 384.48
111111111001111101 // -387 -386.85
000000000110000011 // 387 387.31
111111111001111110 // -386 -385.61
000000000101111101 // 381 381.42
111111111010001010 // -374 -374.34
000000000101101100 // 364 363.85
111111111010100011 // -349 -349.37
000000000101001010 // 330 330.2
111111111011001111 // -305 -305.44
000000000100010010 // 274 273.75
111111111100010111 // -233 -233.21
000000000010110101 // 181 181.19
111111111110001110 // -114 -113.89
000000000000011001 // 25 25.43
000000000001011110 // 94 94.35
111111111011111001 // -263 -263.41
000000001000000101 // 517 517.3
111111110001010111 // -937 -937.39
000000011011100101 // 1765 1764.83
111110111111001111 // -4145 -4145.21
010100001010001111 // 82575 82574.73
000001100010011100 // 6300 6299.88
111111001010011111 // -3425 -3425.2
000000100111000110 // 2502 2501.72
111111100000000110 // -2042 -2041.67
000000011011100011 // 1763 1763.3
111111100111011010 // -1574 -1573.96
000000010110011011 // 1435 1434.79
111111101011010001 // -1327 -1326.55
000000010011010111 // 1239 1238.71
111111101101110011 // -1165 -1164.75
000000010001001101 // 1101 1100.62
111111101111101100 // -1044 -1043.73
000000001111100000 // 992 992.38
111111110001001111 // -945 -945.3
000000001110000101 // 901 901.49
111111110010100100 // -860 -860.24
000000001100110101 // 821 821.08
111111110011110000 // -784 -783.69
000000001011101100 // 748 747.8
111111110100110111 // -713 -713.21
000000001010101000 // 680 679.73
111111110101111001 // -647 -647.25
000000001001101000 // 616 615.63
111111110110110111 // -585 -584.84
000000001000101011 // 555 554.86
111111110111110010 // -526 -525.69
000000000111110001 // 497 497.3
111111111000101010 // -470 -469.66
000000000110111011 // 443 442.76
111111111001011111 // -417 -416.6
000000000110000111 // 391 391.17
111111111010010010 // -366 -366.49
000000000101010111 // 343 342.59
111111111011000000 // -320 -319.51
000000000100101001 // 297 297.25
111111111011101100 // -276 -275.81
000000000011111111 // 255 255.19
111111111100010101 // -235 -235.44
000000000011011001 // 217 216.54
111111111100111001 // -199 -198.52
000000000010110101 // 181 181.34
111111111101011011 // -165 -165.03
000000000010010110 // 150 149.6
111111111101111001 // -135 -135.09
000000000001111001 // 121 121.45
111111111110010011 // -109 -108.71
000000000001100001 // 97 96.9
111111111110101010 // -86 -86.06
000000000001001100 // 76 76.14
111111111110111101 // -67 -67.22
000000000000111011 // 59 59.32
111111111111001011 // -53 -52.57
000000000000101111 // 47 46.89
111111111111010110 // -42 -42.32
000000000000100110 // 38 38.4
111111111111011110 // -34 -33.9
000000000000010111 // 23 23.45
000000000000001011 // 11 11.29
111111111101001110 // -178 -178.04
111111111111010111 // -41 -41.39
000000000000000100 // 4 4.08
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000001 // 1 1.17
111111111110011100 // -100 -100.32
111111111101101010 // -150 -149.71
000000000001010000 // 80 80.21
111111111111010000 // -48 -47.8
000000000000100000 // 32 32.01
111111111111101000 // -24 -24.03
000000000000010011 // 19 19.3
111111111111110000 // -16 -15.93
000000000000001101 // 13 12.83
111111111111110110 // -10 -9.59
000000000000000110 // 6 5.77
111111111111111111 // -1 -1.25
111111111111111100 // -4 -4.14
000000000000001010 // 10 10.44
111111111111101110 // -18 -17.82
000000000000011010 // 26 26.35
111111111111011100 // -36 -36.13
000000000000101111 // 47 47.19
111111111111000100 // -60 -59.68
000000000001001010 // 74 73.67
111111111110100111 // -89 -89.26
000000000001101011 // 107 106.52
111111111110000010 // -126 -125.56
000000000010010011 // 147 146.52
111111111101010110 // -170 -169.53
000000000011000011 // 195 194.66
111111111100100010 // -222 -222.08
000000000011111100 // 252 251.91
111111111011100100 // -284 -284.37
000000000101000000 // 320 319.58
111111111010011010 // -358 -357.72
000000000110001111 // 399 398.98
111111111001000100 // -444 -443.58
000000000111101100 // 492 491.77
111111110111100000 // -544 -543.86
000000001001011000 // 600 600.19
111111110101101011 // -661 -661.2
000000001011010111 // 727 727.32
111111110011100001 // -799 -799.08
000000001101101101 // 877 877.08
111111110000111110 // -962 -962.12
000000010000011111 // 1055 1055.14
111111101101111011 // -1157 -1157.33
000000010011110110 // 1270 1270.15
111111101010001101 // -1395 -1395.45
000000011000000000 // 1536 1535.52
111111100101100011 // -1693 -1693.34
000000011101010001 // 1873 1872.92
111111011111100000 // -2080 -2079.75
000000100100010001 // 2321 2321.41
111111010111010000 // -2608 -2608.46
000000101110001100 // 2956 2956.46
111111001011000011 // -3389 -3389.32
000000111101101010 // 3946 3945.82
111110110110101100 // -4692 -4692.33
000001011001111001 // 5753 5753.43
111110001100011110 // -7394 -7393.55
000010100000110011 // 10291 10291.22
111011111000100100 // -16860 -16859.67
001011011001010110 // 46678 46678.12
001110100100100010 // 59682 59681.81
111011100110011010 // -18022 -18022.23
000010100100011010 // 10522 10521.57
111110001100110111 // -7369 -7368.52
000001010111111001 // 5625 5624.58
111110111001100000 // -4512 -4512.2
000000111010011010 // 3738 3737.57
111111001110100011 // -3165 -3164.82
000000101010100011 // 2723 2722.5
111111011010111111 // -2369 -2369.26
000000100000100000 // 2080 2079.8
111111100011010010 // -1838 -1837.76
000000011001100000 // 1632 1632.02
111111101001010001 // -1455 -1454.65
000000010100010100 // 1300 1299.93
111111101101110100 // -1164 -1163.7
000000010000010011 // 1043 1042.86
111111110001011001 // -935 -935.01
000000001101000110 // 838 838.22
111111110100010001 // -751 -750.96
000000001010100000 // 672 671.99
111111110110101000 // -600 -600.31
000000001000010111 // 535 535.1
111111111000100100 // -476 -475.72
000000000110100110 // 422 421.61
111111111010001100 // -372 -372.28
000000000101000111 // 327 327.27
111111111011100010 // -286 -286.21
000000000011111001 // 249 248.75
111111111100101001 // -215 -214.65
000000000010111000 // 184 183.64
111111111101100100 // -156 -155.52
000000000010000010 // 130 130.09
111111111110010101 // -107 -107.18
000000000001010111 // 87 86.58
111111111110111100 // -68 -68.12
000000000000110100 // 52 51.65
111111111111011011 // -37 -37.06
000000000000011000 // 24 24.2
111111111111110011 // -13 -12.93
000000000000000011 // 3 3.12
000000000000000101 // 5 5.29
111111111111110100 // -12 -12.43
000000000000010010 // 18 18.39
111111111111101001 // -23 -23.31
000000000000011011 // 27 27.25
111111111111100010 // -30 -30.3
000000000000100001 // 33 32.56
111111111111011110 // -34 -34.22
000000000000100011 // 35 35.32
111111111111011100 // -36 -36.05
000000000000100101 // 37 36.59
111111111111011011 // -37 -37.37
000000000000100111 // 39 38.81
111111111111010110 // -42 -41.94
000000000000110000 // 48 48.33
111111111111000011 // -61 -61.32
000000000001010110 // 86 85.67
111111111110000011 // -125 -124.78
111111111110000110 // -122 -121.96
111111111111111110 // -2 -1.94
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000

263
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL4BF.mif 100644
Wyświetl plik

@ -0,0 +1,263 @@
DEPTH = 256;
WIDTH = 18;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT
BEGIN
00 : 3FFF0; -- -16 -15.55
01 : 3FF61; -- -159 -159.46
02 : 3FFC5; -- -59 -59.24
03 : 00044; -- 68 68.31
04 : 3FFC1; -- -63 -63.24
05 : 0003B; -- 59 59.19
06 : 3FFC6; -- -58 -58.15
07 : 0003B; -- 59 59.39
08 : 3FFC2; -- -62 -62.36
09 : 00042; -- 66 66.45
0A : 3FFB9; -- -71 -71.45
0B : 0004D; -- 77 77.01
0C : 3FFAD; -- -83 -82.98
0D : 00059; -- 89 89.21
0E : 3FFA0; -- -96 -95.66
0F : 00066; -- 102 102.2
10 : 3FF93; -- -109 -108.74
11 : 00073; -- 115 115.18
12 : 3FF86; -- -122 -121.52
13 : 00080; -- 128 127.63
14 : 3FF7B; -- -133 -133.43
15 : 0008B; -- 139 138.84
16 : 3FF70; -- -144 -143.8
17 : 00094; -- 148 148.23
18 : 3FF68; -- -152 -152.02
19 : 0009B; -- 155 155.04
1A : 3FF63; -- -157 -157.22
1B : 0009E; -- 158 158.43
1C : 3FF61; -- -159 -158.56
1D : 0009D; -- 157 157.43
1E : 3FF65; -- -155 -154.9
1F : 00097; -- 151 150.81
20 : 3FF6F; -- -145 -145.01
21 : 00089; -- 137 137.32
22 : 3FF80; -- -128 -127.55
23 : 00073; -- 115 115.47
24 : 3FF9B; -- -101 -100.83
25 : 00053; -- 83 83.3
26 : 3FFC1; -- -63 -62.53
27 : 00026; -- 38 38.14
28 : 3FFF6; -- -10 -9.71
29 : 3FFE9; -- -23 -23.27
2A : 0003D; -- 61 61.44
2B : 3FF96; -- -106 -105.57
2C : 0009D; -- 157 156.63
2D : 3FF28; -- -216 -215.84
2E : 0011D; -- 285 284.72
2F : 3FE93; -- -365 -365.16
30 : 001CC; -- 460 459.69
31 : 3FDC4; -- -572 -571.84
32 : 002C3; -- 707 706.59
33 : 3FC99; -- -871 -870.93
34 : 00433; -- 1075 1075.14
35 : 3FAC9; -- -1335 -1335.25
36 : 0068E; -- 1678 1678.01
37 : 3F799; -- -2151 -2150.57
38 : 00B1D; -- 2845 2845.05
39 : 3F07F; -- -3969 -3968.7
3A : 017DE; -- 6110 6109.58
3B : 3D1C6; -- -11834 -11833.59
3C : 1327A; -- 78458 78457.77
3D : 049BC; -- 18876 18875.93
3E : 3DDAD; -- -8787 -8787.3
3F : 016E3; -- 5859 5859.41
40 : 3EE97; -- -4457 -4456.63
41 : 00E2C; -- 3628 3628.21
42 : 3F3FB; -- -3077 -3076.99
43 : 00A79; -- 2681 2680.7
44 : 3F6B4; -- -2380 -2379.71
45 : 0085E; -- 2142 2141.55
46 : 3F865; -- -1947 -1946.74
47 : 006F7; -- 1783 1783.15
48 : 3F995; -- -1643 -1642.85
49 : 005F0; -- 1520 1520.49
4A : 3FA7C; -- -1412 -1412.14
4B : 00523; -- 1315 1314.94
4C : 3FB35; -- -1227 -1226.76
4D : 0047A; -- 1146 1146.07
4E : 3FBD0; -- -1072 -1071.73
4F : 003EB; -- 1003 1002.81
50 : 3FC55; -- -939 -938.55
51 : 0036E; -- 878 878.37
52 : 3FCCA; -- -822 -821.78
53 : 00300; -- 768 768.38
54 : 3FD32; -- -718 -717.9
55 : 0029E; -- 670 670.1
56 : 3FD8F; -- -625 -624.82
57 : 00246; -- 582 581.86
58 : 3FDE3; -- -541 -541.06
59 : 001F6; -- 502 502.28
5A : 3FE2F; -- -465 -465.43
5B : 001AE; -- 430 430.4
5C : 3FE73; -- -397 -397.15
5D : 0016E; -- 366 365.61
5E : 3FEB0; -- -336 -335.77
5F : 00134; -- 308 307.54
60 : 3FEE7; -- -281 -280.87
61 : 00100; -- 256 255.7
62 : 3FF18; -- -232 -232.01
63 : 000D2; -- 210 209.77
64 : 3FF43; -- -189 -188.93
65 : 000A9; -- 169 169.4
66 : 3FF69; -- -151 -151.2
67 : 00086; -- 134 134.29
68 : 3FF89; -- -119 -118.65
69 : 00068; -- 104 104.2
6A : 3FFA5; -- -91 -90.96
6B : 0004F; -- 79 78.88
6C : 3FFBC; -- -68 -67.99
6D : 0003A; -- 58 58.17
6E : 3FFCF; -- -49 -49.45
6F : 0002A; -- 42 41.79
70 : 3FFDD; -- -35 -35.2
71 : 0001D; -- 29 29.46
72 : 3FFE8; -- -24 -24.38
73 : 00013; -- 19 19.15
74 : 3FFF4; -- -12 -12.0
75 : 3FFFD; -- -3 -2.81
76 : 0002A; -- 42 41.57
77 : 3FF4F; -- -177 -176.7
78 : 3FFC5; -- -59 -58.91
79 : 00003; -- 3 2.7
7A : 00000;
7B : 00000;
7C : 00000;
7D : 00000;
7E : 00000;
7F : 00000;
80 : 00003; -- 3 2.53
81 : 3FFB1; -- -79 -78.87
82 : 3FF59; -- -167 -167.26
83 : 00041; -- 65 65.16
84 : 3FFE4; -- -28 -27.52
85 : 0000B; -- 11 10.98
86 : 3FFFD; -- -3 -2.68
87 : 3FFFD; -- -3 -2.82
88 : 00007; -- 7 7.47
89 : 3FFF4; -- -12 -12.31
8A : 00012; -- 18 17.68
8B : 3FFE8; -- -24 -23.92
8C : 0001F; -- 31 31.11
8D : 3FFD9; -- -39 -39.35
8E : 00031; -- 49 48.67
8F : 3FFC5; -- -59 -59.2
90 : 00047; -- 71 70.98
91 : 3FFAC; -- -84 -84.09
92 : 00063; -- 99 98.53
93 : 3FF8E; -- -114 -114.43
94 : 00084; -- 132 131.84
95 : 3FF69; -- -151 -150.82
96 : 000AB; -- 171 171.42
97 : 3FF3E; -- -194 -193.74
98 : 000DA; -- 218 217.86
99 : 3FF0C; -- -244 -243.89
9A : 00110; -- 272 271.89
9B : 3FED2; -- -302 -301.95
9C : 0014E; -- 334 334.19
9D : 3FE8F; -- -369 -368.76
9E : 00196; -- 406 405.74
9F : 3FE43; -- -445 -445.25
A0 : 001E7; -- 487 487.43
A1 : 3FDEC; -- -532 -532.46
A2 : 00245; -- 581 580.51
A3 : 3FD88; -- -632 -631.83
A4 : 002AF; -- 687 686.69
A5 : 3FD17; -- -745 -745.42
A6 : 00328; -- 808 808.35
A7 : 3FC94; -- -876 -875.9
A8 : 003B5; -- 949 948.53
A9 : 3FBFD; -- -1027 -1026.88
AA : 00458; -- 1112 1111.72
AB : 3FB4C; -- -1204 -1204.01
AC : 00519; -- 1305 1304.93
AD : 3FA78; -- -1416 -1415.97
AE : 00603; -- 1539 1538.98
AF : 3F974; -- -1676 -1676.38
B0 : 00727; -- 1831 1831.44
B1 : 3F827; -- -2009 -2008.64
B2 : 008A6; -- 2214 2214.12
B3 : 3F668; -- -2456 -2456.39
B4 : 00ABC; -- 2748 2747.95
B5 : 3F3DC; -- -3108 -3108.0
B6 : 00DEF; -- 3567 3567.43
B7 : 3EFAD; -- -4179 -4178.55
B8 : 013AE; -- 5038 5038.36
B9 : 3E733; -- -6349 -6349.16
BA : 021A7; -- 8615 8615.49
BB : 3CB20; -- -13536 -13535.56
BC : 07FB5; -- 32693 32692.86
BD : 113C2; -- 70594 70593.52
BE : 3BFBA; -- -16454 -16453.82
BF : 0239E; -- 9118 9117.56
C0 : 3E7CB; -- -6197 -6197.2
C1 : 0120E; -- 4622 4621.76
C2 : 3F1D0; -- -3632 -3631.86
C3 : 00B86; -- 2950 2949.91
C4 : 3F66E; -- -2450 -2450.05
C5 : 00813; -- 2067 2066.95
C6 : 3F91D; -- -1763 -1763.2
C7 : 005EC; -- 1516 1516.11
C8 : 3FAE1; -- -1311 -1311.07
C9 : 00472; -- 1138 1138.16
CA : 3FC22; -- -990 -990.32
CB : 0035F; -- 863 862.51
CC : 3FD11; -- -751 -751.06
CD : 0028D; -- 653 653.24
CE : 3FDC9; -- -567 -566.93
CF : 001EA; -- 490 490.39
D0 : 3FE5A; -- -422 -422.28
D1 : 00169; -- 361 361.49
D2 : 3FECD; -- -307 -307.13
D3 : 00102; -- 258 258.48
D4 : 3FF29; -- -215 -214.95
D5 : 000B0; -- 176 176.05
D6 : 3FF73; -- -141 -141.3
D7 : 0006E; -- 110 110.29
D8 : 3FFAD; -- -83 -82.67
D9 : 0003A; -- 58 58.13
DA : 3FFDC; -- -36 -36.44
DB : 00011; -- 17 17.35
DC : 3FFFF; -- -1 -0.67
DD : 3FFF2; -- -14 -13.79
DE : 0001A; -- 26 26.2
DF : 3FFDB; -- -37 -36.78
E0 : 0002E; -- 46 45.67
E1 : 3FFCB; -- -53 -53.03
E2 : 0003B; -- 59 58.95
E3 : 3FFC0; -- -64 -63.59
E4 : 00043; -- 67 67.07
E5 : 3FFBA; -- -70 -69.52
E6 : 00047; -- 71 71.0
E7 : 3FFB8; -- -72 -71.62
E8 : 00047; -- 71 71.49
E9 : 3FFB9; -- -71 -70.72
EA : 00045; -- 69 69.37
EB : 3FFBC; -- -68 -67.55
EC : 00041; -- 65 65.34
ED : 3FFC1; -- -63 -62.92
EE : 0003C; -- 60 60.34
EF : 3FFC6; -- -58 -57.78
F0 : 00037; -- 55 55.42
F1 : 3FFCA; -- -54 -53.67
F2 : 00035; -- 53 52.87
F3 : 3FFCA; -- -54 -53.88
F4 : 0003A; -- 58 57.79
F5 : 3FFBD; -- -67 -66.62
F6 : 00051; -- 81 81.41
F7 : 3FFA2; -- -94 -93.93
F8 : 3FF72; -- -142 -142.25
F9 : 3FFF9; -- -7 -7.35
FA : 00000;
FB : 00000;
FC : 00000;
FD : 00000;
FE : 00000;
FF : 00000;
END;

256
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL4BF.txt 100644
Wyświetl plik

@ -0,0 +1,256 @@
111111111111110000 // -16 -15.55
111111111101100001 // -159 -159.46
111111111111000101 // -59 -59.24
000000000001000100 // 68 68.31
111111111111000001 // -63 -63.24
000000000000111011 // 59 59.19
111111111111000110 // -58 -58.15
000000000000111011 // 59 59.39
111111111111000010 // -62 -62.36
000000000001000010 // 66 66.45
111111111110111001 // -71 -71.45
000000000001001101 // 77 77.01
111111111110101101 // -83 -82.98
000000000001011001 // 89 89.21
111111111110100000 // -96 -95.66
000000000001100110 // 102 102.2
111111111110010011 // -109 -108.74
000000000001110011 // 115 115.18
111111111110000110 // -122 -121.52
000000000010000000 // 128 127.63
111111111101111011 // -133 -133.43
000000000010001011 // 139 138.84
111111111101110000 // -144 -143.8
000000000010010100 // 148 148.23
111111111101101000 // -152 -152.02
000000000010011011 // 155 155.04
111111111101100011 // -157 -157.22
000000000010011110 // 158 158.43
111111111101100001 // -159 -158.56
000000000010011101 // 157 157.43
111111111101100101 // -155 -154.9
000000000010010111 // 151 150.81
111111111101101111 // -145 -145.01
000000000010001001 // 137 137.32
111111111110000000 // -128 -127.55
000000000001110011 // 115 115.47
111111111110011011 // -101 -100.83
000000000001010011 // 83 83.3
111111111111000001 // -63 -62.53
000000000000100110 // 38 38.14
111111111111110110 // -10 -9.71
111111111111101001 // -23 -23.27
000000000000111101 // 61 61.44
111111111110010110 // -106 -105.57
000000000010011101 // 157 156.63
111111111100101000 // -216 -215.84
000000000100011101 // 285 284.72
111111111010010011 // -365 -365.16
000000000111001100 // 460 459.69
111111110111000100 // -572 -571.84
000000001011000011 // 707 706.59
111111110010011001 // -871 -870.93
000000010000110011 // 1075 1075.14
111111101011001001 // -1335 -1335.25
000000011010001110 // 1678 1678.01
111111011110011001 // -2151 -2150.57
000000101100011101 // 2845 2845.05
111111000001111111 // -3969 -3968.7
000001011111011110 // 6110 6109.58
111101000111000110 // -11834 -11833.59
010011001001111010 // 78458 78457.77
000100100110111100 // 18876 18875.93
111101110110101101 // -8787 -8787.3
000001011011100011 // 5859 5859.41
111110111010010111 // -4457 -4456.63
000000111000101100 // 3628 3628.21
111111001111111011 // -3077 -3076.99
000000101001111001 // 2681 2680.7
111111011010110100 // -2380 -2379.71
000000100001011110 // 2142 2141.55
111111100001100101 // -1947 -1946.74
000000011011110111 // 1783 1783.15
111111100110010101 // -1643 -1642.85
000000010111110000 // 1520 1520.49
111111101001111100 // -1412 -1412.14
000000010100100011 // 1315 1314.94
111111101100110101 // -1227 -1226.76
000000010001111010 // 1146 1146.07
111111101111010000 // -1072 -1071.73
000000001111101011 // 1003 1002.81
111111110001010101 // -939 -938.55
000000001101101110 // 878 878.37
111111110011001010 // -822 -821.78
000000001100000000 // 768 768.38
111111110100110010 // -718 -717.9
000000001010011110 // 670 670.1
111111110110001111 // -625 -624.82
000000001001000110 // 582 581.86
111111110111100011 // -541 -541.06
000000000111110110 // 502 502.28
111111111000101111 // -465 -465.43
000000000110101110 // 430 430.4
111111111001110011 // -397 -397.15
000000000101101110 // 366 365.61
111111111010110000 // -336 -335.77
000000000100110100 // 308 307.54
111111111011100111 // -281 -280.87
000000000100000000 // 256 255.7
111111111100011000 // -232 -232.01
000000000011010010 // 210 209.77
111111111101000011 // -189 -188.93
000000000010101001 // 169 169.4
111111111101101001 // -151 -151.2
000000000010000110 // 134 134.29
111111111110001001 // -119 -118.65
000000000001101000 // 104 104.2
111111111110100101 // -91 -90.96
000000000001001111 // 79 78.88
111111111110111100 // -68 -67.99
000000000000111010 // 58 58.17
111111111111001111 // -49 -49.45
000000000000101010 // 42 41.79
111111111111011101 // -35 -35.2
000000000000011101 // 29 29.46
111111111111101000 // -24 -24.38
000000000000010011 // 19 19.15
111111111111110100 // -12 -12.0
111111111111111101 // -3 -2.81
000000000000101010 // 42 41.57
111111111101001111 // -177 -176.7
111111111111000101 // -59 -58.91
000000000000000011 // 3 2.7
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000011 // 3 2.53
111111111110110001 // -79 -78.87
111111111101011001 // -167 -167.26
000000000001000001 // 65 65.16
111111111111100100 // -28 -27.52
000000000000001011 // 11 10.98
111111111111111101 // -3 -2.68
111111111111111101 // -3 -2.82
000000000000000111 // 7 7.47
111111111111110100 // -12 -12.31
000000000000010010 // 18 17.68
111111111111101000 // -24 -23.92
000000000000011111 // 31 31.11
111111111111011001 // -39 -39.35
000000000000110001 // 49 48.67
111111111111000101 // -59 -59.2
000000000001000111 // 71 70.98
111111111110101100 // -84 -84.09
000000000001100011 // 99 98.53
111111111110001110 // -114 -114.43
000000000010000100 // 132 131.84
111111111101101001 // -151 -150.82
000000000010101011 // 171 171.42
111111111100111110 // -194 -193.74
000000000011011010 // 218 217.86
111111111100001100 // -244 -243.89
000000000100010000 // 272 271.89
111111111011010010 // -302 -301.95
000000000101001110 // 334 334.19
111111111010001111 // -369 -368.76
000000000110010110 // 406 405.74
111111111001000011 // -445 -445.25
000000000111100111 // 487 487.43
111111110111101100 // -532 -532.46
000000001001000101 // 581 580.51
111111110110001000 // -632 -631.83
000000001010101111 // 687 686.69
111111110100010111 // -745 -745.42
000000001100101000 // 808 808.35
111111110010010100 // -876 -875.9
000000001110110101 // 949 948.53
111111101111111101 // -1027 -1026.88
000000010001011000 // 1112 1111.72
111111101101001100 // -1204 -1204.01
000000010100011001 // 1305 1304.93
111111101001111000 // -1416 -1415.97
000000011000000011 // 1539 1538.98
111111100101110100 // -1676 -1676.38
000000011100100111 // 1831 1831.44
111111100000100111 // -2009 -2008.64
000000100010100110 // 2214 2214.12
111111011001101000 // -2456 -2456.39
000000101010111100 // 2748 2747.95
111111001111011100 // -3108 -3108.0
000000110111101111 // 3567 3567.43
111110111110101101 // -4179 -4178.55
000001001110101110 // 5038 5038.36
111110011100110011 // -6349 -6349.16
000010000110100111 // 8615 8615.49
111100101100100000 // -13536 -13535.56
000111111110110101 // 32693 32692.86
010001001111000010 // 70594 70593.52
111011111110111010 // -16454 -16453.82
000010001110011110 // 9118 9117.56
111110011111001011 // -6197 -6197.2
000001001000001110 // 4622 4621.76
111111000111010000 // -3632 -3631.86
000000101110000110 // 2950 2949.91
111111011001101110 // -2450 -2450.05
000000100000010011 // 2067 2066.95
111111100100011101 // -1763 -1763.2
000000010111101100 // 1516 1516.11
111111101011100001 // -1311 -1311.07
000000010001110010 // 1138 1138.16
111111110000100010 // -990 -990.32
000000001101011111 // 863 862.51
111111110100010001 // -751 -751.06
000000001010001101 // 653 653.24
111111110111001001 // -567 -566.93
000000000111101010 // 490 490.39
111111111001011010 // -422 -422.28
000000000101101001 // 361 361.49
111111111011001101 // -307 -307.13
000000000100000010 // 258 258.48
111111111100101001 // -215 -214.95
000000000010110000 // 176 176.05
111111111101110011 // -141 -141.3
000000000001101110 // 110 110.29
111111111110101101 // -83 -82.67
000000000000111010 // 58 58.13
111111111111011100 // -36 -36.44
000000000000010001 // 17 17.35
111111111111111111 // -1 -0.67
111111111111110010 // -14 -13.79
000000000000011010 // 26 26.2
111111111111011011 // -37 -36.78
000000000000101110 // 46 45.67
111111111111001011 // -53 -53.03
000000000000111011 // 59 58.95
111111111111000000 // -64 -63.59
000000000001000011 // 67 67.07
111111111110111010 // -70 -69.52
000000000001000111 // 71 71.0
111111111110111000 // -72 -71.62
000000000001000111 // 71 71.49
111111111110111001 // -71 -70.72
000000000001000101 // 69 69.37
111111111110111100 // -68 -67.55
000000000001000001 // 65 65.34
111111111111000001 // -63 -62.92
000000000000111100 // 60 60.34
111111111111000110 // -58 -57.78
000000000000110111 // 55 55.42
111111111111001010 // -54 -53.67
000000000000110101 // 53 52.87
111111111111001010 // -54 -53.88
000000000000111010 // 58 57.79
111111111110111101 // -67 -66.62
000000000001010001 // 81 81.41
111111111110100010 // -94 -93.93
111111111101110010 // -142 -142.25
111111111111111001 // -7 -7.35
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000

263
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL4CG.mif 100644
Wyświetl plik

@ -0,0 +1,263 @@
DEPTH = 256;
WIDTH = 18;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT
BEGIN
00 : 3FFF9; -- -7 -7.35
01 : 3FF72; -- -142 -142.25
02 : 3FFA2; -- -94 -93.93
03 : 00051; -- 81 81.41
04 : 3FFBD; -- -67 -66.62
05 : 0003A; -- 58 57.79
06 : 3FFCA; -- -54 -53.88
07 : 00035; -- 53 52.87
08 : 3FFCA; -- -54 -53.67
09 : 00037; -- 55 55.42
0A : 3FFC6; -- -58 -57.78
0B : 0003C; -- 60 60.34
0C : 3FFC1; -- -63 -62.92
0D : 00041; -- 65 65.34
0E : 3FFBC; -- -68 -67.55
0F : 00045; -- 69 69.37
10 : 3FFB9; -- -71 -70.72
11 : 00047; -- 71 71.49
12 : 3FFB8; -- -72 -71.62
13 : 00047; -- 71 71.0
14 : 3FFBA; -- -70 -69.52
15 : 00043; -- 67 67.07
16 : 3FFC0; -- -64 -63.59
17 : 0003B; -- 59 58.95
18 : 3FFCB; -- -53 -53.03
19 : 0002E; -- 46 45.67
1A : 3FFDB; -- -37 -36.78
1B : 0001A; -- 26 26.2
1C : 3FFF2; -- -14 -13.79
1D : 3FFFF; -- -1 -0.67
1E : 00011; -- 17 17.35
1F : 3FFDC; -- -36 -36.44
20 : 0003A; -- 58 58.13
21 : 3FFAD; -- -83 -82.67
22 : 0006E; -- 110 110.29
23 : 3FF73; -- -141 -141.3
24 : 000B0; -- 176 176.05
25 : 3FF29; -- -215 -214.95
26 : 00102; -- 258 258.48
27 : 3FECD; -- -307 -307.13
28 : 00169; -- 361 361.49
29 : 3FE5A; -- -422 -422.28
2A : 001EA; -- 490 490.39
2B : 3FDC9; -- -567 -566.93
2C : 0028D; -- 653 653.24
2D : 3FD11; -- -751 -751.06
2E : 0035F; -- 863 862.51
2F : 3FC22; -- -990 -990.32
30 : 00472; -- 1138 1138.16
31 : 3FAE1; -- -1311 -1311.07
32 : 005EC; -- 1516 1516.11
33 : 3F91D; -- -1763 -1763.2
34 : 00813; -- 2067 2066.95
35 : 3F66E; -- -2450 -2450.05
36 : 00B86; -- 2950 2949.91
37 : 3F1D0; -- -3632 -3631.86
38 : 0120E; -- 4622 4621.76
39 : 3E7CB; -- -6197 -6197.2
3A : 0239E; -- 9118 9117.56
3B : 3BFBA; -- -16454 -16453.82
3C : 113C2; -- 70594 70593.52
3D : 07FB5; -- 32693 32692.86
3E : 3CB20; -- -13536 -13535.56
3F : 021A7; -- 8615 8615.49
40 : 3E733; -- -6349 -6349.16
41 : 013AE; -- 5038 5038.36
42 : 3EFAD; -- -4179 -4178.55
43 : 00DEF; -- 3567 3567.43
44 : 3F3DC; -- -3108 -3108.0
45 : 00ABC; -- 2748 2747.95
46 : 3F668; -- -2456 -2456.39
47 : 008A6; -- 2214 2214.12
48 : 3F827; -- -2009 -2008.64
49 : 00727; -- 1831 1831.44
4A : 3F974; -- -1676 -1676.38
4B : 00603; -- 1539 1538.98
4C : 3FA78; -- -1416 -1415.97
4D : 00519; -- 1305 1304.93
4E : 3FB4C; -- -1204 -1204.01
4F : 00458; -- 1112 1111.72
50 : 3FBFD; -- -1027 -1026.88
51 : 003B5; -- 949 948.53
52 : 3FC94; -- -876 -875.9
53 : 00328; -- 808 808.35
54 : 3FD17; -- -745 -745.42
55 : 002AF; -- 687 686.69
56 : 3FD88; -- -632 -631.83
57 : 00245; -- 581 580.51
58 : 3FDEC; -- -532 -532.46
59 : 001E7; -- 487 487.43
5A : 3FE43; -- -445 -445.25
5B : 00196; -- 406 405.74
5C : 3FE8F; -- -369 -368.76
5D : 0014E; -- 334 334.19
5E : 3FED2; -- -302 -301.95
5F : 00110; -- 272 271.89
60 : 3FF0C; -- -244 -243.89
61 : 000DA; -- 218 217.86
62 : 3FF3E; -- -194 -193.74
63 : 000AB; -- 171 171.42
64 : 3FF69; -- -151 -150.82
65 : 00084; -- 132 131.84
66 : 3FF8E; -- -114 -114.43
67 : 00063; -- 99 98.53
68 : 3FFAC; -- -84 -84.09
69 : 00047; -- 71 70.98
6A : 3FFC5; -- -59 -59.2
6B : 00031; -- 49 48.67
6C : 3FFD9; -- -39 -39.35
6D : 0001F; -- 31 31.11
6E : 3FFE8; -- -24 -23.92
6F : 00012; -- 18 17.68
70 : 3FFF4; -- -12 -12.31
71 : 00007; -- 7 7.47
72 : 3FFFD; -- -3 -2.82
73 : 3FFFD; -- -3 -2.68
74 : 0000B; -- 11 10.98
75 : 3FFE4; -- -28 -27.52
76 : 00041; -- 65 65.16
77 : 3FF59; -- -167 -167.26
78 : 3FFB1; -- -79 -78.87
79 : 00003; -- 3 2.53
7A : 00000;
7B : 00000;
7C : 00000;
7D : 00000;
7E : 00000;
7F : 00000;
80 : 00003; -- 3 2.7
81 : 3FFC5; -- -59 -58.91
82 : 3FF4F; -- -177 -176.7
83 : 0002A; -- 42 41.57
84 : 3FFFD; -- -3 -2.81
85 : 3FFF4; -- -12 -12.0
86 : 00013; -- 19 19.15
87 : 3FFE8; -- -24 -24.38
88 : 0001D; -- 29 29.46
89 : 3FFDD; -- -35 -35.2
8A : 0002A; -- 42 41.79
8B : 3FFCF; -- -49 -49.45
8C : 0003A; -- 58 58.17
8D : 3FFBC; -- -68 -67.99
8E : 0004F; -- 79 78.88
8F : 3FFA5; -- -91 -90.96
90 : 00068; -- 104 104.2
91 : 3FF89; -- -119 -118.65
92 : 00086; -- 134 134.29
93 : 3FF69; -- -151 -151.2
94 : 000A9; -- 169 169.4
95 : 3FF43; -- -189 -188.93
96 : 000D2; -- 210 209.77
97 : 3FF18; -- -232 -232.01
98 : 00100; -- 256 255.7
99 : 3FEE7; -- -281 -280.87
9A : 00134; -- 308 307.54
9B : 3FEB0; -- -336 -335.77
9C : 0016E; -- 366 365.61
9D : 3FE73; -- -397 -397.15
9E : 001AE; -- 430 430.4
9F : 3FE2F; -- -465 -465.43
A0 : 001F6; -- 502 502.28
A1 : 3FDE3; -- -541 -541.06
A2 : 00246; -- 582 581.86
A3 : 3FD8F; -- -625 -624.82
A4 : 0029E; -- 670 670.1
A5 : 3FD32; -- -718 -717.9
A6 : 00300; -- 768 768.38
A7 : 3FCCA; -- -822 -821.78
A8 : 0036E; -- 878 878.37
A9 : 3FC55; -- -939 -938.55
AA : 003EB; -- 1003 1002.81
AB : 3FBD0; -- -1072 -1071.73
AC : 0047A; -- 1146 1146.07
AD : 3FB35; -- -1227 -1226.76
AE : 00523; -- 1315 1314.94
AF : 3FA7C; -- -1412 -1412.14
B0 : 005F0; -- 1520 1520.49
B1 : 3F995; -- -1643 -1642.85
B2 : 006F7; -- 1783 1783.15
B3 : 3F865; -- -1947 -1946.74
B4 : 0085E; -- 2142 2141.55
B5 : 3F6B4; -- -2380 -2379.71
B6 : 00A79; -- 2681 2680.7
B7 : 3F3FB; -- -3077 -3076.99
B8 : 00E2C; -- 3628 3628.21
B9 : 3EE97; -- -4457 -4456.63
BA : 016E3; -- 5859 5859.41
BB : 3DDAD; -- -8787 -8787.3
BC : 049BC; -- 18876 18875.93
BD : 1327A; -- 78458 78457.77
BE : 3D1C6; -- -11834 -11833.59
BF : 017DE; -- 6110 6109.58
C0 : 3F07F; -- -3969 -3968.7
C1 : 00B1D; -- 2845 2845.05
C2 : 3F799; -- -2151 -2150.57
C3 : 0068E; -- 1678 1678.01
C4 : 3FAC9; -- -1335 -1335.25
C5 : 00433; -- 1075 1075.14
C6 : 3FC99; -- -871 -870.93
C7 : 002C3; -- 707 706.59
C8 : 3FDC4; -- -572 -571.84
C9 : 001CC; -- 460 459.69
CA : 3FE93; -- -365 -365.16
CB : 0011D; -- 285 284.72
CC : 3FF28; -- -216 -215.84
CD : 0009D; -- 157 156.63
CE : 3FF96; -- -106 -105.57
CF : 0003D; -- 61 61.44
D0 : 3FFE9; -- -23 -23.27
D1 : 3FFF6; -- -10 -9.71
D2 : 00026; -- 38 38.14
D3 : 3FFC1; -- -63 -62.53
D4 : 00053; -- 83 83.3
D5 : 3FF9B; -- -101 -100.83
D6 : 00073; -- 115 115.47
D7 : 3FF80; -- -128 -127.55
D8 : 00089; -- 137 137.32
D9 : 3FF6F; -- -145 -145.01
DA : 00097; -- 151 150.81
DB : 3FF65; -- -155 -154.9
DC : 0009D; -- 157 157.43
DD : 3FF61; -- -159 -158.56
DE : 0009E; -- 158 158.43
DF : 3FF63; -- -157 -157.22
E0 : 0009B; -- 155 155.04
E1 : 3FF68; -- -152 -152.02
E2 : 00094; -- 148 148.23
E3 : 3FF70; -- -144 -143.8
E4 : 0008B; -- 139 138.84
E5 : 3FF7B; -- -133 -133.43
E6 : 00080; -- 128 127.63
E7 : 3FF86; -- -122 -121.52
E8 : 00073; -- 115 115.18
E9 : 3FF93; -- -109 -108.74
EA : 00066; -- 102 102.2
EB : 3FFA0; -- -96 -95.66
EC : 00059; -- 89 89.21
ED : 3FFAD; -- -83 -82.98
EE : 0004D; -- 77 77.01
EF : 3FFB9; -- -71 -71.45
F0 : 00042; -- 66 66.45
F1 : 3FFC2; -- -62 -62.36
F2 : 0003B; -- 59 59.39
F3 : 3FFC6; -- -58 -58.15
F4 : 0003B; -- 59 59.19
F5 : 3FFC1; -- -63 -63.24
F6 : 00044; -- 68 68.31
F7 : 3FFC5; -- -59 -59.24
F8 : 3FF61; -- -159 -159.46
F9 : 3FFF0; -- -16 -15.55
FA : 00000;
FB : 00000;
FC : 00000;
FD : 00000;
FE : 00000;
FF : 00000;
END;

256
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL4CG.txt 100644
Wyświetl plik

@ -0,0 +1,256 @@
111111111111111001 // -7 -7.35
111111111101110010 // -142 -142.25
111111111110100010 // -94 -93.93
000000000001010001 // 81 81.41
111111111110111101 // -67 -66.62
000000000000111010 // 58 57.79
111111111111001010 // -54 -53.88
000000000000110101 // 53 52.87
111111111111001010 // -54 -53.67
000000000000110111 // 55 55.42
111111111111000110 // -58 -57.78
000000000000111100 // 60 60.34
111111111111000001 // -63 -62.92
000000000001000001 // 65 65.34
111111111110111100 // -68 -67.55
000000000001000101 // 69 69.37
111111111110111001 // -71 -70.72
000000000001000111 // 71 71.49
111111111110111000 // -72 -71.62
000000000001000111 // 71 71.0
111111111110111010 // -70 -69.52
000000000001000011 // 67 67.07
111111111111000000 // -64 -63.59
000000000000111011 // 59 58.95
111111111111001011 // -53 -53.03
000000000000101110 // 46 45.67
111111111111011011 // -37 -36.78
000000000000011010 // 26 26.2
111111111111110010 // -14 -13.79
111111111111111111 // -1 -0.67
000000000000010001 // 17 17.35
111111111111011100 // -36 -36.44
000000000000111010 // 58 58.13
111111111110101101 // -83 -82.67
000000000001101110 // 110 110.29
111111111101110011 // -141 -141.3
000000000010110000 // 176 176.05
111111111100101001 // -215 -214.95
000000000100000010 // 258 258.48
111111111011001101 // -307 -307.13
000000000101101001 // 361 361.49
111111111001011010 // -422 -422.28
000000000111101010 // 490 490.39
111111110111001001 // -567 -566.93
000000001010001101 // 653 653.24
111111110100010001 // -751 -751.06
000000001101011111 // 863 862.51
111111110000100010 // -990 -990.32
000000010001110010 // 1138 1138.16
111111101011100001 // -1311 -1311.07
000000010111101100 // 1516 1516.11
111111100100011101 // -1763 -1763.2
000000100000010011 // 2067 2066.95
111111011001101110 // -2450 -2450.05
000000101110000110 // 2950 2949.91
111111000111010000 // -3632 -3631.86
000001001000001110 // 4622 4621.76
111110011111001011 // -6197 -6197.2
000010001110011110 // 9118 9117.56
111011111110111010 // -16454 -16453.82
010001001111000010 // 70594 70593.52
000111111110110101 // 32693 32692.86
111100101100100000 // -13536 -13535.56
000010000110100111 // 8615 8615.49
111110011100110011 // -6349 -6349.16
000001001110101110 // 5038 5038.36
111110111110101101 // -4179 -4178.55
000000110111101111 // 3567 3567.43
111111001111011100 // -3108 -3108.0
000000101010111100 // 2748 2747.95
111111011001101000 // -2456 -2456.39
000000100010100110 // 2214 2214.12
111111100000100111 // -2009 -2008.64
000000011100100111 // 1831 1831.44
111111100101110100 // -1676 -1676.38
000000011000000011 // 1539 1538.98
111111101001111000 // -1416 -1415.97
000000010100011001 // 1305 1304.93
111111101101001100 // -1204 -1204.01
000000010001011000 // 1112 1111.72
111111101111111101 // -1027 -1026.88
000000001110110101 // 949 948.53
111111110010010100 // -876 -875.9
000000001100101000 // 808 808.35
111111110100010111 // -745 -745.42
000000001010101111 // 687 686.69
111111110110001000 // -632 -631.83
000000001001000101 // 581 580.51
111111110111101100 // -532 -532.46
000000000111100111 // 487 487.43
111111111001000011 // -445 -445.25
000000000110010110 // 406 405.74
111111111010001111 // -369 -368.76
000000000101001110 // 334 334.19
111111111011010010 // -302 -301.95
000000000100010000 // 272 271.89
111111111100001100 // -244 -243.89
000000000011011010 // 218 217.86
111111111100111110 // -194 -193.74
000000000010101011 // 171 171.42
111111111101101001 // -151 -150.82
000000000010000100 // 132 131.84
111111111110001110 // -114 -114.43
000000000001100011 // 99 98.53
111111111110101100 // -84 -84.09
000000000001000111 // 71 70.98
111111111111000101 // -59 -59.2
000000000000110001 // 49 48.67
111111111111011001 // -39 -39.35
000000000000011111 // 31 31.11
111111111111101000 // -24 -23.92
000000000000010010 // 18 17.68
111111111111110100 // -12 -12.31
000000000000000111 // 7 7.47
111111111111111101 // -3 -2.82
111111111111111101 // -3 -2.68
000000000000001011 // 11 10.98
111111111111100100 // -28 -27.52
000000000001000001 // 65 65.16
111111111101011001 // -167 -167.26
111111111110110001 // -79 -78.87
000000000000000011 // 3 2.53
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000011 // 3 2.7
111111111111000101 // -59 -58.91
111111111101001111 // -177 -176.7
000000000000101010 // 42 41.57
111111111111111101 // -3 -2.81
111111111111110100 // -12 -12.0
000000000000010011 // 19 19.15
111111111111101000 // -24 -24.38
000000000000011101 // 29 29.46
111111111111011101 // -35 -35.2
000000000000101010 // 42 41.79
111111111111001111 // -49 -49.45
000000000000111010 // 58 58.17
111111111110111100 // -68 -67.99
000000000001001111 // 79 78.88
111111111110100101 // -91 -90.96
000000000001101000 // 104 104.2
111111111110001001 // -119 -118.65
000000000010000110 // 134 134.29
111111111101101001 // -151 -151.2
000000000010101001 // 169 169.4
111111111101000011 // -189 -188.93
000000000011010010 // 210 209.77
111111111100011000 // -232 -232.01
000000000100000000 // 256 255.7
111111111011100111 // -281 -280.87
000000000100110100 // 308 307.54
111111111010110000 // -336 -335.77
000000000101101110 // 366 365.61
111111111001110011 // -397 -397.15
000000000110101110 // 430 430.4
111111111000101111 // -465 -465.43
000000000111110110 // 502 502.28
111111110111100011 // -541 -541.06
000000001001000110 // 582 581.86
111111110110001111 // -625 -624.82
000000001010011110 // 670 670.1
111111110100110010 // -718 -717.9
000000001100000000 // 768 768.38
111111110011001010 // -822 -821.78
000000001101101110 // 878 878.37
111111110001010101 // -939 -938.55
000000001111101011 // 1003 1002.81
111111101111010000 // -1072 -1071.73
000000010001111010 // 1146 1146.07
111111101100110101 // -1227 -1226.76
000000010100100011 // 1315 1314.94
111111101001111100 // -1412 -1412.14
000000010111110000 // 1520 1520.49
111111100110010101 // -1643 -1642.85
000000011011110111 // 1783 1783.15
111111100001100101 // -1947 -1946.74
000000100001011110 // 2142 2141.55
111111011010110100 // -2380 -2379.71
000000101001111001 // 2681 2680.7
111111001111111011 // -3077 -3076.99
000000111000101100 // 3628 3628.21
111110111010010111 // -4457 -4456.63
000001011011100011 // 5859 5859.41
111101110110101101 // -8787 -8787.3
000100100110111100 // 18876 18875.93
010011001001111010 // 78458 78457.77
111101000111000110 // -11834 -11833.59
000001011111011110 // 6110 6109.58
111111000001111111 // -3969 -3968.7
000000101100011101 // 2845 2845.05
111111011110011001 // -2151 -2150.57
000000011010001110 // 1678 1678.01
111111101011001001 // -1335 -1335.25
000000010000110011 // 1075 1075.14
111111110010011001 // -871 -870.93
000000001011000011 // 707 706.59
111111110111000100 // -572 -571.84
000000000111001100 // 460 459.69
111111111010010011 // -365 -365.16
000000000100011101 // 285 284.72
111111111100101000 // -216 -215.84
000000000010011101 // 157 156.63
111111111110010110 // -106 -105.57
000000000000111101 // 61 61.44
111111111111101001 // -23 -23.27
111111111111110110 // -10 -9.71
000000000000100110 // 38 38.14
111111111111000001 // -63 -62.53
000000000001010011 // 83 83.3
111111111110011011 // -101 -100.83
000000000001110011 // 115 115.47
111111111110000000 // -128 -127.55
000000000010001001 // 137 137.32
111111111101101111 // -145 -145.01
000000000010010111 // 151 150.81
111111111101100101 // -155 -154.9
000000000010011101 // 157 157.43
111111111101100001 // -159 -158.56
000000000010011110 // 158 158.43
111111111101100011 // -157 -157.22
000000000010011011 // 155 155.04
111111111101101000 // -152 -152.02
000000000010010100 // 148 148.23
111111111101110000 // -144 -143.8
000000000010001011 // 139 138.84
111111111101111011 // -133 -133.43
000000000010000000 // 128 127.63
111111111110000110 // -122 -121.52
000000000001110011 // 115 115.18
111111111110010011 // -109 -108.74
000000000001100110 // 102 102.2
111111111110100000 // -96 -95.66
000000000001011001 // 89 89.21
111111111110101101 // -83 -82.98
000000000001001101 // 77 77.01
111111111110111001 // -71 -71.45
000000000001000010 // 66 66.45
111111111111000010 // -62 -62.36
000000000000111011 // 59 59.39
111111111111000110 // -58 -58.15
000000000000111011 // 59 59.19
111111111111000001 // -63 -63.24
000000000001000100 // 68 68.31
111111111111000101 // -59 -59.24
111111111101100001 // -159 -159.46
111111111111110000 // -16 -15.55
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000

263
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL4DH.mif 100644
Wyświetl plik

@ -0,0 +1,263 @@
DEPTH = 256;
WIDTH = 18;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT
BEGIN
00 : 3FFFE; -- -2 -1.94
01 : 3FF86; -- -122 -121.96
02 : 3FF83; -- -125 -124.78
03 : 00056; -- 86 85.67
04 : 3FFC3; -- -61 -61.32
05 : 00030; -- 48 48.33
06 : 3FFD6; -- -42 -41.94
07 : 00027; -- 39 38.81
08 : 3FFDB; -- -37 -37.37
09 : 00025; -- 37 36.59
0A : 3FFDC; -- -36 -36.05
0B : 00023; -- 35 35.32
0C : 3FFDE; -- -34 -34.22
0D : 00021; -- 33 32.56
0E : 3FFE2; -- -30 -30.3
0F : 0001B; -- 27 27.25
10 : 3FFE9; -- -23 -23.31
11 : 00012; -- 18 18.39
12 : 3FFF4; -- -12 -12.43
13 : 00005; -- 5 5.29
14 : 00003; -- 3 3.12
15 : 3FFF3; -- -13 -12.93
16 : 00018; -- 24 24.2
17 : 3FFDB; -- -37 -37.06
18 : 00034; -- 52 51.65
19 : 3FFBC; -- -68 -68.12
1A : 00057; -- 87 86.58
1B : 3FF95; -- -107 -107.18
1C : 00082; -- 130 130.09
1D : 3FF64; -- -156 -155.52
1E : 000B8; -- 184 183.64
1F : 3FF29; -- -215 -214.65
20 : 000F9; -- 249 248.75
21 : 3FEE2; -- -286 -286.21
22 : 00147; -- 327 327.27
23 : 3FE8C; -- -372 -372.28
24 : 001A6; -- 422 421.61
25 : 3FE24; -- -476 -475.72
26 : 00217; -- 535 535.1
27 : 3FDA8; -- -600 -600.31
28 : 002A0; -- 672 671.99
29 : 3FD11; -- -751 -750.96
2A : 00346; -- 838 838.22
2B : 3FC59; -- -935 -935.01
2C : 00413; -- 1043 1042.86
2D : 3FB74; -- -1164 -1163.7
2E : 00514; -- 1300 1299.93
2F : 3FA51; -- -1455 -1454.65
30 : 00660; -- 1632 1632.02
31 : 3F8D2; -- -1838 -1837.76
32 : 00820; -- 2080 2079.8
33 : 3F6BF; -- -2369 -2369.26
34 : 00AA3; -- 2723 2722.5
35 : 3F3A3; -- -3165 -3164.82
36 : 00E9A; -- 3738 3737.57
37 : 3EE60; -- -4512 -4512.2
38 : 015F9; -- 5625 5624.58
39 : 3E337; -- -7369 -7368.52
3A : 0291A; -- 10522 10521.57
3B : 3B99A; -- -18022 -18022.23
3C : 0E922; -- 59682 59681.81
3D : 0B656; -- 46678 46678.12
3E : 3BE24; -- -16860 -16859.67
3F : 02833; -- 10291 10291.22
40 : 3E31E; -- -7394 -7393.55
41 : 01679; -- 5753 5753.43
42 : 3EDAC; -- -4692 -4692.33
43 : 00F6A; -- 3946 3945.82
44 : 3F2C3; -- -3389 -3389.32
45 : 00B8C; -- 2956 2956.46
46 : 3F5D0; -- -2608 -2608.46
47 : 00911; -- 2321 2321.41
48 : 3F7E0; -- -2080 -2079.75
49 : 00751; -- 1873 1872.92
4A : 3F963; -- -1693 -1693.34
4B : 00600; -- 1536 1535.52
4C : 3FA8D; -- -1395 -1395.45
4D : 004F6; -- 1270 1270.15
4E : 3FB7B; -- -1157 -1157.33
4F : 0041F; -- 1055 1055.14
50 : 3FC3E; -- -962 -962.12
51 : 0036D; -- 877 877.08
52 : 3FCE1; -- -799 -799.08
53 : 002D7; -- 727 727.32
54 : 3FD6B; -- -661 -661.2
55 : 00258; -- 600 600.19
56 : 3FDE0; -- -544 -543.86
57 : 001EC; -- 492 491.77
58 : 3FE44; -- -444 -443.58
59 : 0018F; -- 399 398.98
5A : 3FE9A; -- -358 -357.72
5B : 00140; -- 320 319.58
5C : 3FEE4; -- -284 -284.37
5D : 000FC; -- 252 251.91
5E : 3FF22; -- -222 -222.08
5F : 000C3; -- 195 194.66
60 : 3FF56; -- -170 -169.53
61 : 00093; -- 147 146.52
62 : 3FF82; -- -126 -125.56
63 : 0006B; -- 107 106.52
64 : 3FFA7; -- -89 -89.26
65 : 0004A; -- 74 73.67
66 : 3FFC4; -- -60 -59.68
67 : 0002F; -- 47 47.19
68 : 3FFDC; -- -36 -36.13
69 : 0001A; -- 26 26.35
6A : 3FFEE; -- -18 -17.82
6B : 0000A; -- 10 10.44
6C : 3FFFC; -- -4 -4.14
6D : 3FFFF; -- -1 -1.25
6E : 00006; -- 6 5.77
6F : 3FFF6; -- -10 -9.59
70 : 0000D; -- 13 12.83
71 : 3FFF0; -- -16 -15.93
72 : 00013; -- 19 19.3
73 : 3FFE8; -- -24 -24.03
74 : 00020; -- 32 32.01
75 : 3FFD0; -- -48 -47.8
76 : 00050; -- 80 80.21
77 : 3FF6A; -- -150 -149.71
78 : 3FF9C; -- -100 -100.32
79 : 00001; -- 1 1.17
7A : 00000;
7B : 00000;
7C : 00000;
7D : 00000;
7E : 00000;
7F : 00000;
80 : 00004; -- 4 4.08
81 : 3FFD7; -- -41 -41.39
82 : 3FF4E; -- -178 -178.04
83 : 0000B; -- 11 11.29
84 : 00017; -- 23 23.45
85 : 3FFDE; -- -34 -33.9
86 : 00026; -- 38 38.4
87 : 3FFD6; -- -42 -42.32
88 : 0002F; -- 47 46.89
89 : 3FFCB; -- -53 -52.57
8A : 0003B; -- 59 59.32
8B : 3FFBD; -- -67 -67.22
8C : 0004C; -- 76 76.14
8D : 3FFAA; -- -86 -86.06
8E : 00061; -- 97 96.9
8F : 3FF93; -- -109 -108.71
90 : 00079; -- 121 121.45
91 : 3FF79; -- -135 -135.09
92 : 00096; -- 150 149.6
93 : 3FF5B; -- -165 -165.03
94 : 000B5; -- 181 181.34
95 : 3FF39; -- -199 -198.52
96 : 000D9; -- 217 216.54
97 : 3FF15; -- -235 -235.44
98 : 000FF; -- 255 255.19
99 : 3FEEC; -- -276 -275.81
9A : 00129; -- 297 297.25
9B : 3FEC0; -- -320 -319.51
9C : 00157; -- 343 342.59
9D : 3FE92; -- -366 -366.49
9E : 00187; -- 391 391.17
9F : 3FE5F; -- -417 -416.6
A0 : 001BB; -- 443 442.76
A1 : 3FE2A; -- -470 -469.66
A2 : 001F1; -- 497 497.3
A3 : 3FDF2; -- -526 -525.69
A4 : 0022B; -- 555 554.86
A5 : 3FDB7; -- -585 -584.84
A6 : 00268; -- 616 615.63
A7 : 3FD79; -- -647 -647.25
A8 : 002A8; -- 680 679.73
A9 : 3FD37; -- -713 -713.21
AA : 002EC; -- 748 747.8
AB : 3FCF0; -- -784 -783.69
AC : 00335; -- 821 821.08
AD : 3FCA4; -- -860 -860.24
AE : 00385; -- 901 901.49
AF : 3FC4F; -- -945 -945.3
B0 : 003E0; -- 992 992.38
B1 : 3FBEC; -- -1044 -1043.73
B2 : 0044D; -- 1101 1100.62
B3 : 3FB73; -- -1165 -1164.75
B4 : 004D7; -- 1239 1238.71
B5 : 3FAD1; -- -1327 -1326.55
B6 : 0059B; -- 1435 1434.79
B7 : 3F9DA; -- -1574 -1573.96
B8 : 006E3; -- 1763 1763.3
B9 : 3F806; -- -2042 -2041.67
BA : 009C6; -- 2502 2501.72
BB : 3F29F; -- -3425 -3425.2
BC : 0189C; -- 6300 6299.88
BD : 1428F; -- 82575 82574.73
BE : 3EFCF; -- -4145 -4145.21
BF : 006E5; -- 1765 1764.83
C0 : 3FC57; -- -937 -937.39
C1 : 00205; -- 517 517.3
C2 : 3FEF9; -- -263 -263.41
C3 : 0005E; -- 94 94.35
C4 : 00019; -- 25 25.43
C5 : 3FF8E; -- -114 -113.89
C6 : 000B5; -- 181 181.19
C7 : 3FF17; -- -233 -233.21
C8 : 00112; -- 274 273.75
C9 : 3FECF; -- -305 -305.44
CA : 0014A; -- 330 330.2
CB : 3FEA3; -- -349 -349.37
CC : 0016C; -- 364 363.85
CD : 3FE8A; -- -374 -374.34
CE : 0017D; -- 381 381.42
CF : 3FE7E; -- -386 -385.61
D0 : 00183; -- 387 387.31
D1 : 3FE7D; -- -387 -386.85
D2 : 00180; -- 384 384.48
D3 : 3FE84; -- -380 -380.43
D4 : 00177; -- 375 374.85
D5 : 3FE90; -- -368 -367.93
D6 : 00168; -- 360 359.87
D7 : 3FEA1; -- -351 -350.84
D8 : 00155; -- 341 340.96
D9 : 3FEB6; -- -330 -330.35
DA : 0013F; -- 319 319.1
DB : 3FECD; -- -307 -307.32
DC : 00127; -- 295 295.08
DD : 3FEE6; -- -282 -282.48
DE : 0010E; -- 270 269.6
DF : 3FEFF; -- -257 -256.58
E0 : 000F3; -- 243 243.48
E1 : 3FF1A; -- -230 -230.35
E2 : 000D9; -- 217 217.25
E3 : 3FF34; -- -204 -204.26
E4 : 000BF; -- 191 191.44
E5 : 3FF4D; -- -179 -178.84
E6 : 000A6; -- 166 166.48
E7 : 3FF66; -- -154 -154.43
E8 : 0008F; -- 143 142.73
E9 : 3FF7D; -- -131 -131.45
EA : 00079; -- 121 120.59
EB : 3FF92; -- -110 -110.22
EC : 00064; -- 100 100.39
ED : 3FFA5; -- -91 -91.2
EE : 00053; -- 83 82.65
EF : 3FFB5; -- -75 -74.85
F0 : 00044; -- 68 67.89
F1 : 3FFC2; -- -62 -62.03
F2 : 00039; -- 57 57.33
F3 : 3FFCA; -- -54 -54.12
F4 : 00034; -- 52 52.4
F5 : 3FFCC; -- -52 -51.78
F6 : 00030; -- 48 48.15
F7 : 3FFE9; -- -23 -23.23
F8 : 3FF54; -- -172 -171.9
F9 : 3FFE5; -- -27 -26.86
FA : 00000;
FB : 00000;
FC : 00000;
FD : 00000;
FE : 00000;
FF : 00000;
END;

256
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL4DH.txt 100644
Wyświetl plik

@ -0,0 +1,256 @@
111111111111111110 // -2 -1.94
111111111110000110 // -122 -121.96
111111111110000011 // -125 -124.78
000000000001010110 // 86 85.67
111111111111000011 // -61 -61.32
000000000000110000 // 48 48.33
111111111111010110 // -42 -41.94
000000000000100111 // 39 38.81
111111111111011011 // -37 -37.37
000000000000100101 // 37 36.59
111111111111011100 // -36 -36.05
000000000000100011 // 35 35.32
111111111111011110 // -34 -34.22
000000000000100001 // 33 32.56
111111111111100010 // -30 -30.3
000000000000011011 // 27 27.25
111111111111101001 // -23 -23.31
000000000000010010 // 18 18.39
111111111111110100 // -12 -12.43
000000000000000101 // 5 5.29
000000000000000011 // 3 3.12
111111111111110011 // -13 -12.93
000000000000011000 // 24 24.2
111111111111011011 // -37 -37.06
000000000000110100 // 52 51.65
111111111110111100 // -68 -68.12
000000000001010111 // 87 86.58
111111111110010101 // -107 -107.18
000000000010000010 // 130 130.09
111111111101100100 // -156 -155.52
000000000010111000 // 184 183.64
111111111100101001 // -215 -214.65
000000000011111001 // 249 248.75
111111111011100010 // -286 -286.21
000000000101000111 // 327 327.27
111111111010001100 // -372 -372.28
000000000110100110 // 422 421.61
111111111000100100 // -476 -475.72
000000001000010111 // 535 535.1
111111110110101000 // -600 -600.31
000000001010100000 // 672 671.99
111111110100010001 // -751 -750.96
000000001101000110 // 838 838.22
111111110001011001 // -935 -935.01
000000010000010011 // 1043 1042.86
111111101101110100 // -1164 -1163.7
000000010100010100 // 1300 1299.93
111111101001010001 // -1455 -1454.65
000000011001100000 // 1632 1632.02
111111100011010010 // -1838 -1837.76
000000100000100000 // 2080 2079.8
111111011010111111 // -2369 -2369.26
000000101010100011 // 2723 2722.5
111111001110100011 // -3165 -3164.82
000000111010011010 // 3738 3737.57
111110111001100000 // -4512 -4512.2
000001010111111001 // 5625 5624.58
111110001100110111 // -7369 -7368.52
000010100100011010 // 10522 10521.57
111011100110011010 // -18022 -18022.23
001110100100100010 // 59682 59681.81
001011011001010110 // 46678 46678.12
111011111000100100 // -16860 -16859.67
000010100000110011 // 10291 10291.22
111110001100011110 // -7394 -7393.55
000001011001111001 // 5753 5753.43
111110110110101100 // -4692 -4692.33
000000111101101010 // 3946 3945.82
111111001011000011 // -3389 -3389.32
000000101110001100 // 2956 2956.46
111111010111010000 // -2608 -2608.46
000000100100010001 // 2321 2321.41
111111011111100000 // -2080 -2079.75
000000011101010001 // 1873 1872.92
111111100101100011 // -1693 -1693.34
000000011000000000 // 1536 1535.52
111111101010001101 // -1395 -1395.45
000000010011110110 // 1270 1270.15
111111101101111011 // -1157 -1157.33
000000010000011111 // 1055 1055.14
111111110000111110 // -962 -962.12
000000001101101101 // 877 877.08
111111110011100001 // -799 -799.08
000000001011010111 // 727 727.32
111111110101101011 // -661 -661.2
000000001001011000 // 600 600.19
111111110111100000 // -544 -543.86
000000000111101100 // 492 491.77
111111111001000100 // -444 -443.58
000000000110001111 // 399 398.98
111111111010011010 // -358 -357.72
000000000101000000 // 320 319.58
111111111011100100 // -284 -284.37
000000000011111100 // 252 251.91
111111111100100010 // -222 -222.08
000000000011000011 // 195 194.66
111111111101010110 // -170 -169.53
000000000010010011 // 147 146.52
111111111110000010 // -126 -125.56
000000000001101011 // 107 106.52
111111111110100111 // -89 -89.26
000000000001001010 // 74 73.67
111111111111000100 // -60 -59.68
000000000000101111 // 47 47.19
111111111111011100 // -36 -36.13
000000000000011010 // 26 26.35
111111111111101110 // -18 -17.82
000000000000001010 // 10 10.44
111111111111111100 // -4 -4.14
111111111111111111 // -1 -1.25
000000000000000110 // 6 5.77
111111111111110110 // -10 -9.59
000000000000001101 // 13 12.83
111111111111110000 // -16 -15.93
000000000000010011 // 19 19.3
111111111111101000 // -24 -24.03
000000000000100000 // 32 32.01
111111111111010000 // -48 -47.8
000000000001010000 // 80 80.21
111111111101101010 // -150 -149.71
111111111110011100 // -100 -100.32
000000000000000001 // 1 1.17
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000100 // 4 4.08
111111111111010111 // -41 -41.39
111111111101001110 // -178 -178.04
000000000000001011 // 11 11.29
000000000000010111 // 23 23.45
111111111111011110 // -34 -33.9
000000000000100110 // 38 38.4
111111111111010110 // -42 -42.32
000000000000101111 // 47 46.89
111111111111001011 // -53 -52.57
000000000000111011 // 59 59.32
111111111110111101 // -67 -67.22
000000000001001100 // 76 76.14
111111111110101010 // -86 -86.06
000000000001100001 // 97 96.9
111111111110010011 // -109 -108.71
000000000001111001 // 121 121.45
111111111101111001 // -135 -135.09
000000000010010110 // 150 149.6
111111111101011011 // -165 -165.03
000000000010110101 // 181 181.34
111111111100111001 // -199 -198.52
000000000011011001 // 217 216.54
111111111100010101 // -235 -235.44
000000000011111111 // 255 255.19
111111111011101100 // -276 -275.81
000000000100101001 // 297 297.25
111111111011000000 // -320 -319.51
000000000101010111 // 343 342.59
111111111010010010 // -366 -366.49
000000000110000111 // 391 391.17
111111111001011111 // -417 -416.6
000000000110111011 // 443 442.76
111111111000101010 // -470 -469.66
000000000111110001 // 497 497.3
111111110111110010 // -526 -525.69
000000001000101011 // 555 554.86
111111110110110111 // -585 -584.84
000000001001101000 // 616 615.63
111111110101111001 // -647 -647.25
000000001010101000 // 680 679.73
111111110100110111 // -713 -713.21
000000001011101100 // 748 747.8
111111110011110000 // -784 -783.69
000000001100110101 // 821 821.08
111111110010100100 // -860 -860.24
000000001110000101 // 901 901.49
111111110001001111 // -945 -945.3
000000001111100000 // 992 992.38
111111101111101100 // -1044 -1043.73
000000010001001101 // 1101 1100.62
111111101101110011 // -1165 -1164.75
000000010011010111 // 1239 1238.71
111111101011010001 // -1327 -1326.55
000000010110011011 // 1435 1434.79
111111100111011010 // -1574 -1573.96
000000011011100011 // 1763 1763.3
111111100000000110 // -2042 -2041.67
000000100111000110 // 2502 2501.72
111111001010011111 // -3425 -3425.2
000001100010011100 // 6300 6299.88
010100001010001111 // 82575 82574.73
111110111111001111 // -4145 -4145.21
000000011011100101 // 1765 1764.83
111111110001010111 // -937 -937.39
000000001000000101 // 517 517.3
111111111011111001 // -263 -263.41
000000000001011110 // 94 94.35
000000000000011001 // 25 25.43
111111111110001110 // -114 -113.89
000000000010110101 // 181 181.19
111111111100010111 // -233 -233.21
000000000100010010 // 274 273.75
111111111011001111 // -305 -305.44
000000000101001010 // 330 330.2
111111111010100011 // -349 -349.37
000000000101101100 // 364 363.85
111111111010001010 // -374 -374.34
000000000101111101 // 381 381.42
111111111001111110 // -386 -385.61
000000000110000011 // 387 387.31
111111111001111101 // -387 -386.85
000000000110000000 // 384 384.48
111111111010000100 // -380 -380.43
000000000101110111 // 375 374.85
111111111010010000 // -368 -367.93
000000000101101000 // 360 359.87
111111111010100001 // -351 -350.84
000000000101010101 // 341 340.96
111111111010110110 // -330 -330.35
000000000100111111 // 319 319.1
111111111011001101 // -307 -307.32
000000000100100111 // 295 295.08
111111111011100110 // -282 -282.48
000000000100001110 // 270 269.6
111111111011111111 // -257 -256.58
000000000011110011 // 243 243.48
111111111100011010 // -230 -230.35
000000000011011001 // 217 217.25
111111111100110100 // -204 -204.26
000000000010111111 // 191 191.44
111111111101001101 // -179 -178.84
000000000010100110 // 166 166.48
111111111101100110 // -154 -154.43
000000000010001111 // 143 142.73
111111111101111101 // -131 -131.45
000000000001111001 // 121 120.59
111111111110010010 // -110 -110.22
000000000001100100 // 100 100.39
111111111110100101 // -91 -91.2
000000000001010011 // 83 82.65
111111111110110101 // -75 -74.85
000000000001000100 // 68 67.89
111111111111000010 // -62 -62.03
000000000000111001 // 57 57.33
111111111111001010 // -54 -54.12
000000000000110100 // 52 52.4
111111111111001100 // -52 -51.78
000000000000110000 // 48 48.15
111111111111101001 // -23 -23.23
111111111101010100 // -172 -171.9
111111111111100101 // -27 -26.86
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000
000000000000000000

1021
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8.py 100644
Wyświetl plik

Plik diff jest za duży Load Diff

263
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8A.mif 100644
Wyświetl plik

@ -0,0 +1,263 @@
DEPTH = 256;
WIDTH = 18;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT
BEGIN
00 : 3FFE5; -- -27 -26.86
01 : 3FF54; -- -172 -171.9
02 : 3FFE9; -- -23 -23.23
03 : 00030; -- 48 48.15
04 : 3FFCC; -- -52 -51.78
05 : 00034; -- 52 52.4
06 : 3FFCA; -- -54 -54.12
07 : 00039; -- 57 57.33
08 : 3FFC2; -- -62 -62.03
09 : 00044; -- 68 67.89
0A : 3FFB5; -- -75 -74.85
0B : 00053; -- 83 82.65
0C : 3FFA5; -- -91 -91.2
0D : 00064; -- 100 100.39
0E : 3FF92; -- -110 -110.22
0F : 00079; -- 121 120.59
10 : 3FF7D; -- -131 -131.45
11 : 0008F; -- 143 142.73
12 : 3FF66; -- -154 -154.43
13 : 000A6; -- 166 166.48
14 : 3FF4D; -- -179 -178.84
15 : 000BF; -- 191 191.44
16 : 3FF34; -- -204 -204.26
17 : 000D9; -- 217 217.25
18 : 3FF1A; -- -230 -230.35
19 : 000F3; -- 243 243.48
1A : 3FEFF; -- -257 -256.58
1B : 0010E; -- 270 269.6
1C : 3FEE6; -- -282 -282.48
1D : 00127; -- 295 295.08
1E : 3FECD; -- -307 -307.32
1F : 0013F; -- 319 319.1
20 : 3FEB6; -- -330 -330.35
21 : 00155; -- 341 340.96
22 : 3FEA1; -- -351 -350.84
23 : 00168; -- 360 359.87
24 : 3FE90; -- -368 -367.93
25 : 00177; -- 375 374.85
26 : 3FE84; -- -380 -380.43
27 : 00180; -- 384 384.48
28 : 3FE7D; -- -387 -386.85
29 : 00183; -- 387 387.31
2A : 3FE7E; -- -386 -385.61
2B : 0017D; -- 381 381.42
2C : 3FE8A; -- -374 -374.34
2D : 0016C; -- 364 363.85
2E : 3FEA3; -- -349 -349.37
2F : 0014A; -- 330 330.2
30 : 3FECF; -- -305 -305.44
31 : 00112; -- 274 273.75
32 : 3FF17; -- -233 -233.21
33 : 000B5; -- 181 181.19
34 : 3FF8E; -- -114 -113.89
35 : 00019; -- 25 25.43
36 : 0005E; -- 94 94.35
37 : 3FEF9; -- -263 -263.41
38 : 00205; -- 517 517.3
39 : 3FC57; -- -937 -937.39
3A : 006E5; -- 1765 1764.83
3B : 3EFCF; -- -4145 -4145.21
3C : 1428F; -- 82575 82574.73
3D : 0189C; -- 6300 6299.88
3E : 3F29F; -- -3425 -3425.2
3F : 009C6; -- 2502 2501.72
40 : 3F806; -- -2042 -2041.67
41 : 006E3; -- 1763 1763.3
42 : 3F9DA; -- -1574 -1573.96
43 : 0059B; -- 1435 1434.79
44 : 3FAD1; -- -1327 -1326.55
45 : 004D7; -- 1239 1238.71
46 : 3FB73; -- -1165 -1164.75
47 : 0044D; -- 1101 1100.62
48 : 3FBEC; -- -1044 -1043.73
49 : 003E0; -- 992 992.38
4A : 3FC4F; -- -945 -945.3
4B : 00385; -- 901 901.49
4C : 3FCA4; -- -860 -860.24
4D : 00335; -- 821 821.08
4E : 3FCF0; -- -784 -783.69
4F : 002EC; -- 748 747.8
50 : 3FD37; -- -713 -713.21
51 : 002A8; -- 680 679.73
52 : 3FD79; -- -647 -647.25
53 : 00268; -- 616 615.63
54 : 3FDB7; -- -585 -584.84
55 : 0022B; -- 555 554.86
56 : 3FDF2; -- -526 -525.69
57 : 001F1; -- 497 497.3
58 : 3FE2A; -- -470 -469.66
59 : 001BB; -- 443 442.76
5A : 3FE5F; -- -417 -416.6
5B : 00187; -- 391 391.17
5C : 3FE92; -- -366 -366.49
5D : 00157; -- 343 342.59
5E : 3FEC0; -- -320 -319.51
5F : 00129; -- 297 297.25
60 : 3FEEC; -- -276 -275.81
61 : 000FF; -- 255 255.19
62 : 3FF15; -- -235 -235.44
63 : 000D9; -- 217 216.54
64 : 3FF39; -- -199 -198.52
65 : 000B5; -- 181 181.34
66 : 3FF5B; -- -165 -165.03
67 : 00096; -- 150 149.6
68 : 3FF79; -- -135 -135.09
69 : 00079; -- 121 121.45
6A : 3FF93; -- -109 -108.71
6B : 00061; -- 97 96.9
6C : 3FFAA; -- -86 -86.06
6D : 0004C; -- 76 76.14
6E : 3FFBD; -- -67 -67.22
6F : 0003B; -- 59 59.32
70 : 3FFCB; -- -53 -52.57
71 : 0002F; -- 47 46.89
72 : 3FFD6; -- -42 -42.32
73 : 00026; -- 38 38.4
74 : 3FFDE; -- -34 -33.9
75 : 00017; -- 23 23.45
76 : 0000B; -- 11 11.29
77 : 3FF4E; -- -178 -178.04
78 : 3FFD7; -- -41 -41.39
79 : 00004; -- 4 4.08
7A : 00000;
7B : 00000;
7C : 00000;
7D : 00000;
7E : 00000;
7F : 00000;
80 : 00000;
81 : 00000;
82 : 00000;
83 : 00000;
84 : 00000;
85 : 00000;
86 : 00000;
87 : 00000;
88 : 00000;
89 : 00000;
8A : 00000;
8B : 00000;
8C : 00000;
8D : 00000;
8E : 00000;
8F : 00000;
90 : 00000;
91 : 00000;
92 : 00000;
93 : 00000;
94 : 00000;
95 : 00000;
96 : 00000;
97 : 00000;
98 : 00000;
99 : 00000;
9A : 00000;
9B : 00000;
9C : 00000;
9D : 00000;
9E : 00000;
9F : 00000;
A0 : 00000;
A1 : 00000;
A2 : 00000;
A3 : 00000;
A4 : 00000;
A5 : 00000;
A6 : 00000;
A7 : 00000;
A8 : 00000;
A9 : 00000;
AA : 00000;
AB : 00000;
AC : 00000;
AD : 00000;
AE : 00000;
AF : 00000;
B0 : 00000;
B1 : 00000;
B2 : 00000;
B3 : 00000;
B4 : 00000;
B5 : 00000;
B6 : 00000;
B7 : 00000;
B8 : 00000;
B9 : 00000;
BA : 00000;
BB : 00000;
BC : 00000;
BD : 00000;
BE : 00000;
BF : 00000;
C0 : 00000;
C1 : 00000;
C2 : 00000;
C3 : 00000;
C4 : 00000;
C5 : 00000;
C6 : 00000;
C7 : 00000;
C8 : 00000;
C9 : 00000;
CA : 00000;
CB : 00000;
CC : 00000;
CD : 00000;
CE : 00000;
CF : 00000;
D0 : 00000;
D1 : 00000;
D2 : 00000;
D3 : 00000;
D4 : 00000;
D5 : 00000;
D6 : 00000;
D7 : 00000;
D8 : 00000;
D9 : 00000;
DA : 00000;
DB : 00000;
DC : 00000;
DD : 00000;
DE : 00000;
DF : 00000;
E0 : 00000;
E1 : 00000;
E2 : 00000;
E3 : 00000;
E4 : 00000;
E5 : 00000;
E6 : 00000;
E7 : 00000;
E8 : 00000;
E9 : 00000;
EA : 00000;
EB : 00000;
EC : 00000;
ED : 00000;
EE : 00000;
EF : 00000;
F0 : 00000;
F1 : 00000;
F2 : 00000;
F3 : 00000;
F4 : 00000;
F5 : 00000;
F6 : 00000;
F7 : 00000;
F8 : 00000;
F9 : 00000;
FA : 00000;
FB : 00000;
FC : 00000;
FD : 00000;
FE : 00000;
FF : 00000;
END;

256
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8A.txt 100644
Wyświetl plik

@ -0,0 +1,256 @@
111111111111100101 // -27 -26.86
111111111101010100 // -172 -171.9
111111111111101001 // -23 -23.23
000000000000110000 // 48 48.15
111111111111001100 // -52 -51.78
000000000000110100 // 52 52.4
111111111111001010 // -54 -54.12
000000000000111001 // 57 57.33
111111111111000010 // -62 -62.03
000000000001000100 // 68 67.89
111111111110110101 // -75 -74.85
000000000001010011 // 83 82.65
111111111110100101 // -91 -91.2
000000000001100100 // 100 100.39
111111111110010010 // -110 -110.22
000000000001111001 // 121 120.59
111111111101111101 // -131 -131.45
000000000010001111 // 143 142.73
111111111101100110 // -154 -154.43
000000000010100110 // 166 166.48
111111111101001101 // -179 -178.84
000000000010111111 // 191 191.44
111111111100110100 // -204 -204.26
000000000011011001 // 217 217.25
111111111100011010 // -230 -230.35
000000000011110011 // 243 243.48
111111111011111111 // -257 -256.58
000000000100001110 // 270 269.6
111111111011100110 // -282 -282.48
000000000100100111 // 295 295.08
111111111011001101 // -307 -307.32
000000000100111111 // 319 319.1
111111111010110110 // -330 -330.35
000000000101010101 // 341 340.96
111111111010100001 // -351 -350.84
000000000101101000 // 360 359.87
111111111010010000 // -368 -367.93
000000000101110111 // 375 374.85
111111111010000100 // -380 -380.43
000000000110000000 // 384 384.48
111111111001111101 // -387 -386.85
000000000110000011 // 387 387.31
111111111001111110 // -386 -385.61
000000000101111101 // 381 381.42
111111111010001010 // -374 -374.34
000000000101101100 // 364 363.85
111111111010100011 // -349 -349.37
000000000101001010 // 330 330.2
111111111011001111 // -305 -305.44
000000000100010010 // 274 273.75
111111111100010111 // -233 -233.21
000000000010110101 // 181 181.19
111111111110001110 // -114 -113.89
000000000000011001 // 25 25.43
000000000001011110 // 94 94.35
111111111011111001 // -263 -263.41
000000001000000101 // 517 517.3
111111110001010111 // -937 -937.39
000000011011100101 // 1765 1764.83
111110111111001111 // -4145 -4145.21
010100001010001111 // 82575 82574.73
000001100010011100 // 6300 6299.88
111111001010011111 // -3425 -3425.2
000000100111000110 // 2502 2501.72
111111100000000110 // -2042 -2041.67
000000011011100011 // 1763 1763.3
111111100111011010 // -1574 -1573.96
000000010110011011 // 1435 1434.79
111111101011010001 // -1327 -1326.55
000000010011010111 // 1239 1238.71
111111101101110011 // -1165 -1164.75
000000010001001101 // 1101 1100.62
111111101111101100 // -1044 -1043.73
000000001111100000 // 992 992.38
111111110001001111 // -945 -945.3
000000001110000101 // 901 901.49
111111110010100100 // -860 -860.24
000000001100110101 // 821 821.08
111111110011110000 // -784 -783.69
000000001011101100 // 748 747.8
111111110100110111 // -713 -713.21
000000001010101000 // 680 679.73
111111110101111001 // -647 -647.25
000000001001101000 // 616 615.63
111111110110110111 // -585 -584.84
000000001000101011 // 555 554.86
111111110111110010 // -526 -525.69
000000000111110001 // 497 497.3
111111111000101010 // -470 -469.66
000000000110111011 // 443 442.76
111111111001011111 // -417 -416.6
000000000110000111 // 391 391.17
111111111010010010 // -366 -366.49
000000000101010111 // 343 342.59
111111111011000000 // -320 -319.51
000000000100101001 // 297 297.25
111111111011101100 // -276 -275.81
000000000011111111 // 255 255.19
111111111100010101 // -235 -235.44
000000000011011001 // 217 216.54
111111111100111001 // -199 -198.52
000000000010110101 // 181 181.34
111111111101011011 // -165 -165.03
000000000010010110 // 150 149.6
111111111101111001 // -135 -135.09
000000000001111001 // 121 121.45
111111111110010011 // -109 -108.71
000000000001100001 // 97 96.9
111111111110101010 // -86 -86.06
000000000001001100 // 76 76.14
111111111110111101 // -67 -67.22
000000000000111011 // 59 59.32
111111111111001011 // -53 -52.57
000000000000101111 // 47 46.89
111111111111010110 // -42 -42.32
000000000000100110 // 38 38.4
111111111111011110 // -34 -33.9
000000000000010111 // 23 23.45
000000000000001011 // 11 11.29
111111111101001110 // -178 -178.04
111111111111010111 // -41 -41.39
000000000000000100 // 4 4.08
000000000000000000
000000000000000000
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263
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8B.mif 100644
Wyświetl plik

@ -0,0 +1,263 @@
DEPTH = 256;
WIDTH = 18;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT
BEGIN
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01 : 3FF61; -- -159 -159.46
02 : 3FFC5; -- -59 -59.24
03 : 00044; -- 68 68.31
04 : 3FFC1; -- -63 -63.24
05 : 0003B; -- 59 59.19
06 : 3FFC6; -- -58 -58.15
07 : 0003B; -- 59 59.39
08 : 3FFC2; -- -62 -62.36
09 : 00042; -- 66 66.45
0A : 3FFB9; -- -71 -71.45
0B : 0004D; -- 77 77.01
0C : 3FFAD; -- -83 -82.98
0D : 00059; -- 89 89.21
0E : 3FFA0; -- -96 -95.66
0F : 00066; -- 102 102.2
10 : 3FF93; -- -109 -108.74
11 : 00073; -- 115 115.18
12 : 3FF86; -- -122 -121.52
13 : 00080; -- 128 127.63
14 : 3FF7B; -- -133 -133.43
15 : 0008B; -- 139 138.84
16 : 3FF70; -- -144 -143.8
17 : 00094; -- 148 148.23
18 : 3FF68; -- -152 -152.02
19 : 0009B; -- 155 155.04
1A : 3FF63; -- -157 -157.22
1B : 0009E; -- 158 158.43
1C : 3FF61; -- -159 -158.56
1D : 0009D; -- 157 157.43
1E : 3FF65; -- -155 -154.9
1F : 00097; -- 151 150.81
20 : 3FF6F; -- -145 -145.01
21 : 00089; -- 137 137.32
22 : 3FF80; -- -128 -127.55
23 : 00073; -- 115 115.47
24 : 3FF9B; -- -101 -100.83
25 : 00053; -- 83 83.3
26 : 3FFC1; -- -63 -62.53
27 : 00026; -- 38 38.14
28 : 3FFF6; -- -10 -9.71
29 : 3FFE9; -- -23 -23.27
2A : 0003D; -- 61 61.44
2B : 3FF96; -- -106 -105.57
2C : 0009D; -- 157 156.63
2D : 3FF28; -- -216 -215.84
2E : 0011D; -- 285 284.72
2F : 3FE93; -- -365 -365.16
30 : 001CC; -- 460 459.69
31 : 3FDC4; -- -572 -571.84
32 : 002C3; -- 707 706.59
33 : 3FC99; -- -871 -870.93
34 : 00433; -- 1075 1075.14
35 : 3FAC9; -- -1335 -1335.25
36 : 0068E; -- 1678 1678.01
37 : 3F799; -- -2151 -2150.57
38 : 00B1D; -- 2845 2845.05
39 : 3F07F; -- -3969 -3968.7
3A : 017DE; -- 6110 6109.58
3B : 3D1C6; -- -11834 -11833.59
3C : 1327A; -- 78458 78457.77
3D : 049BC; -- 18876 18875.93
3E : 3DDAD; -- -8787 -8787.3
3F : 016E3; -- 5859 5859.41
40 : 3EE97; -- -4457 -4456.63
41 : 00E2C; -- 3628 3628.21
42 : 3F3FB; -- -3077 -3076.99
43 : 00A79; -- 2681 2680.7
44 : 3F6B4; -- -2380 -2379.71
45 : 0085E; -- 2142 2141.55
46 : 3F865; -- -1947 -1946.74
47 : 006F7; -- 1783 1783.15
48 : 3F995; -- -1643 -1642.85
49 : 005F0; -- 1520 1520.49
4A : 3FA7C; -- -1412 -1412.14
4B : 00523; -- 1315 1314.94
4C : 3FB35; -- -1227 -1226.76
4D : 0047A; -- 1146 1146.07
4E : 3FBD0; -- -1072 -1071.73
4F : 003EB; -- 1003 1002.81
50 : 3FC55; -- -939 -938.55
51 : 0036E; -- 878 878.37
52 : 3FCCA; -- -822 -821.78
53 : 00300; -- 768 768.38
54 : 3FD32; -- -718 -717.9
55 : 0029E; -- 670 670.1
56 : 3FD8F; -- -625 -624.82
57 : 00246; -- 582 581.86
58 : 3FDE3; -- -541 -541.06
59 : 001F6; -- 502 502.28
5A : 3FE2F; -- -465 -465.43
5B : 001AE; -- 430 430.4
5C : 3FE73; -- -397 -397.15
5D : 0016E; -- 366 365.61
5E : 3FEB0; -- -336 -335.77
5F : 00134; -- 308 307.54
60 : 3FEE7; -- -281 -280.87
61 : 00100; -- 256 255.7
62 : 3FF18; -- -232 -232.01
63 : 000D2; -- 210 209.77
64 : 3FF43; -- -189 -188.93
65 : 000A9; -- 169 169.4
66 : 3FF69; -- -151 -151.2
67 : 00086; -- 134 134.29
68 : 3FF89; -- -119 -118.65
69 : 00068; -- 104 104.2
6A : 3FFA5; -- -91 -90.96
6B : 0004F; -- 79 78.88
6C : 3FFBC; -- -68 -67.99
6D : 0003A; -- 58 58.17
6E : 3FFCF; -- -49 -49.45
6F : 0002A; -- 42 41.79
70 : 3FFDD; -- -35 -35.2
71 : 0001D; -- 29 29.46
72 : 3FFE8; -- -24 -24.38
73 : 00013; -- 19 19.15
74 : 3FFF4; -- -12 -12.0
75 : 3FFFD; -- -3 -2.81
76 : 0002A; -- 42 41.57
77 : 3FF4F; -- -177 -176.7
78 : 3FFC5; -- -59 -58.91
79 : 00003; -- 3 2.7
7A : 00000;
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81 : 00000;
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BA : 00000;
BB : 00000;
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C3 : 00000;
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FD : 00000;
FE : 00000;
FF : 00000;
END;

256
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8B.txt 100644
Wyświetl plik

@ -0,0 +1,256 @@
111111111111110000 // -16 -15.55
111111111101100001 // -159 -159.46
111111111111000101 // -59 -59.24
000000000001000100 // 68 68.31
111111111111000001 // -63 -63.24
000000000000111011 // 59 59.19
111111111111000110 // -58 -58.15
000000000000111011 // 59 59.39
111111111111000010 // -62 -62.36
000000000001000010 // 66 66.45
111111111110111001 // -71 -71.45
000000000001001101 // 77 77.01
111111111110101101 // -83 -82.98
000000000001011001 // 89 89.21
111111111110100000 // -96 -95.66
000000000001100110 // 102 102.2
111111111110010011 // -109 -108.74
000000000001110011 // 115 115.18
111111111110000110 // -122 -121.52
000000000010000000 // 128 127.63
111111111101111011 // -133 -133.43
000000000010001011 // 139 138.84
111111111101110000 // -144 -143.8
000000000010010100 // 148 148.23
111111111101101000 // -152 -152.02
000000000010011011 // 155 155.04
111111111101100011 // -157 -157.22
000000000010011110 // 158 158.43
111111111101100001 // -159 -158.56
000000000010011101 // 157 157.43
111111111101100101 // -155 -154.9
000000000010010111 // 151 150.81
111111111101101111 // -145 -145.01
000000000010001001 // 137 137.32
111111111110000000 // -128 -127.55
000000000001110011 // 115 115.47
111111111110011011 // -101 -100.83
000000000001010011 // 83 83.3
111111111111000001 // -63 -62.53
000000000000100110 // 38 38.14
111111111111110110 // -10 -9.71
111111111111101001 // -23 -23.27
000000000000111101 // 61 61.44
111111111110010110 // -106 -105.57
000000000010011101 // 157 156.63
111111111100101000 // -216 -215.84
000000000100011101 // 285 284.72
111111111010010011 // -365 -365.16
000000000111001100 // 460 459.69
111111110111000100 // -572 -571.84
000000001011000011 // 707 706.59
111111110010011001 // -871 -870.93
000000010000110011 // 1075 1075.14
111111101011001001 // -1335 -1335.25
000000011010001110 // 1678 1678.01
111111011110011001 // -2151 -2150.57
000000101100011101 // 2845 2845.05
111111000001111111 // -3969 -3968.7
000001011111011110 // 6110 6109.58
111101000111000110 // -11834 -11833.59
010011001001111010 // 78458 78457.77
000100100110111100 // 18876 18875.93
111101110110101101 // -8787 -8787.3
000001011011100011 // 5859 5859.41
111110111010010111 // -4457 -4456.63
000000111000101100 // 3628 3628.21
111111001111111011 // -3077 -3076.99
000000101001111001 // 2681 2680.7
111111011010110100 // -2380 -2379.71
000000100001011110 // 2142 2141.55
111111100001100101 // -1947 -1946.74
000000011011110111 // 1783 1783.15
111111100110010101 // -1643 -1642.85
000000010111110000 // 1520 1520.49
111111101001111100 // -1412 -1412.14
000000010100100011 // 1315 1314.94
111111101100110101 // -1227 -1226.76
000000010001111010 // 1146 1146.07
111111101111010000 // -1072 -1071.73
000000001111101011 // 1003 1002.81
111111110001010101 // -939 -938.55
000000001101101110 // 878 878.37
111111110011001010 // -822 -821.78
000000001100000000 // 768 768.38
111111110100110010 // -718 -717.9
000000001010011110 // 670 670.1
111111110110001111 // -625 -624.82
000000001001000110 // 582 581.86
111111110111100011 // -541 -541.06
000000000111110110 // 502 502.28
111111111000101111 // -465 -465.43
000000000110101110 // 430 430.4
111111111001110011 // -397 -397.15
000000000101101110 // 366 365.61
111111111010110000 // -336 -335.77
000000000100110100 // 308 307.54
111111111011100111 // -281 -280.87
000000000100000000 // 256 255.7
111111111100011000 // -232 -232.01
000000000011010010 // 210 209.77
111111111101000011 // -189 -188.93
000000000010101001 // 169 169.4
111111111101101001 // -151 -151.2
000000000010000110 // 134 134.29
111111111110001001 // -119 -118.65
000000000001101000 // 104 104.2
111111111110100101 // -91 -90.96
000000000001001111 // 79 78.88
111111111110111100 // -68 -67.99
000000000000111010 // 58 58.17
111111111111001111 // -49 -49.45
000000000000101010 // 42 41.79
111111111111011101 // -35 -35.2
000000000000011101 // 29 29.46
111111111111101000 // -24 -24.38
000000000000010011 // 19 19.15
111111111111110100 // -12 -12.0
111111111111111101 // -3 -2.81
000000000000101010 // 42 41.57
111111111101001111 // -177 -176.7
111111111111000101 // -59 -58.91
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263
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8C.mif 100644
Wyświetl plik

@ -0,0 +1,263 @@
DEPTH = 256;
WIDTH = 18;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT
BEGIN
00 : 3FFF9; -- -7 -7.35
01 : 3FF72; -- -142 -142.25
02 : 3FFA2; -- -94 -93.93
03 : 00051; -- 81 81.41
04 : 3FFBD; -- -67 -66.62
05 : 0003A; -- 58 57.79
06 : 3FFCA; -- -54 -53.88
07 : 00035; -- 53 52.87
08 : 3FFCA; -- -54 -53.67
09 : 00037; -- 55 55.42
0A : 3FFC6; -- -58 -57.78
0B : 0003C; -- 60 60.34
0C : 3FFC1; -- -63 -62.92
0D : 00041; -- 65 65.34
0E : 3FFBC; -- -68 -67.55
0F : 00045; -- 69 69.37
10 : 3FFB9; -- -71 -70.72
11 : 00047; -- 71 71.49
12 : 3FFB8; -- -72 -71.62
13 : 00047; -- 71 71.0
14 : 3FFBA; -- -70 -69.52
15 : 00043; -- 67 67.07
16 : 3FFC0; -- -64 -63.59
17 : 0003B; -- 59 58.95
18 : 3FFCB; -- -53 -53.03
19 : 0002E; -- 46 45.67
1A : 3FFDB; -- -37 -36.78
1B : 0001A; -- 26 26.2
1C : 3FFF2; -- -14 -13.79
1D : 3FFFF; -- -1 -0.67
1E : 00011; -- 17 17.35
1F : 3FFDC; -- -36 -36.44
20 : 0003A; -- 58 58.13
21 : 3FFAD; -- -83 -82.67
22 : 0006E; -- 110 110.29
23 : 3FF73; -- -141 -141.3
24 : 000B0; -- 176 176.05
25 : 3FF29; -- -215 -214.95
26 : 00102; -- 258 258.48
27 : 3FECD; -- -307 -307.13
28 : 00169; -- 361 361.49
29 : 3FE5A; -- -422 -422.28
2A : 001EA; -- 490 490.39
2B : 3FDC9; -- -567 -566.93
2C : 0028D; -- 653 653.24
2D : 3FD11; -- -751 -751.06
2E : 0035F; -- 863 862.51
2F : 3FC22; -- -990 -990.32
30 : 00472; -- 1138 1138.16
31 : 3FAE1; -- -1311 -1311.07
32 : 005EC; -- 1516 1516.11
33 : 3F91D; -- -1763 -1763.2
34 : 00813; -- 2067 2066.95
35 : 3F66E; -- -2450 -2450.05
36 : 00B86; -- 2950 2949.91
37 : 3F1D0; -- -3632 -3631.86
38 : 0120E; -- 4622 4621.76
39 : 3E7CB; -- -6197 -6197.2
3A : 0239E; -- 9118 9117.56
3B : 3BFBA; -- -16454 -16453.82
3C : 113C2; -- 70594 70593.52
3D : 07FB5; -- 32693 32692.86
3E : 3CB20; -- -13536 -13535.56
3F : 021A7; -- 8615 8615.49
40 : 3E733; -- -6349 -6349.16
41 : 013AE; -- 5038 5038.36
42 : 3EFAD; -- -4179 -4178.55
43 : 00DEF; -- 3567 3567.43
44 : 3F3DC; -- -3108 -3108.0
45 : 00ABC; -- 2748 2747.95
46 : 3F668; -- -2456 -2456.39
47 : 008A6; -- 2214 2214.12
48 : 3F827; -- -2009 -2008.64
49 : 00727; -- 1831 1831.44
4A : 3F974; -- -1676 -1676.38
4B : 00603; -- 1539 1538.98
4C : 3FA78; -- -1416 -1415.97
4D : 00519; -- 1305 1304.93
4E : 3FB4C; -- -1204 -1204.01
4F : 00458; -- 1112 1111.72
50 : 3FBFD; -- -1027 -1026.88
51 : 003B5; -- 949 948.53
52 : 3FC94; -- -876 -875.9
53 : 00328; -- 808 808.35
54 : 3FD17; -- -745 -745.42
55 : 002AF; -- 687 686.69
56 : 3FD88; -- -632 -631.83
57 : 00245; -- 581 580.51
58 : 3FDEC; -- -532 -532.46
59 : 001E7; -- 487 487.43
5A : 3FE43; -- -445 -445.25
5B : 00196; -- 406 405.74
5C : 3FE8F; -- -369 -368.76
5D : 0014E; -- 334 334.19
5E : 3FED2; -- -302 -301.95
5F : 00110; -- 272 271.89
60 : 3FF0C; -- -244 -243.89
61 : 000DA; -- 218 217.86
62 : 3FF3E; -- -194 -193.74
63 : 000AB; -- 171 171.42
64 : 3FF69; -- -151 -150.82
65 : 00084; -- 132 131.84
66 : 3FF8E; -- -114 -114.43
67 : 00063; -- 99 98.53
68 : 3FFAC; -- -84 -84.09
69 : 00047; -- 71 70.98
6A : 3FFC5; -- -59 -59.2
6B : 00031; -- 49 48.67
6C : 3FFD9; -- -39 -39.35
6D : 0001F; -- 31 31.11
6E : 3FFE8; -- -24 -23.92
6F : 00012; -- 18 17.68
70 : 3FFF4; -- -12 -12.31
71 : 00007; -- 7 7.47
72 : 3FFFD; -- -3 -2.82
73 : 3FFFD; -- -3 -2.68
74 : 0000B; -- 11 10.98
75 : 3FFE4; -- -28 -27.52
76 : 00041; -- 65 65.16
77 : 3FF59; -- -167 -167.26
78 : 3FFB1; -- -79 -78.87
79 : 00003; -- 3 2.53
7A : 00000;
7B : 00000;
7C : 00000;
7D : 00000;
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CE : 00000;
CF : 00000;
D0 : 00000;
D1 : 00000;
D2 : 00000;
D3 : 00000;
D4 : 00000;
D5 : 00000;
D6 : 00000;
D7 : 00000;
D8 : 00000;
D9 : 00000;
DA : 00000;
DB : 00000;
DC : 00000;
DD : 00000;
DE : 00000;
DF : 00000;
E0 : 00000;
E1 : 00000;
E2 : 00000;
E3 : 00000;
E4 : 00000;
E5 : 00000;
E6 : 00000;
E7 : 00000;
E8 : 00000;
E9 : 00000;
EA : 00000;
EB : 00000;
EC : 00000;
ED : 00000;
EE : 00000;
EF : 00000;
F0 : 00000;
F1 : 00000;
F2 : 00000;
F3 : 00000;
F4 : 00000;
F5 : 00000;
F6 : 00000;
F7 : 00000;
F8 : 00000;
F9 : 00000;
FA : 00000;
FB : 00000;
FC : 00000;
FD : 00000;
FE : 00000;
FF : 00000;
END;

256
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@ -0,0 +1,256 @@
111111111111111001 // -7 -7.35
111111111101110010 // -142 -142.25
111111111110100010 // -94 -93.93
000000000001010001 // 81 81.41
111111111110111101 // -67 -66.62
000000000000111010 // 58 57.79
111111111111001010 // -54 -53.88
000000000000110101 // 53 52.87
111111111111001010 // -54 -53.67
000000000000110111 // 55 55.42
111111111111000110 // -58 -57.78
000000000000111100 // 60 60.34
111111111111000001 // -63 -62.92
000000000001000001 // 65 65.34
111111111110111100 // -68 -67.55
000000000001000101 // 69 69.37
111111111110111001 // -71 -70.72
000000000001000111 // 71 71.49
111111111110111000 // -72 -71.62
000000000001000111 // 71 71.0
111111111110111010 // -70 -69.52
000000000001000011 // 67 67.07
111111111111000000 // -64 -63.59
000000000000111011 // 59 58.95
111111111111001011 // -53 -53.03
000000000000101110 // 46 45.67
111111111111011011 // -37 -36.78
000000000000011010 // 26 26.2
111111111111110010 // -14 -13.79
111111111111111111 // -1 -0.67
000000000000010001 // 17 17.35
111111111111011100 // -36 -36.44
000000000000111010 // 58 58.13
111111111110101101 // -83 -82.67
000000000001101110 // 110 110.29
111111111101110011 // -141 -141.3
000000000010110000 // 176 176.05
111111111100101001 // -215 -214.95
000000000100000010 // 258 258.48
111111111011001101 // -307 -307.13
000000000101101001 // 361 361.49
111111111001011010 // -422 -422.28
000000000111101010 // 490 490.39
111111110111001001 // -567 -566.93
000000001010001101 // 653 653.24
111111110100010001 // -751 -751.06
000000001101011111 // 863 862.51
111111110000100010 // -990 -990.32
000000010001110010 // 1138 1138.16
111111101011100001 // -1311 -1311.07
000000010111101100 // 1516 1516.11
111111100100011101 // -1763 -1763.2
000000100000010011 // 2067 2066.95
111111011001101110 // -2450 -2450.05
000000101110000110 // 2950 2949.91
111111000111010000 // -3632 -3631.86
000001001000001110 // 4622 4621.76
111110011111001011 // -6197 -6197.2
000010001110011110 // 9118 9117.56
111011111110111010 // -16454 -16453.82
010001001111000010 // 70594 70593.52
000111111110110101 // 32693 32692.86
111100101100100000 // -13536 -13535.56
000010000110100111 // 8615 8615.49
111110011100110011 // -6349 -6349.16
000001001110101110 // 5038 5038.36
111110111110101101 // -4179 -4178.55
000000110111101111 // 3567 3567.43
111111001111011100 // -3108 -3108.0
000000101010111100 // 2748 2747.95
111111011001101000 // -2456 -2456.39
000000100010100110 // 2214 2214.12
111111100000100111 // -2009 -2008.64
000000011100100111 // 1831 1831.44
111111100101110100 // -1676 -1676.38
000000011000000011 // 1539 1538.98
111111101001111000 // -1416 -1415.97
000000010100011001 // 1305 1304.93
111111101101001100 // -1204 -1204.01
000000010001011000 // 1112 1111.72
111111101111111101 // -1027 -1026.88
000000001110110101 // 949 948.53
111111110010010100 // -876 -875.9
000000001100101000 // 808 808.35
111111110100010111 // -745 -745.42
000000001010101111 // 687 686.69
111111110110001000 // -632 -631.83
000000001001000101 // 581 580.51
111111110111101100 // -532 -532.46
000000000111100111 // 487 487.43
111111111001000011 // -445 -445.25
000000000110010110 // 406 405.74
111111111010001111 // -369 -368.76
000000000101001110 // 334 334.19
111111111011010010 // -302 -301.95
000000000100010000 // 272 271.89
111111111100001100 // -244 -243.89
000000000011011010 // 218 217.86
111111111100111110 // -194 -193.74
000000000010101011 // 171 171.42
111111111101101001 // -151 -150.82
000000000010000100 // 132 131.84
111111111110001110 // -114 -114.43
000000000001100011 // 99 98.53
111111111110101100 // -84 -84.09
000000000001000111 // 71 70.98
111111111111000101 // -59 -59.2
000000000000110001 // 49 48.67
111111111111011001 // -39 -39.35
000000000000011111 // 31 31.11
111111111111101000 // -24 -23.92
000000000000010010 // 18 17.68
111111111111110100 // -12 -12.31
000000000000000111 // 7 7.47
111111111111111101 // -3 -2.82
111111111111111101 // -3 -2.68
000000000000001011 // 11 10.98
111111111111100100 // -28 -27.52
000000000001000001 // 65 65.16
111111111101011001 // -167 -167.26
111111111110110001 // -79 -78.87
000000000000000011 // 3 2.53
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263
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8D.mif 100644
Wyświetl plik

@ -0,0 +1,263 @@
DEPTH = 256;
WIDTH = 18;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT
BEGIN
00 : 3FFFE; -- -2 -1.94
01 : 3FF86; -- -122 -121.96
02 : 3FF83; -- -125 -124.78
03 : 00056; -- 86 85.67
04 : 3FFC3; -- -61 -61.32
05 : 00030; -- 48 48.33
06 : 3FFD6; -- -42 -41.94
07 : 00027; -- 39 38.81
08 : 3FFDB; -- -37 -37.37
09 : 00025; -- 37 36.59
0A : 3FFDC; -- -36 -36.05
0B : 00023; -- 35 35.32
0C : 3FFDE; -- -34 -34.22
0D : 00021; -- 33 32.56
0E : 3FFE2; -- -30 -30.3
0F : 0001B; -- 27 27.25
10 : 3FFE9; -- -23 -23.31
11 : 00012; -- 18 18.39
12 : 3FFF4; -- -12 -12.43
13 : 00005; -- 5 5.29
14 : 00003; -- 3 3.12
15 : 3FFF3; -- -13 -12.93
16 : 00018; -- 24 24.2
17 : 3FFDB; -- -37 -37.06
18 : 00034; -- 52 51.65
19 : 3FFBC; -- -68 -68.12
1A : 00057; -- 87 86.58
1B : 3FF95; -- -107 -107.18
1C : 00082; -- 130 130.09
1D : 3FF64; -- -156 -155.52
1E : 000B8; -- 184 183.64
1F : 3FF29; -- -215 -214.65
20 : 000F9; -- 249 248.75
21 : 3FEE2; -- -286 -286.21
22 : 00147; -- 327 327.27
23 : 3FE8C; -- -372 -372.28
24 : 001A6; -- 422 421.61
25 : 3FE24; -- -476 -475.72
26 : 00217; -- 535 535.1
27 : 3FDA8; -- -600 -600.31
28 : 002A0; -- 672 671.99
29 : 3FD11; -- -751 -750.96
2A : 00346; -- 838 838.22
2B : 3FC59; -- -935 -935.01
2C : 00413; -- 1043 1042.86
2D : 3FB74; -- -1164 -1163.7
2E : 00514; -- 1300 1299.93
2F : 3FA51; -- -1455 -1454.65
30 : 00660; -- 1632 1632.02
31 : 3F8D2; -- -1838 -1837.76
32 : 00820; -- 2080 2079.8
33 : 3F6BF; -- -2369 -2369.26
34 : 00AA3; -- 2723 2722.5
35 : 3F3A3; -- -3165 -3164.82
36 : 00E9A; -- 3738 3737.57
37 : 3EE60; -- -4512 -4512.2
38 : 015F9; -- 5625 5624.58
39 : 3E337; -- -7369 -7368.52
3A : 0291A; -- 10522 10521.57
3B : 3B99A; -- -18022 -18022.23
3C : 0E922; -- 59682 59681.81
3D : 0B656; -- 46678 46678.12
3E : 3BE24; -- -16860 -16859.67
3F : 02833; -- 10291 10291.22
40 : 3E31E; -- -7394 -7393.55
41 : 01679; -- 5753 5753.43
42 : 3EDAC; -- -4692 -4692.33
43 : 00F6A; -- 3946 3945.82
44 : 3F2C3; -- -3389 -3389.32
45 : 00B8C; -- 2956 2956.46
46 : 3F5D0; -- -2608 -2608.46
47 : 00911; -- 2321 2321.41
48 : 3F7E0; -- -2080 -2079.75
49 : 00751; -- 1873 1872.92
4A : 3F963; -- -1693 -1693.34
4B : 00600; -- 1536 1535.52
4C : 3FA8D; -- -1395 -1395.45
4D : 004F6; -- 1270 1270.15
4E : 3FB7B; -- -1157 -1157.33
4F : 0041F; -- 1055 1055.14
50 : 3FC3E; -- -962 -962.12
51 : 0036D; -- 877 877.08
52 : 3FCE1; -- -799 -799.08
53 : 002D7; -- 727 727.32
54 : 3FD6B; -- -661 -661.2
55 : 00258; -- 600 600.19
56 : 3FDE0; -- -544 -543.86
57 : 001EC; -- 492 491.77
58 : 3FE44; -- -444 -443.58
59 : 0018F; -- 399 398.98
5A : 3FE9A; -- -358 -357.72
5B : 00140; -- 320 319.58
5C : 3FEE4; -- -284 -284.37
5D : 000FC; -- 252 251.91
5E : 3FF22; -- -222 -222.08
5F : 000C3; -- 195 194.66
60 : 3FF56; -- -170 -169.53
61 : 00093; -- 147 146.52
62 : 3FF82; -- -126 -125.56
63 : 0006B; -- 107 106.52
64 : 3FFA7; -- -89 -89.26
65 : 0004A; -- 74 73.67
66 : 3FFC4; -- -60 -59.68
67 : 0002F; -- 47 47.19
68 : 3FFDC; -- -36 -36.13
69 : 0001A; -- 26 26.35
6A : 3FFEE; -- -18 -17.82
6B : 0000A; -- 10 10.44
6C : 3FFFC; -- -4 -4.14
6D : 3FFFF; -- -1 -1.25
6E : 00006; -- 6 5.77
6F : 3FFF6; -- -10 -9.59
70 : 0000D; -- 13 12.83
71 : 3FFF0; -- -16 -15.93
72 : 00013; -- 19 19.3
73 : 3FFE8; -- -24 -24.03
74 : 00020; -- 32 32.01
75 : 3FFD0; -- -48 -47.8
76 : 00050; -- 80 80.21
77 : 3FF6A; -- -150 -149.71
78 : 3FF9C; -- -100 -100.32
79 : 00001; -- 1 1.17
7A : 00000;
7B : 00000;
7C : 00000;
7D : 00000;
7E : 00000;
7F : 00000;
80 : 00000;
81 : 00000;
82 : 00000;
83 : 00000;
84 : 00000;
85 : 00000;
86 : 00000;
87 : 00000;
88 : 00000;
89 : 00000;
8A : 00000;
8B : 00000;
8C : 00000;
8D : 00000;
8E : 00000;
8F : 00000;
90 : 00000;
91 : 00000;
92 : 00000;
93 : 00000;
94 : 00000;
95 : 00000;
96 : 00000;
97 : 00000;
98 : 00000;
99 : 00000;
9A : 00000;
9B : 00000;
9C : 00000;
9D : 00000;
9E : 00000;
9F : 00000;
A0 : 00000;
A1 : 00000;
A2 : 00000;
A3 : 00000;
A4 : 00000;
A5 : 00000;
A6 : 00000;
A7 : 00000;
A8 : 00000;
A9 : 00000;
AA : 00000;
AB : 00000;
AC : 00000;
AD : 00000;
AE : 00000;
AF : 00000;
B0 : 00000;
B1 : 00000;
B2 : 00000;
B3 : 00000;
B4 : 00000;
B5 : 00000;
B6 : 00000;
B7 : 00000;
B8 : 00000;
B9 : 00000;
BA : 00000;
BB : 00000;
BC : 00000;
BD : 00000;
BE : 00000;
BF : 00000;
C0 : 00000;
C1 : 00000;
C2 : 00000;
C3 : 00000;
C4 : 00000;
C5 : 00000;
C6 : 00000;
C7 : 00000;
C8 : 00000;
C9 : 00000;
CA : 00000;
CB : 00000;
CC : 00000;
CD : 00000;
CE : 00000;
CF : 00000;
D0 : 00000;
D1 : 00000;
D2 : 00000;
D3 : 00000;
D4 : 00000;
D5 : 00000;
D6 : 00000;
D7 : 00000;
D8 : 00000;
D9 : 00000;
DA : 00000;
DB : 00000;
DC : 00000;
DD : 00000;
DE : 00000;
DF : 00000;
E0 : 00000;
E1 : 00000;
E2 : 00000;
E3 : 00000;
E4 : 00000;
E5 : 00000;
E6 : 00000;
E7 : 00000;
E8 : 00000;
E9 : 00000;
EA : 00000;
EB : 00000;
EC : 00000;
ED : 00000;
EE : 00000;
EF : 00000;
F0 : 00000;
F1 : 00000;
F2 : 00000;
F3 : 00000;
F4 : 00000;
F5 : 00000;
F6 : 00000;
F7 : 00000;
F8 : 00000;
F9 : 00000;
FA : 00000;
FB : 00000;
FC : 00000;
FD : 00000;
FE : 00000;
FF : 00000;
END;

256
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8D.txt 100644
Wyświetl plik

@ -0,0 +1,256 @@
111111111111111110 // -2 -1.94
111111111110000110 // -122 -121.96
111111111110000011 // -125 -124.78
000000000001010110 // 86 85.67
111111111111000011 // -61 -61.32
000000000000110000 // 48 48.33
111111111111010110 // -42 -41.94
000000000000100111 // 39 38.81
111111111111011011 // -37 -37.37
000000000000100101 // 37 36.59
111111111111011100 // -36 -36.05
000000000000100011 // 35 35.32
111111111111011110 // -34 -34.22
000000000000100001 // 33 32.56
111111111111100010 // -30 -30.3
000000000000011011 // 27 27.25
111111111111101001 // -23 -23.31
000000000000010010 // 18 18.39
111111111111110100 // -12 -12.43
000000000000000101 // 5 5.29
000000000000000011 // 3 3.12
111111111111110011 // -13 -12.93
000000000000011000 // 24 24.2
111111111111011011 // -37 -37.06
000000000000110100 // 52 51.65
111111111110111100 // -68 -68.12
000000000001010111 // 87 86.58
111111111110010101 // -107 -107.18
000000000010000010 // 130 130.09
111111111101100100 // -156 -155.52
000000000010111000 // 184 183.64
111111111100101001 // -215 -214.65
000000000011111001 // 249 248.75
111111111011100010 // -286 -286.21
000000000101000111 // 327 327.27
111111111010001100 // -372 -372.28
000000000110100110 // 422 421.61
111111111000100100 // -476 -475.72
000000001000010111 // 535 535.1
111111110110101000 // -600 -600.31
000000001010100000 // 672 671.99
111111110100010001 // -751 -750.96
000000001101000110 // 838 838.22
111111110001011001 // -935 -935.01
000000010000010011 // 1043 1042.86
111111101101110100 // -1164 -1163.7
000000010100010100 // 1300 1299.93
111111101001010001 // -1455 -1454.65
000000011001100000 // 1632 1632.02
111111100011010010 // -1838 -1837.76
000000100000100000 // 2080 2079.8
111111011010111111 // -2369 -2369.26
000000101010100011 // 2723 2722.5
111111001110100011 // -3165 -3164.82
000000111010011010 // 3738 3737.57
111110111001100000 // -4512 -4512.2
000001010111111001 // 5625 5624.58
111110001100110111 // -7369 -7368.52
000010100100011010 // 10522 10521.57
111011100110011010 // -18022 -18022.23
001110100100100010 // 59682 59681.81
001011011001010110 // 46678 46678.12
111011111000100100 // -16860 -16859.67
000010100000110011 // 10291 10291.22
111110001100011110 // -7394 -7393.55
000001011001111001 // 5753 5753.43
111110110110101100 // -4692 -4692.33
000000111101101010 // 3946 3945.82
111111001011000011 // -3389 -3389.32
000000101110001100 // 2956 2956.46
111111010111010000 // -2608 -2608.46
000000100100010001 // 2321 2321.41
111111011111100000 // -2080 -2079.75
000000011101010001 // 1873 1872.92
111111100101100011 // -1693 -1693.34
000000011000000000 // 1536 1535.52
111111101010001101 // -1395 -1395.45
000000010011110110 // 1270 1270.15
111111101101111011 // -1157 -1157.33
000000010000011111 // 1055 1055.14
111111110000111110 // -962 -962.12
000000001101101101 // 877 877.08
111111110011100001 // -799 -799.08
000000001011010111 // 727 727.32
111111110101101011 // -661 -661.2
000000001001011000 // 600 600.19
111111110111100000 // -544 -543.86
000000000111101100 // 492 491.77
111111111001000100 // -444 -443.58
000000000110001111 // 399 398.98
111111111010011010 // -358 -357.72
000000000101000000 // 320 319.58
111111111011100100 // -284 -284.37
000000000011111100 // 252 251.91
111111111100100010 // -222 -222.08
000000000011000011 // 195 194.66
111111111101010110 // -170 -169.53
000000000010010011 // 147 146.52
111111111110000010 // -126 -125.56
000000000001101011 // 107 106.52
111111111110100111 // -89 -89.26
000000000001001010 // 74 73.67
111111111111000100 // -60 -59.68
000000000000101111 // 47 47.19
111111111111011100 // -36 -36.13
000000000000011010 // 26 26.35
111111111111101110 // -18 -17.82
000000000000001010 // 10 10.44
111111111111111100 // -4 -4.14
111111111111111111 // -1 -1.25
000000000000000110 // 6 5.77
111111111111110110 // -10 -9.59
000000000000001101 // 13 12.83
111111111111110000 // -16 -15.93
000000000000010011 // 19 19.3
111111111111101000 // -24 -24.03
000000000000100000 // 32 32.01
111111111111010000 // -48 -47.8
000000000001010000 // 80 80.21
111111111101101010 // -150 -149.71
111111111110011100 // -100 -100.32
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263
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8E.mif 100644
Wyświetl plik

@ -0,0 +1,263 @@
DEPTH = 256;
WIDTH = 18;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT
BEGIN
00 : 00001; -- 1 1.17
01 : 3FF9C; -- -100 -100.32
02 : 3FF6A; -- -150 -149.71
03 : 00050; -- 80 80.21
04 : 3FFD0; -- -48 -47.8
05 : 00020; -- 32 32.01
06 : 3FFE8; -- -24 -24.03
07 : 00013; -- 19 19.3
08 : 3FFF0; -- -16 -15.93
09 : 0000D; -- 13 12.83
0A : 3FFF6; -- -10 -9.59
0B : 00006; -- 6 5.77
0C : 3FFFF; -- -1 -1.25
0D : 3FFFC; -- -4 -4.14
0E : 0000A; -- 10 10.44
0F : 3FFEE; -- -18 -17.82
10 : 0001A; -- 26 26.35
11 : 3FFDC; -- -36 -36.13
12 : 0002F; -- 47 47.19
13 : 3FFC4; -- -60 -59.68
14 : 0004A; -- 74 73.67
15 : 3FFA7; -- -89 -89.26
16 : 0006B; -- 107 106.52
17 : 3FF82; -- -126 -125.56
18 : 00093; -- 147 146.52
19 : 3FF56; -- -170 -169.53
1A : 000C3; -- 195 194.66
1B : 3FF22; -- -222 -222.08
1C : 000FC; -- 252 251.91
1D : 3FEE4; -- -284 -284.37
1E : 00140; -- 320 319.58
1F : 3FE9A; -- -358 -357.72
20 : 0018F; -- 399 398.98
21 : 3FE44; -- -444 -443.58
22 : 001EC; -- 492 491.77
23 : 3FDE0; -- -544 -543.86
24 : 00258; -- 600 600.19
25 : 3FD6B; -- -661 -661.2
26 : 002D7; -- 727 727.32
27 : 3FCE1; -- -799 -799.08
28 : 0036D; -- 877 877.08
29 : 3FC3E; -- -962 -962.12
2A : 0041F; -- 1055 1055.14
2B : 3FB7B; -- -1157 -1157.33
2C : 004F6; -- 1270 1270.15
2D : 3FA8D; -- -1395 -1395.45
2E : 00600; -- 1536 1535.52
2F : 3F963; -- -1693 -1693.34
30 : 00751; -- 1873 1872.92
31 : 3F7E0; -- -2080 -2079.75
32 : 00911; -- 2321 2321.41
33 : 3F5D0; -- -2608 -2608.46
34 : 00B8C; -- 2956 2956.46
35 : 3F2C3; -- -3389 -3389.32
36 : 00F6A; -- 3946 3945.82
37 : 3EDAC; -- -4692 -4692.33
38 : 01679; -- 5753 5753.43
39 : 3E31E; -- -7394 -7393.55
3A : 02833; -- 10291 10291.22
3B : 3BE24; -- -16860 -16859.67
3C : 0B656; -- 46678 46678.12
3D : 0E922; -- 59682 59681.81
3E : 3B99A; -- -18022 -18022.23
3F : 0291A; -- 10522 10521.57
40 : 3E337; -- -7369 -7368.52
41 : 015F9; -- 5625 5624.58
42 : 3EE60; -- -4512 -4512.2
43 : 00E9A; -- 3738 3737.57
44 : 3F3A3; -- -3165 -3164.82
45 : 00AA3; -- 2723 2722.5
46 : 3F6BF; -- -2369 -2369.26
47 : 00820; -- 2080 2079.8
48 : 3F8D2; -- -1838 -1837.76
49 : 00660; -- 1632 1632.02
4A : 3FA51; -- -1455 -1454.65
4B : 00514; -- 1300 1299.93
4C : 3FB74; -- -1164 -1163.7
4D : 00413; -- 1043 1042.86
4E : 3FC59; -- -935 -935.01
4F : 00346; -- 838 838.22
50 : 3FD11; -- -751 -750.96
51 : 002A0; -- 672 671.99
52 : 3FDA8; -- -600 -600.31
53 : 00217; -- 535 535.1
54 : 3FE24; -- -476 -475.72
55 : 001A6; -- 422 421.61
56 : 3FE8C; -- -372 -372.28
57 : 00147; -- 327 327.27
58 : 3FEE2; -- -286 -286.21
59 : 000F9; -- 249 248.75
5A : 3FF29; -- -215 -214.65
5B : 000B8; -- 184 183.64
5C : 3FF64; -- -156 -155.52
5D : 00082; -- 130 130.09
5E : 3FF95; -- -107 -107.18
5F : 00057; -- 87 86.58
60 : 3FFBC; -- -68 -68.12
61 : 00034; -- 52 51.65
62 : 3FFDB; -- -37 -37.06
63 : 00018; -- 24 24.2
64 : 3FFF3; -- -13 -12.93
65 : 00003; -- 3 3.12
66 : 00005; -- 5 5.29
67 : 3FFF4; -- -12 -12.43
68 : 00012; -- 18 18.39
69 : 3FFE9; -- -23 -23.31
6A : 0001B; -- 27 27.25
6B : 3FFE2; -- -30 -30.3
6C : 00021; -- 33 32.56
6D : 3FFDE; -- -34 -34.22
6E : 00023; -- 35 35.32
6F : 3FFDC; -- -36 -36.05
70 : 00025; -- 37 36.59
71 : 3FFDB; -- -37 -37.37
72 : 00027; -- 39 38.81
73 : 3FFD6; -- -42 -41.94
74 : 00030; -- 48 48.33
75 : 3FFC3; -- -61 -61.32
76 : 00056; -- 86 85.67
77 : 3FF83; -- -125 -124.78
78 : 3FF86; -- -122 -121.96
79 : 3FFFE; -- -2 -1.94
7A : 00000;
7B : 00000;
7C : 00000;
7D : 00000;
7E : 00000;
7F : 00000;
80 : 00000;
81 : 00000;
82 : 00000;
83 : 00000;
84 : 00000;
85 : 00000;
86 : 00000;
87 : 00000;
88 : 00000;
89 : 00000;
8A : 00000;
8B : 00000;
8C : 00000;
8D : 00000;
8E : 00000;
8F : 00000;
90 : 00000;
91 : 00000;
92 : 00000;
93 : 00000;
94 : 00000;
95 : 00000;
96 : 00000;
97 : 00000;
98 : 00000;
99 : 00000;
9A : 00000;
9B : 00000;
9C : 00000;
9D : 00000;
9E : 00000;
9F : 00000;
A0 : 00000;
A1 : 00000;
A2 : 00000;
A3 : 00000;
A4 : 00000;
A5 : 00000;
A6 : 00000;
A7 : 00000;
A8 : 00000;
A9 : 00000;
AA : 00000;
AB : 00000;
AC : 00000;
AD : 00000;
AE : 00000;
AF : 00000;
B0 : 00000;
B1 : 00000;
B2 : 00000;
B3 : 00000;
B4 : 00000;
B5 : 00000;
B6 : 00000;
B7 : 00000;
B8 : 00000;
B9 : 00000;
BA : 00000;
BB : 00000;
BC : 00000;
BD : 00000;
BE : 00000;
BF : 00000;
C0 : 00000;
C1 : 00000;
C2 : 00000;
C3 : 00000;
C4 : 00000;
C5 : 00000;
C6 : 00000;
C7 : 00000;
C8 : 00000;
C9 : 00000;
CA : 00000;
CB : 00000;
CC : 00000;
CD : 00000;
CE : 00000;
CF : 00000;
D0 : 00000;
D1 : 00000;
D2 : 00000;
D3 : 00000;
D4 : 00000;
D5 : 00000;
D6 : 00000;
D7 : 00000;
D8 : 00000;
D9 : 00000;
DA : 00000;
DB : 00000;
DC : 00000;
DD : 00000;
DE : 00000;
DF : 00000;
E0 : 00000;
E1 : 00000;
E2 : 00000;
E3 : 00000;
E4 : 00000;
E5 : 00000;
E6 : 00000;
E7 : 00000;
E8 : 00000;
E9 : 00000;
EA : 00000;
EB : 00000;
EC : 00000;
ED : 00000;
EE : 00000;
EF : 00000;
F0 : 00000;
F1 : 00000;
F2 : 00000;
F3 : 00000;
F4 : 00000;
F5 : 00000;
F6 : 00000;
F7 : 00000;
F8 : 00000;
F9 : 00000;
FA : 00000;
FB : 00000;
FC : 00000;
FD : 00000;
FE : 00000;
FF : 00000;
END;

256
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8E.txt 100644
Wyświetl plik

@ -0,0 +1,256 @@
000000000000000001 // 1 1.17
111111111110011100 // -100 -100.32
111111111101101010 // -150 -149.71
000000000001010000 // 80 80.21
111111111111010000 // -48 -47.8
000000000000100000 // 32 32.01
111111111111101000 // -24 -24.03
000000000000010011 // 19 19.3
111111111111110000 // -16 -15.93
000000000000001101 // 13 12.83
111111111111110110 // -10 -9.59
000000000000000110 // 6 5.77
111111111111111111 // -1 -1.25
111111111111111100 // -4 -4.14
000000000000001010 // 10 10.44
111111111111101110 // -18 -17.82
000000000000011010 // 26 26.35
111111111111011100 // -36 -36.13
000000000000101111 // 47 47.19
111111111111000100 // -60 -59.68
000000000001001010 // 74 73.67
111111111110100111 // -89 -89.26
000000000001101011 // 107 106.52
111111111110000010 // -126 -125.56
000000000010010011 // 147 146.52
111111111101010110 // -170 -169.53
000000000011000011 // 195 194.66
111111111100100010 // -222 -222.08
000000000011111100 // 252 251.91
111111111011100100 // -284 -284.37
000000000101000000 // 320 319.58
111111111010011010 // -358 -357.72
000000000110001111 // 399 398.98
111111111001000100 // -444 -443.58
000000000111101100 // 492 491.77
111111110111100000 // -544 -543.86
000000001001011000 // 600 600.19
111111110101101011 // -661 -661.2
000000001011010111 // 727 727.32
111111110011100001 // -799 -799.08
000000001101101101 // 877 877.08
111111110000111110 // -962 -962.12
000000010000011111 // 1055 1055.14
111111101101111011 // -1157 -1157.33
000000010011110110 // 1270 1270.15
111111101010001101 // -1395 -1395.45
000000011000000000 // 1536 1535.52
111111100101100011 // -1693 -1693.34
000000011101010001 // 1873 1872.92
111111011111100000 // -2080 -2079.75
000000100100010001 // 2321 2321.41
111111010111010000 // -2608 -2608.46
000000101110001100 // 2956 2956.46
111111001011000011 // -3389 -3389.32
000000111101101010 // 3946 3945.82
111110110110101100 // -4692 -4692.33
000001011001111001 // 5753 5753.43
111110001100011110 // -7394 -7393.55
000010100000110011 // 10291 10291.22
111011111000100100 // -16860 -16859.67
001011011001010110 // 46678 46678.12
001110100100100010 // 59682 59681.81
111011100110011010 // -18022 -18022.23
000010100100011010 // 10522 10521.57
111110001100110111 // -7369 -7368.52
000001010111111001 // 5625 5624.58
111110111001100000 // -4512 -4512.2
000000111010011010 // 3738 3737.57
111111001110100011 // -3165 -3164.82
000000101010100011 // 2723 2722.5
111111011010111111 // -2369 -2369.26
000000100000100000 // 2080 2079.8
111111100011010010 // -1838 -1837.76
000000011001100000 // 1632 1632.02
111111101001010001 // -1455 -1454.65
000000010100010100 // 1300 1299.93
111111101101110100 // -1164 -1163.7
000000010000010011 // 1043 1042.86
111111110001011001 // -935 -935.01
000000001101000110 // 838 838.22
111111110100010001 // -751 -750.96
000000001010100000 // 672 671.99
111111110110101000 // -600 -600.31
000000001000010111 // 535 535.1
111111111000100100 // -476 -475.72
000000000110100110 // 422 421.61
111111111010001100 // -372 -372.28
000000000101000111 // 327 327.27
111111111011100010 // -286 -286.21
000000000011111001 // 249 248.75
111111111100101001 // -215 -214.65
000000000010111000 // 184 183.64
111111111101100100 // -156 -155.52
000000000010000010 // 130 130.09
111111111110010101 // -107 -107.18
000000000001010111 // 87 86.58
111111111110111100 // -68 -68.12
000000000000110100 // 52 51.65
111111111111011011 // -37 -37.06
000000000000011000 // 24 24.2
111111111111110011 // -13 -12.93
000000000000000011 // 3 3.12
000000000000000101 // 5 5.29
111111111111110100 // -12 -12.43
000000000000010010 // 18 18.39
111111111111101001 // -23 -23.31
000000000000011011 // 27 27.25
111111111111100010 // -30 -30.3
000000000000100001 // 33 32.56
111111111111011110 // -34 -34.22
000000000000100011 // 35 35.32
111111111111011100 // -36 -36.05
000000000000100101 // 37 36.59
111111111111011011 // -37 -37.37
000000000000100111 // 39 38.81
111111111111010110 // -42 -41.94
000000000000110000 // 48 48.33
111111111111000011 // -61 -61.32
000000000001010110 // 86 85.67
111111111110000011 // -125 -124.78
111111111110000110 // -122 -121.96
111111111111111110 // -2 -1.94
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263
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8F.mif 100644
Wyświetl plik

@ -0,0 +1,263 @@
DEPTH = 256;
WIDTH = 18;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT
BEGIN
00 : 00003; -- 3 2.53
01 : 3FFB1; -- -79 -78.87
02 : 3FF59; -- -167 -167.26
03 : 00041; -- 65 65.16
04 : 3FFE4; -- -28 -27.52
05 : 0000B; -- 11 10.98
06 : 3FFFD; -- -3 -2.68
07 : 3FFFD; -- -3 -2.82
08 : 00007; -- 7 7.47
09 : 3FFF4; -- -12 -12.31
0A : 00012; -- 18 17.68
0B : 3FFE8; -- -24 -23.92
0C : 0001F; -- 31 31.11
0D : 3FFD9; -- -39 -39.35
0E : 00031; -- 49 48.67
0F : 3FFC5; -- -59 -59.2
10 : 00047; -- 71 70.98
11 : 3FFAC; -- -84 -84.09
12 : 00063; -- 99 98.53
13 : 3FF8E; -- -114 -114.43
14 : 00084; -- 132 131.84
15 : 3FF69; -- -151 -150.82
16 : 000AB; -- 171 171.42
17 : 3FF3E; -- -194 -193.74
18 : 000DA; -- 218 217.86
19 : 3FF0C; -- -244 -243.89
1A : 00110; -- 272 271.89
1B : 3FED2; -- -302 -301.95
1C : 0014E; -- 334 334.19
1D : 3FE8F; -- -369 -368.76
1E : 00196; -- 406 405.74
1F : 3FE43; -- -445 -445.25
20 : 001E7; -- 487 487.43
21 : 3FDEC; -- -532 -532.46
22 : 00245; -- 581 580.51
23 : 3FD88; -- -632 -631.83
24 : 002AF; -- 687 686.69
25 : 3FD17; -- -745 -745.42
26 : 00328; -- 808 808.35
27 : 3FC94; -- -876 -875.9
28 : 003B5; -- 949 948.53
29 : 3FBFD; -- -1027 -1026.88
2A : 00458; -- 1112 1111.72
2B : 3FB4C; -- -1204 -1204.01
2C : 00519; -- 1305 1304.93
2D : 3FA78; -- -1416 -1415.97
2E : 00603; -- 1539 1538.98
2F : 3F974; -- -1676 -1676.38
30 : 00727; -- 1831 1831.44
31 : 3F827; -- -2009 -2008.64
32 : 008A6; -- 2214 2214.12
33 : 3F668; -- -2456 -2456.39
34 : 00ABC; -- 2748 2747.95
35 : 3F3DC; -- -3108 -3108.0
36 : 00DEF; -- 3567 3567.43
37 : 3EFAD; -- -4179 -4178.55
38 : 013AE; -- 5038 5038.36
39 : 3E733; -- -6349 -6349.16
3A : 021A7; -- 8615 8615.49
3B : 3CB20; -- -13536 -13535.56
3C : 07FB5; -- 32693 32692.86
3D : 113C2; -- 70594 70593.52
3E : 3BFBA; -- -16454 -16453.82
3F : 0239E; -- 9118 9117.56
40 : 3E7CB; -- -6197 -6197.2
41 : 0120E; -- 4622 4621.76
42 : 3F1D0; -- -3632 -3631.86
43 : 00B86; -- 2950 2949.91
44 : 3F66E; -- -2450 -2450.05
45 : 00813; -- 2067 2066.95
46 : 3F91D; -- -1763 -1763.2
47 : 005EC; -- 1516 1516.11
48 : 3FAE1; -- -1311 -1311.07
49 : 00472; -- 1138 1138.16
4A : 3FC22; -- -990 -990.32
4B : 0035F; -- 863 862.51
4C : 3FD11; -- -751 -751.06
4D : 0028D; -- 653 653.24
4E : 3FDC9; -- -567 -566.93
4F : 001EA; -- 490 490.39
50 : 3FE5A; -- -422 -422.28
51 : 00169; -- 361 361.49
52 : 3FECD; -- -307 -307.13
53 : 00102; -- 258 258.48
54 : 3FF29; -- -215 -214.95
55 : 000B0; -- 176 176.05
56 : 3FF73; -- -141 -141.3
57 : 0006E; -- 110 110.29
58 : 3FFAD; -- -83 -82.67
59 : 0003A; -- 58 58.13
5A : 3FFDC; -- -36 -36.44
5B : 00011; -- 17 17.35
5C : 3FFFF; -- -1 -0.67
5D : 3FFF2; -- -14 -13.79
5E : 0001A; -- 26 26.2
5F : 3FFDB; -- -37 -36.78
60 : 0002E; -- 46 45.67
61 : 3FFCB; -- -53 -53.03
62 : 0003B; -- 59 58.95
63 : 3FFC0; -- -64 -63.59
64 : 00043; -- 67 67.07
65 : 3FFBA; -- -70 -69.52
66 : 00047; -- 71 71.0
67 : 3FFB8; -- -72 -71.62
68 : 00047; -- 71 71.49
69 : 3FFB9; -- -71 -70.72
6A : 00045; -- 69 69.37
6B : 3FFBC; -- -68 -67.55
6C : 00041; -- 65 65.34
6D : 3FFC1; -- -63 -62.92
6E : 0003C; -- 60 60.34
6F : 3FFC6; -- -58 -57.78
70 : 00037; -- 55 55.42
71 : 3FFCA; -- -54 -53.67
72 : 00035; -- 53 52.87
73 : 3FFCA; -- -54 -53.88
74 : 0003A; -- 58 57.79
75 : 3FFBD; -- -67 -66.62
76 : 00051; -- 81 81.41
77 : 3FFA2; -- -94 -93.93
78 : 3FF72; -- -142 -142.25
79 : 3FFF9; -- -7 -7.35
7A : 00000;
7B : 00000;
7C : 00000;
7D : 00000;
7E : 00000;
7F : 00000;
80 : 00000;
81 : 00000;
82 : 00000;
83 : 00000;
84 : 00000;
85 : 00000;
86 : 00000;
87 : 00000;
88 : 00000;
89 : 00000;
8A : 00000;
8B : 00000;
8C : 00000;
8D : 00000;
8E : 00000;
8F : 00000;
90 : 00000;
91 : 00000;
92 : 00000;
93 : 00000;
94 : 00000;
95 : 00000;
96 : 00000;
97 : 00000;
98 : 00000;
99 : 00000;
9A : 00000;
9B : 00000;
9C : 00000;
9D : 00000;
9E : 00000;
9F : 00000;
A0 : 00000;
A1 : 00000;
A2 : 00000;
A3 : 00000;
A4 : 00000;
A5 : 00000;
A6 : 00000;
A7 : 00000;
A8 : 00000;
A9 : 00000;
AA : 00000;
AB : 00000;
AC : 00000;
AD : 00000;
AE : 00000;
AF : 00000;
B0 : 00000;
B1 : 00000;
B2 : 00000;
B3 : 00000;
B4 : 00000;
B5 : 00000;
B6 : 00000;
B7 : 00000;
B8 : 00000;
B9 : 00000;
BA : 00000;
BB : 00000;
BC : 00000;
BD : 00000;
BE : 00000;
BF : 00000;
C0 : 00000;
C1 : 00000;
C2 : 00000;
C3 : 00000;
C4 : 00000;
C5 : 00000;
C6 : 00000;
C7 : 00000;
C8 : 00000;
C9 : 00000;
CA : 00000;
CB : 00000;
CC : 00000;
CD : 00000;
CE : 00000;
CF : 00000;
D0 : 00000;
D1 : 00000;
D2 : 00000;
D3 : 00000;
D4 : 00000;
D5 : 00000;
D6 : 00000;
D7 : 00000;
D8 : 00000;
D9 : 00000;
DA : 00000;
DB : 00000;
DC : 00000;
DD : 00000;
DE : 00000;
DF : 00000;
E0 : 00000;
E1 : 00000;
E2 : 00000;
E3 : 00000;
E4 : 00000;
E5 : 00000;
E6 : 00000;
E7 : 00000;
E8 : 00000;
E9 : 00000;
EA : 00000;
EB : 00000;
EC : 00000;
ED : 00000;
EE : 00000;
EF : 00000;
F0 : 00000;
F1 : 00000;
F2 : 00000;
F3 : 00000;
F4 : 00000;
F5 : 00000;
F6 : 00000;
F7 : 00000;
F8 : 00000;
F9 : 00000;
FA : 00000;
FB : 00000;
FC : 00000;
FD : 00000;
FE : 00000;
FF : 00000;
END;

256
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8F.txt 100644
Wyświetl plik

@ -0,0 +1,256 @@
000000000000000011 // 3 2.53
111111111110110001 // -79 -78.87
111111111101011001 // -167 -167.26
000000000001000001 // 65 65.16
111111111111100100 // -28 -27.52
000000000000001011 // 11 10.98
111111111111111101 // -3 -2.68
111111111111111101 // -3 -2.82
000000000000000111 // 7 7.47
111111111111110100 // -12 -12.31
000000000000010010 // 18 17.68
111111111111101000 // -24 -23.92
000000000000011111 // 31 31.11
111111111111011001 // -39 -39.35
000000000000110001 // 49 48.67
111111111111000101 // -59 -59.2
000000000001000111 // 71 70.98
111111111110101100 // -84 -84.09
000000000001100011 // 99 98.53
111111111110001110 // -114 -114.43
000000000010000100 // 132 131.84
111111111101101001 // -151 -150.82
000000000010101011 // 171 171.42
111111111100111110 // -194 -193.74
000000000011011010 // 218 217.86
111111111100001100 // -244 -243.89
000000000100010000 // 272 271.89
111111111011010010 // -302 -301.95
000000000101001110 // 334 334.19
111111111010001111 // -369 -368.76
000000000110010110 // 406 405.74
111111111001000011 // -445 -445.25
000000000111100111 // 487 487.43
111111110111101100 // -532 -532.46
000000001001000101 // 581 580.51
111111110110001000 // -632 -631.83
000000001010101111 // 687 686.69
111111110100010111 // -745 -745.42
000000001100101000 // 808 808.35
111111110010010100 // -876 -875.9
000000001110110101 // 949 948.53
111111101111111101 // -1027 -1026.88
000000010001011000 // 1112 1111.72
111111101101001100 // -1204 -1204.01
000000010100011001 // 1305 1304.93
111111101001111000 // -1416 -1415.97
000000011000000011 // 1539 1538.98
111111100101110100 // -1676 -1676.38
000000011100100111 // 1831 1831.44
111111100000100111 // -2009 -2008.64
000000100010100110 // 2214 2214.12
111111011001101000 // -2456 -2456.39
000000101010111100 // 2748 2747.95
111111001111011100 // -3108 -3108.0
000000110111101111 // 3567 3567.43
111110111110101101 // -4179 -4178.55
000001001110101110 // 5038 5038.36
111110011100110011 // -6349 -6349.16
000010000110100111 // 8615 8615.49
111100101100100000 // -13536 -13535.56
000111111110110101 // 32693 32692.86
010001001111000010 // 70594 70593.52
111011111110111010 // -16454 -16453.82
000010001110011110 // 9118 9117.56
111110011111001011 // -6197 -6197.2
000001001000001110 // 4622 4621.76
111111000111010000 // -3632 -3631.86
000000101110000110 // 2950 2949.91
111111011001101110 // -2450 -2450.05
000000100000010011 // 2067 2066.95
111111100100011101 // -1763 -1763.2
000000010111101100 // 1516 1516.11
111111101011100001 // -1311 -1311.07
000000010001110010 // 1138 1138.16
111111110000100010 // -990 -990.32
000000001101011111 // 863 862.51
111111110100010001 // -751 -751.06
000000001010001101 // 653 653.24
111111110111001001 // -567 -566.93
000000000111101010 // 490 490.39
111111111001011010 // -422 -422.28
000000000101101001 // 361 361.49
111111111011001101 // -307 -307.13
000000000100000010 // 258 258.48
111111111100101001 // -215 -214.95
000000000010110000 // 176 176.05
111111111101110011 // -141 -141.3
000000000001101110 // 110 110.29
111111111110101101 // -83 -82.67
000000000000111010 // 58 58.13
111111111111011100 // -36 -36.44
000000000000010001 // 17 17.35
111111111111111111 // -1 -0.67
111111111111110010 // -14 -13.79
000000000000011010 // 26 26.2
111111111111011011 // -37 -36.78
000000000000101110 // 46 45.67
111111111111001011 // -53 -53.03
000000000000111011 // 59 58.95
111111111111000000 // -64 -63.59
000000000001000011 // 67 67.07
111111111110111010 // -70 -69.52
000000000001000111 // 71 71.0
111111111110111000 // -72 -71.62
000000000001000111 // 71 71.49
111111111110111001 // -71 -70.72
000000000001000101 // 69 69.37
111111111110111100 // -68 -67.55
000000000001000001 // 65 65.34
111111111111000001 // -63 -62.92
000000000000111100 // 60 60.34
111111111111000110 // -58 -57.78
000000000000110111 // 55 55.42
111111111111001010 // -54 -53.67
000000000000110101 // 53 52.87
111111111111001010 // -54 -53.88
000000000000111010 // 58 57.79
111111111110111101 // -67 -66.62
000000000001010001 // 81 81.41
111111111110100010 // -94 -93.93
111111111101110010 // -142 -142.25
111111111111111001 // -7 -7.35
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263
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8G.mif 100644
Wyświetl plik

@ -0,0 +1,263 @@
DEPTH = 256;
WIDTH = 18;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT
BEGIN
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01 : 3FFC5; -- -59 -58.91
02 : 3FF4F; -- -177 -176.7
03 : 0002A; -- 42 41.57
04 : 3FFFD; -- -3 -2.81
05 : 3FFF4; -- -12 -12.0
06 : 00013; -- 19 19.15
07 : 3FFE8; -- -24 -24.38
08 : 0001D; -- 29 29.46
09 : 3FFDD; -- -35 -35.2
0A : 0002A; -- 42 41.79
0B : 3FFCF; -- -49 -49.45
0C : 0003A; -- 58 58.17
0D : 3FFBC; -- -68 -67.99
0E : 0004F; -- 79 78.88
0F : 3FFA5; -- -91 -90.96
10 : 00068; -- 104 104.2
11 : 3FF89; -- -119 -118.65
12 : 00086; -- 134 134.29
13 : 3FF69; -- -151 -151.2
14 : 000A9; -- 169 169.4
15 : 3FF43; -- -189 -188.93
16 : 000D2; -- 210 209.77
17 : 3FF18; -- -232 -232.01
18 : 00100; -- 256 255.7
19 : 3FEE7; -- -281 -280.87
1A : 00134; -- 308 307.54
1B : 3FEB0; -- -336 -335.77
1C : 0016E; -- 366 365.61
1D : 3FE73; -- -397 -397.15
1E : 001AE; -- 430 430.4
1F : 3FE2F; -- -465 -465.43
20 : 001F6; -- 502 502.28
21 : 3FDE3; -- -541 -541.06
22 : 00246; -- 582 581.86
23 : 3FD8F; -- -625 -624.82
24 : 0029E; -- 670 670.1
25 : 3FD32; -- -718 -717.9
26 : 00300; -- 768 768.38
27 : 3FCCA; -- -822 -821.78
28 : 0036E; -- 878 878.37
29 : 3FC55; -- -939 -938.55
2A : 003EB; -- 1003 1002.81
2B : 3FBD0; -- -1072 -1071.73
2C : 0047A; -- 1146 1146.07
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2E : 00523; -- 1315 1314.94
2F : 3FA7C; -- -1412 -1412.14
30 : 005F0; -- 1520 1520.49
31 : 3F995; -- -1643 -1642.85
32 : 006F7; -- 1783 1783.15
33 : 3F865; -- -1947 -1946.74
34 : 0085E; -- 2142 2141.55
35 : 3F6B4; -- -2380 -2379.71
36 : 00A79; -- 2681 2680.7
37 : 3F3FB; -- -3077 -3076.99
38 : 00E2C; -- 3628 3628.21
39 : 3EE97; -- -4457 -4456.63
3A : 016E3; -- 5859 5859.41
3B : 3DDAD; -- -8787 -8787.3
3C : 049BC; -- 18876 18875.93
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3E : 3D1C6; -- -11834 -11833.59
3F : 017DE; -- 6110 6109.58
40 : 3F07F; -- -3969 -3968.7
41 : 00B1D; -- 2845 2845.05
42 : 3F799; -- -2151 -2150.57
43 : 0068E; -- 1678 1678.01
44 : 3FAC9; -- -1335 -1335.25
45 : 00433; -- 1075 1075.14
46 : 3FC99; -- -871 -870.93
47 : 002C3; -- 707 706.59
48 : 3FDC4; -- -572 -571.84
49 : 001CC; -- 460 459.69
4A : 3FE93; -- -365 -365.16
4B : 0011D; -- 285 284.72
4C : 3FF28; -- -216 -215.84
4D : 0009D; -- 157 156.63
4E : 3FF96; -- -106 -105.57
4F : 0003D; -- 61 61.44
50 : 3FFE9; -- -23 -23.27
51 : 3FFF6; -- -10 -9.71
52 : 00026; -- 38 38.14
53 : 3FFC1; -- -63 -62.53
54 : 00053; -- 83 83.3
55 : 3FF9B; -- -101 -100.83
56 : 00073; -- 115 115.47
57 : 3FF80; -- -128 -127.55
58 : 00089; -- 137 137.32
59 : 3FF6F; -- -145 -145.01
5A : 00097; -- 151 150.81
5B : 3FF65; -- -155 -154.9
5C : 0009D; -- 157 157.43
5D : 3FF61; -- -159 -158.56
5E : 0009E; -- 158 158.43
5F : 3FF63; -- -157 -157.22
60 : 0009B; -- 155 155.04
61 : 3FF68; -- -152 -152.02
62 : 00094; -- 148 148.23
63 : 3FF70; -- -144 -143.8
64 : 0008B; -- 139 138.84
65 : 3FF7B; -- -133 -133.43
66 : 00080; -- 128 127.63
67 : 3FF86; -- -122 -121.52
68 : 00073; -- 115 115.18
69 : 3FF93; -- -109 -108.74
6A : 00066; -- 102 102.2
6B : 3FFA0; -- -96 -95.66
6C : 00059; -- 89 89.21
6D : 3FFAD; -- -83 -82.98
6E : 0004D; -- 77 77.01
6F : 3FFB9; -- -71 -71.45
70 : 00042; -- 66 66.45
71 : 3FFC2; -- -62 -62.36
72 : 0003B; -- 59 59.39
73 : 3FFC6; -- -58 -58.15
74 : 0003B; -- 59 59.19
75 : 3FFC1; -- -63 -63.24
76 : 00044; -- 68 68.31
77 : 3FFC5; -- -59 -59.24
78 : 3FF61; -- -159 -159.46
79 : 3FFF0; -- -16 -15.55
7A : 00000;
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FD : 00000;
FE : 00000;
FF : 00000;
END;

256
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8G.txt 100644
Wyświetl plik

@ -0,0 +1,256 @@
000000000000000011 // 3 2.7
111111111111000101 // -59 -58.91
111111111101001111 // -177 -176.7
000000000000101010 // 42 41.57
111111111111111101 // -3 -2.81
111111111111110100 // -12 -12.0
000000000000010011 // 19 19.15
111111111111101000 // -24 -24.38
000000000000011101 // 29 29.46
111111111111011101 // -35 -35.2
000000000000101010 // 42 41.79
111111111111001111 // -49 -49.45
000000000000111010 // 58 58.17
111111111110111100 // -68 -67.99
000000000001001111 // 79 78.88
111111111110100101 // -91 -90.96
000000000001101000 // 104 104.2
111111111110001001 // -119 -118.65
000000000010000110 // 134 134.29
111111111101101001 // -151 -151.2
000000000010101001 // 169 169.4
111111111101000011 // -189 -188.93
000000000011010010 // 210 209.77
111111111100011000 // -232 -232.01
000000000100000000 // 256 255.7
111111111011100111 // -281 -280.87
000000000100110100 // 308 307.54
111111111010110000 // -336 -335.77
000000000101101110 // 366 365.61
111111111001110011 // -397 -397.15
000000000110101110 // 430 430.4
111111111000101111 // -465 -465.43
000000000111110110 // 502 502.28
111111110111100011 // -541 -541.06
000000001001000110 // 582 581.86
111111110110001111 // -625 -624.82
000000001010011110 // 670 670.1
111111110100110010 // -718 -717.9
000000001100000000 // 768 768.38
111111110011001010 // -822 -821.78
000000001101101110 // 878 878.37
111111110001010101 // -939 -938.55
000000001111101011 // 1003 1002.81
111111101111010000 // -1072 -1071.73
000000010001111010 // 1146 1146.07
111111101100110101 // -1227 -1226.76
000000010100100011 // 1315 1314.94
111111101001111100 // -1412 -1412.14
000000010111110000 // 1520 1520.49
111111100110010101 // -1643 -1642.85
000000011011110111 // 1783 1783.15
111111100001100101 // -1947 -1946.74
000000100001011110 // 2142 2141.55
111111011010110100 // -2380 -2379.71
000000101001111001 // 2681 2680.7
111111001111111011 // -3077 -3076.99
000000111000101100 // 3628 3628.21
111110111010010111 // -4457 -4456.63
000001011011100011 // 5859 5859.41
111101110110101101 // -8787 -8787.3
000100100110111100 // 18876 18875.93
010011001001111010 // 78458 78457.77
111101000111000110 // -11834 -11833.59
000001011111011110 // 6110 6109.58
111111000001111111 // -3969 -3968.7
000000101100011101 // 2845 2845.05
111111011110011001 // -2151 -2150.57
000000011010001110 // 1678 1678.01
111111101011001001 // -1335 -1335.25
000000010000110011 // 1075 1075.14
111111110010011001 // -871 -870.93
000000001011000011 // 707 706.59
111111110111000100 // -572 -571.84
000000000111001100 // 460 459.69
111111111010010011 // -365 -365.16
000000000100011101 // 285 284.72
111111111100101000 // -216 -215.84
000000000010011101 // 157 156.63
111111111110010110 // -106 -105.57
000000000000111101 // 61 61.44
111111111111101001 // -23 -23.27
111111111111110110 // -10 -9.71
000000000000100110 // 38 38.14
111111111111000001 // -63 -62.53
000000000001010011 // 83 83.3
111111111110011011 // -101 -100.83
000000000001110011 // 115 115.47
111111111110000000 // -128 -127.55
000000000010001001 // 137 137.32
111111111101101111 // -145 -145.01
000000000010010111 // 151 150.81
111111111101100101 // -155 -154.9
000000000010011101 // 157 157.43
111111111101100001 // -159 -158.56
000000000010011110 // 158 158.43
111111111101100011 // -157 -157.22
000000000010011011 // 155 155.04
111111111101101000 // -152 -152.02
000000000010010100 // 148 148.23
111111111101110000 // -144 -143.8
000000000010001011 // 139 138.84
111111111101111011 // -133 -133.43
000000000010000000 // 128 127.63
111111111110000110 // -122 -121.52
000000000001110011 // 115 115.18
111111111110010011 // -109 -108.74
000000000001100110 // 102 102.2
111111111110100000 // -96 -95.66
000000000001011001 // 89 89.21
111111111110101101 // -83 -82.98
000000000001001101 // 77 77.01
111111111110111001 // -71 -71.45
000000000001000010 // 66 66.45
111111111111000010 // -62 -62.36
000000000000111011 // 59 59.39
111111111111000110 // -58 -58.15
000000000000111011 // 59 59.19
111111111111000001 // -63 -63.24
000000000001000100 // 68 68.31
111111111111000101 // -59 -59.24
111111111101100001 // -159 -159.46
111111111111110000 // -16 -15.55
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263
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8H.mif 100644
Wyświetl plik

@ -0,0 +1,263 @@
DEPTH = 256;
WIDTH = 18;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT
BEGIN
00 : 00004; -- 4 4.08
01 : 3FFD7; -- -41 -41.39
02 : 3FF4E; -- -178 -178.04
03 : 0000B; -- 11 11.29
04 : 00017; -- 23 23.45
05 : 3FFDE; -- -34 -33.9
06 : 00026; -- 38 38.4
07 : 3FFD6; -- -42 -42.32
08 : 0002F; -- 47 46.89
09 : 3FFCB; -- -53 -52.57
0A : 0003B; -- 59 59.32
0B : 3FFBD; -- -67 -67.22
0C : 0004C; -- 76 76.14
0D : 3FFAA; -- -86 -86.06
0E : 00061; -- 97 96.9
0F : 3FF93; -- -109 -108.71
10 : 00079; -- 121 121.45
11 : 3FF79; -- -135 -135.09
12 : 00096; -- 150 149.6
13 : 3FF5B; -- -165 -165.03
14 : 000B5; -- 181 181.34
15 : 3FF39; -- -199 -198.52
16 : 000D9; -- 217 216.54
17 : 3FF15; -- -235 -235.44
18 : 000FF; -- 255 255.19
19 : 3FEEC; -- -276 -275.81
1A : 00129; -- 297 297.25
1B : 3FEC0; -- -320 -319.51
1C : 00157; -- 343 342.59
1D : 3FE92; -- -366 -366.49
1E : 00187; -- 391 391.17
1F : 3FE5F; -- -417 -416.6
20 : 001BB; -- 443 442.76
21 : 3FE2A; -- -470 -469.66
22 : 001F1; -- 497 497.3
23 : 3FDF2; -- -526 -525.69
24 : 0022B; -- 555 554.86
25 : 3FDB7; -- -585 -584.84
26 : 00268; -- 616 615.63
27 : 3FD79; -- -647 -647.25
28 : 002A8; -- 680 679.73
29 : 3FD37; -- -713 -713.21
2A : 002EC; -- 748 747.8
2B : 3FCF0; -- -784 -783.69
2C : 00335; -- 821 821.08
2D : 3FCA4; -- -860 -860.24
2E : 00385; -- 901 901.49
2F : 3FC4F; -- -945 -945.3
30 : 003E0; -- 992 992.38
31 : 3FBEC; -- -1044 -1043.73
32 : 0044D; -- 1101 1100.62
33 : 3FB73; -- -1165 -1164.75
34 : 004D7; -- 1239 1238.71
35 : 3FAD1; -- -1327 -1326.55
36 : 0059B; -- 1435 1434.79
37 : 3F9DA; -- -1574 -1573.96
38 : 006E3; -- 1763 1763.3
39 : 3F806; -- -2042 -2041.67
3A : 009C6; -- 2502 2501.72
3B : 3F29F; -- -3425 -3425.2
3C : 0189C; -- 6300 6299.88
3D : 1428F; -- 82575 82574.73
3E : 3EFCF; -- -4145 -4145.21
3F : 006E5; -- 1765 1764.83
40 : 3FC57; -- -937 -937.39
41 : 00205; -- 517 517.3
42 : 3FEF9; -- -263 -263.41
43 : 0005E; -- 94 94.35
44 : 00019; -- 25 25.43
45 : 3FF8E; -- -114 -113.89
46 : 000B5; -- 181 181.19
47 : 3FF17; -- -233 -233.21
48 : 00112; -- 274 273.75
49 : 3FECF; -- -305 -305.44
4A : 0014A; -- 330 330.2
4B : 3FEA3; -- -349 -349.37
4C : 0016C; -- 364 363.85
4D : 3FE8A; -- -374 -374.34
4E : 0017D; -- 381 381.42
4F : 3FE7E; -- -386 -385.61
50 : 00183; -- 387 387.31
51 : 3FE7D; -- -387 -386.85
52 : 00180; -- 384 384.48
53 : 3FE84; -- -380 -380.43
54 : 00177; -- 375 374.85
55 : 3FE90; -- -368 -367.93
56 : 00168; -- 360 359.87
57 : 3FEA1; -- -351 -350.84
58 : 00155; -- 341 340.96
59 : 3FEB6; -- -330 -330.35
5A : 0013F; -- 319 319.1
5B : 3FECD; -- -307 -307.32
5C : 00127; -- 295 295.08
5D : 3FEE6; -- -282 -282.48
5E : 0010E; -- 270 269.6
5F : 3FEFF; -- -257 -256.58
60 : 000F3; -- 243 243.48
61 : 3FF1A; -- -230 -230.35
62 : 000D9; -- 217 217.25
63 : 3FF34; -- -204 -204.26
64 : 000BF; -- 191 191.44
65 : 3FF4D; -- -179 -178.84
66 : 000A6; -- 166 166.48
67 : 3FF66; -- -154 -154.43
68 : 0008F; -- 143 142.73
69 : 3FF7D; -- -131 -131.45
6A : 00079; -- 121 120.59
6B : 3FF92; -- -110 -110.22
6C : 00064; -- 100 100.39
6D : 3FFA5; -- -91 -91.2
6E : 00053; -- 83 82.65
6F : 3FFB5; -- -75 -74.85
70 : 00044; -- 68 67.89
71 : 3FFC2; -- -62 -62.03
72 : 00039; -- 57 57.33
73 : 3FFCA; -- -54 -54.12
74 : 00034; -- 52 52.4
75 : 3FFCC; -- -52 -51.78
76 : 00030; -- 48 48.15
77 : 3FFE9; -- -23 -23.23
78 : 3FF54; -- -172 -171.9
79 : 3FFE5; -- -27 -26.86
7A : 00000;
7B : 00000;
7C : 00000;
7D : 00000;
7E : 00000;
7F : 00000;
80 : 00000;
81 : 00000;
82 : 00000;
83 : 00000;
84 : 00000;
85 : 00000;
86 : 00000;
87 : 00000;
88 : 00000;
89 : 00000;
8A : 00000;
8B : 00000;
8C : 00000;
8D : 00000;
8E : 00000;
8F : 00000;
90 : 00000;
91 : 00000;
92 : 00000;
93 : 00000;
94 : 00000;
95 : 00000;
96 : 00000;
97 : 00000;
98 : 00000;
99 : 00000;
9A : 00000;
9B : 00000;
9C : 00000;
9D : 00000;
9E : 00000;
9F : 00000;
A0 : 00000;
A1 : 00000;
A2 : 00000;
A3 : 00000;
A4 : 00000;
A5 : 00000;
A6 : 00000;
A7 : 00000;
A8 : 00000;
A9 : 00000;
AA : 00000;
AB : 00000;
AC : 00000;
AD : 00000;
AE : 00000;
AF : 00000;
B0 : 00000;
B1 : 00000;
B2 : 00000;
B3 : 00000;
B4 : 00000;
B5 : 00000;
B6 : 00000;
B7 : 00000;
B8 : 00000;
B9 : 00000;
BA : 00000;
BB : 00000;
BC : 00000;
BD : 00000;
BE : 00000;
BF : 00000;
C0 : 00000;
C1 : 00000;
C2 : 00000;
C3 : 00000;
C4 : 00000;
C5 : 00000;
C6 : 00000;
C7 : 00000;
C8 : 00000;
C9 : 00000;
CA : 00000;
CB : 00000;
CC : 00000;
CD : 00000;
CE : 00000;
CF : 00000;
D0 : 00000;
D1 : 00000;
D2 : 00000;
D3 : 00000;
D4 : 00000;
D5 : 00000;
D6 : 00000;
D7 : 00000;
D8 : 00000;
D9 : 00000;
DA : 00000;
DB : 00000;
DC : 00000;
DD : 00000;
DE : 00000;
DF : 00000;
E0 : 00000;
E1 : 00000;
E2 : 00000;
E3 : 00000;
E4 : 00000;
E5 : 00000;
E6 : 00000;
E7 : 00000;
E8 : 00000;
E9 : 00000;
EA : 00000;
EB : 00000;
EC : 00000;
ED : 00000;
EE : 00000;
EF : 00000;
F0 : 00000;
F1 : 00000;
F2 : 00000;
F3 : 00000;
F4 : 00000;
F5 : 00000;
F6 : 00000;
F7 : 00000;
F8 : 00000;
F9 : 00000;
FA : 00000;
FB : 00000;
FC : 00000;
FD : 00000;
FE : 00000;
FF : 00000;
END;

256
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/coefL8H.txt 100644
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@ -0,0 +1,256 @@
000000000000000100 // 4 4.08
111111111111010111 // -41 -41.39
111111111101001110 // -178 -178.04
000000000000001011 // 11 11.29
000000000000010111 // 23 23.45
111111111111011110 // -34 -33.9
000000000000100110 // 38 38.4
111111111111010110 // -42 -42.32
000000000000101111 // 47 46.89
111111111111001011 // -53 -52.57
000000000000111011 // 59 59.32
111111111110111101 // -67 -67.22
000000000001001100 // 76 76.14
111111111110101010 // -86 -86.06
000000000001100001 // 97 96.9
111111111110010011 // -109 -108.71
000000000001111001 // 121 121.45
111111111101111001 // -135 -135.09
000000000010010110 // 150 149.6
111111111101011011 // -165 -165.03
000000000010110101 // 181 181.34
111111111100111001 // -199 -198.52
000000000011011001 // 217 216.54
111111111100010101 // -235 -235.44
000000000011111111 // 255 255.19
111111111011101100 // -276 -275.81
000000000100101001 // 297 297.25
111111111011000000 // -320 -319.51
000000000101010111 // 343 342.59
111111111010010010 // -366 -366.49
000000000110000111 // 391 391.17
111111111001011111 // -417 -416.6
000000000110111011 // 443 442.76
111111111000101010 // -470 -469.66
000000000111110001 // 497 497.3
111111110111110010 // -526 -525.69
000000001000101011 // 555 554.86
111111110110110111 // -585 -584.84
000000001001101000 // 616 615.63
111111110101111001 // -647 -647.25
000000001010101000 // 680 679.73
111111110100110111 // -713 -713.21
000000001011101100 // 748 747.8
111111110011110000 // -784 -783.69
000000001100110101 // 821 821.08
111111110010100100 // -860 -860.24
000000001110000101 // 901 901.49
111111110001001111 // -945 -945.3
000000001111100000 // 992 992.38
111111101111101100 // -1044 -1043.73
000000010001001101 // 1101 1100.62
111111101101110011 // -1165 -1164.75
000000010011010111 // 1239 1238.71
111111101011010001 // -1327 -1326.55
000000010110011011 // 1435 1434.79
111111100111011010 // -1574 -1573.96
000000011011100011 // 1763 1763.3
111111100000000110 // -2042 -2041.67
000000100111000110 // 2502 2501.72
111111001010011111 // -3425 -3425.2
000001100010011100 // 6300 6299.88
010100001010001111 // 82575 82574.73
111110111111001111 // -4145 -4145.21
000000011011100101 // 1765 1764.83
111111110001010111 // -937 -937.39
000000001000000101 // 517 517.3
111111111011111001 // -263 -263.41
000000000001011110 // 94 94.35
000000000000011001 // 25 25.43
111111111110001110 // -114 -113.89
000000000010110101 // 181 181.19
111111111100010111 // -233 -233.21
000000000100010010 // 274 273.75
111111111011001111 // -305 -305.44
000000000101001010 // 330 330.2
111111111010100011 // -349 -349.37
000000000101101100 // 364 363.85
111111111010001010 // -374 -374.34
000000000101111101 // 381 381.42
111111111001111110 // -386 -385.61
000000000110000011 // 387 387.31
111111111001111101 // -387 -386.85
000000000110000000 // 384 384.48
111111111010000100 // -380 -380.43
000000000101110111 // 375 374.85
111111111010010000 // -368 -367.93
000000000101101000 // 360 359.87
111111111010100001 // -351 -350.84
000000000101010101 // 341 340.96
111111111010110110 // -330 -330.35
000000000100111111 // 319 319.1
111111111011001101 // -307 -307.32
000000000100100111 // 295 295.08
111111111011100110 // -282 -282.48
000000000100001110 // 270 269.6
111111111011111111 // -257 -256.58
000000000011110011 // 243 243.48
111111111100011010 // -230 -230.35
000000000011011001 // 217 217.25
111111111100110100 // -204 -204.26
000000000010111111 // 191 191.44
111111111101001101 // -179 -178.84
000000000010100110 // 166 166.48
111111111101100110 // -154 -154.43
000000000010001111 // 143 142.73
111111111101111101 // -131 -131.45
000000000001111001 // 121 120.59
111111111110010010 // -110 -110.22
000000000001100100 // 100 100.39
111111111110100101 // -91 -91.2
000000000001010011 // 83 82.65
111111111110110101 // -75 -74.85
000000000001000100 // 68 67.89
111111111111000010 // -62 -62.03
000000000000111001 // 57 57.33
111111111111001010 // -54 -54.12
000000000000110100 // 52 52.4
111111111111001100 // -52 -51.78
000000000000110000 // 48 48.15
111111111111101001 // -23 -23.23
111111111101010100 // -172 -171.9
111111111111100101 // -27 -26.86
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0
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/firromH.qip 100644
Wyświetl plik

162
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/firromH.v 100644
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@ -0,0 +1,162 @@
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: firromH.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module firromH (
address,
clock,
q);
parameter init_file = "missing_file.mif";
input [7:0] address;
input clock;
output [17:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
//tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [17:0] sub_wire0;
wire [17:0] q = sub_wire0[17:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({18{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = init_file,
altsyncram_component.intended_device_family = "Cyclone 10 LP",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 18,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./Polyphase_FIR/xx.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "18"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./Polyphase_FIR/xx.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0
// Retrieval info: GEN_FILE: TYPE_NORMAL firromH.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL firromH.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firromH.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firromH.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firromH_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firromH_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

0
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/firromI_1024.qip 100644
Wyświetl plik

162
WSPRBerry/wsprberry-verilog-fpga/rtl/radio_openhpsdr/firrom/firromI_1024.v 100644
Wyświetl plik

@ -0,0 +1,162 @@
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: firromI_1024.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module firromI_1024 (
address,
clock,
q);
parameter init_file = "missing_file.mif";
input [9:0] address;
input clock;
output [17:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [17:0] sub_wire0;
wire [17:0] q = sub_wire0[17:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({18{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = init_file,
altsyncram_component.intended_device_family = "Cyclone 10 LP",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 18,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./Polyphase_FIR/coefI8_1024.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "18"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./Polyphase_FIR/coefI8_1024.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0
// Retrieval info: GEN_FILE: TYPE_NORMAL firromI_1024.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL firromI_1024.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firromI_1024.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firromI_1024.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firromI_1024_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firromI_1024_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

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// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: firrom1_1025.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module firrom1_1025 (
address,
clock,
q);
input [10:0] address;
input clock;
output [17:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [17:0] sub_wire0;
wire [17:0] q = sub_wire0[17:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({18{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./rtl/radio_openhpsdr/coefI5_1025_EER.mif",
altsyncram_component.intended_device_family = "Cyclone 10 LP",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1025,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 18,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./rtl/radio_openhpsdr/coefI5_1025_EER.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1025"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "18"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/radio_openhpsdr/coefI5_1025_EER.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1025"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0
// Retrieval info: GEN_FILE: TYPE_NORMAL firrom1_1025.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL firrom1_1025.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firrom1_1025.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firrom1_1025.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firrom1_1025_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL firrom1_1025_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

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/*
--------------------------------------------------------------------------------
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
License as published by the Free Software Foundation; either
version 2 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Library General Public License for more details.
You should have received a copy of the GNU Library General Public
License along with this library; if not, write to the
Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
Boston, MA 02110-1301, USA.
--------------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Copyright (c) 2008 Alex Shovkoplyas, VE3NEA
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Copyright (c) 2013 Phil Harman, VK6APH
//------------------------------------------------------------------------------
// 2013 Jan 26 - varcic now accepts 2...40 as decimation and CFIR
// replaced with Polyphase FIR - VK6APH
// 2015 Jan 31 - updated for Hermes-Lite 12bit Steve Haynal KF7O
module receiver(
input clock, //61.44 MHz
input clock_2x,
input [5:0] rate, //48k....384k
input [31:0] frequency,
output out_strobe,
input signed [11:0] in_data,
output [23:0] out_data_I,
output [23:0] out_data_Q
);
parameter CICRATE;
wire signed [17:0] cordic_outdata_I;
wire signed [17:0] cordic_outdata_Q;
// gain adjustment, Hermes reduced by 6dB to match previous receiver code.
// Hermes-Lite gain reduced to calibrate QtRadio
wire signed [23:0] out_data_I2;
wire signed [23:0] out_data_Q2;
assign out_data_I = out_data_I2; //>>> 3);
assign out_data_Q = out_data_Q2; //>>> 3);
//------------------------------------------------------------------------------
// cordic
//------------------------------------------------------------------------------
cordic cordic_inst(
.clock(clock),
.in_data(in_data), //12 bit
.frequency(frequency), //32 bit
.out_data_I(cordic_outdata_I), //18 bit
.out_data_Q(cordic_outdata_Q)
);
// Receive CIC filters followed by FIR filter
wire decimA_avail, decimB_avail, decimC_avail;
wire signed [15:0] decimA_real, decimA_imag;
wire signed [15:0] decimB_real, decimB_imag;
wire signed [15:0] decimC_real, decimC_imag;
localparam VARCICWIDTH = (CICRATE == 10) ? 36 : (CICRATE == 13) ? 36 : (CICRATE == 5) ? 43 : 39; // Last is default rate of 8
localparam ACCWIDTH = (CICRATE == 10) ? 28 : (CICRATE == 13) ? 30 : (CICRATE == 5) ? 25 : 27; // Last is default rate of 8
// CIC filter
//I channel
cic #(.STAGES(3), .DECIMATION(CICRATE), .IN_WIDTH(18), .ACC_WIDTH(ACCWIDTH), .OUT_WIDTH(16))
cic_inst_I2(
.clock(clock),
.in_strobe(1'b1),
.out_strobe(decimA_avail),
.in_data(cordic_outdata_I),
.out_data(decimA_real)
);
//Q channel
cic #(.STAGES(3), .DECIMATION(CICRATE), .IN_WIDTH(18), .ACC_WIDTH(ACCWIDTH), .OUT_WIDTH(16))
cic_inst_Q2(
.clock(clock),
.in_strobe(1'b1),
.out_strobe(),
.in_data(cordic_outdata_Q),
.out_data(decimA_imag)
);
// Variable CIC filter - in width = out width = 14 bits, decimation rate = 2 to 16
//I channel
varcic #(.STAGES(5), .IN_WIDTH(16), .ACC_WIDTH(VARCICWIDTH), .OUT_WIDTH(16), .CICRATE(CICRATE))
varcic_inst_I1(
.clock(clock),
.in_strobe(decimA_avail),
.decimation(6'd40),
.out_strobe(decimB_avail),
.in_data(decimA_real),
.out_data(decimB_real)
);
//Q channel
varcic #(.STAGES(5), .IN_WIDTH(16), .ACC_WIDTH(VARCICWIDTH), .OUT_WIDTH(16), .CICRATE(CICRATE))
varcic_inst_Q1(
.clock(clock),
.in_strobe(decimA_avail),
.decimation(6'd40),
.out_strobe(),
.in_data(decimA_imag),
.out_data(decimB_imag)
);
// Variable CIC filter - in width = out width = 14 bits, decimation rate = 2 to 16
//I channel
varcic #(.STAGES(5), .IN_WIDTH(16), .ACC_WIDTH(VARCICWIDTH), .OUT_WIDTH(16), .CICRATE(CICRATE))
varcic_inst2_I1(
.clock(clock),
.in_strobe(decimB_avail),
.decimation(6'd40),
.out_strobe(decimC_avail),
.in_data(decimB_real),
.out_data(decimC_real)
);
//Q channel
varcic #(.STAGES(5), .IN_WIDTH(16), .ACC_WIDTH(VARCICWIDTH), .OUT_WIDTH(16), .CICRATE(CICRATE))
varcic_inst2_Q1(
.clock(clock),
.in_strobe(decimB_avail),
.decimation(6'd40),
.out_strobe(),
.in_data(decimB_imag),
.out_data(decimC_imag)
);
firX8R8 fir2 (clock, clock_2x, decimC_avail, {{2{decimC_real[15]}},decimC_real}, {{2{decimC_imag[15]}},decimC_imag}, out_strobe, out_data_I2, out_data_Q2);
endmodule

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/*
--------------------------------------------------------------------------------
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
License as published by the Free Software Foundation; either
version 2 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Library General Public License for more details.
You should have received a copy of the GNU Library General Public
License along with this library; if not, write to the
Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
Boston, MA 02110-1301, USA.
--------------------------------------------------------------------------------
*/
//------------------------------------------------------------------------------
// Copyright (c) 2008 Alex Shovkoplyas, VE3NEA
//------------------------------------------------------------------------------
// 2013 Jan 26 - Modified to accept decimation values from 1-40. VK6APH
module varcic(decimation, clock, in_strobe, out_strobe, in_data, out_data );
//design parameters
parameter STAGES = 5;
parameter IN_WIDTH = 18;
parameter ACC_WIDTH = 45;
parameter OUT_WIDTH = 18;
parameter CICRATE = 12;
input [5:0] decimation;
input clock;
input in_strobe;
output reg out_strobe;
input signed [IN_WIDTH-1:0] in_data;
output reg signed [OUT_WIDTH-1:0] out_data;
//------------------------------------------------------------------------------
// control
//------------------------------------------------------------------------------
reg [15:0] sample_no = 0;
always @(posedge clock)
if (in_strobe)
begin
if (sample_no == (decimation - 1))
begin
sample_no <= 0;
out_strobe <= 1;
end
else
begin
sample_no <= sample_no + 8'd1;
out_strobe <= 0;
end
end
else
out_strobe <= 0;
//------------------------------------------------------------------------------
// stages
//------------------------------------------------------------------------------
wire signed [ACC_WIDTH-1:0] integrator_data [0:STAGES];
wire signed [ACC_WIDTH-1:0] comb_data [0:STAGES];
assign integrator_data[0] = in_data;
assign comb_data[0] = integrator_data[STAGES];
genvar i;
generate
for (i=0; i<STAGES; i=i+1)
begin : cic_stages
cic_integrator #(ACC_WIDTH) cic_integrator_inst(
.clock(clock),
.strobe(in_strobe),
.in_data(integrator_data[i]),
.out_data(integrator_data[i+1])
);
cic_comb #(ACC_WIDTH) cic_comb_inst(
.clock(clock),
.strobe(out_strobe),
.in_data(comb_data[i]),
.out_data(comb_data[i+1])
);
end
endgenerate
//------------------------------------------------------------------------------
// output rounding
//------------------------------------------------------------------------------
/*
-----------------------------------------------------
Output rounding calculations for 5 stages
sample rate (ksps) decimation bit growth
48 16 34-14 = 20
96 8 29-14 = 15
192 4 24-14 = 10
384 2 19-14 = 5
-------------------------------------------------------
*/
// also math.log(growthN,2) * 5
// FIXME: Should be cleaner way to do all this...
localparam GROWTH2 = 5;
localparam GROWTH4 = 10;
localparam GROWTH8 = 15;
localparam GROWTH16 = 20;
localparam MSB2 = (IN_WIDTH + GROWTH2) - 1;
localparam LSB2 = (IN_WIDTH + GROWTH2) - OUT_WIDTH;
localparam MSB4 = (IN_WIDTH + GROWTH4) - 1;
localparam LSB4 = (IN_WIDTH + GROWTH4) - OUT_WIDTH;
localparam MSB8 = (IN_WIDTH + GROWTH8) - 1;
localparam LSB8 = (IN_WIDTH + GROWTH8) - OUT_WIDTH;
localparam MSB16 = (IN_WIDTH + GROWTH16) - 1;
localparam LSB16 = (IN_WIDTH + GROWTH16) - OUT_WIDTH;
localparam GROWTH3 = 8;
localparam GROWTH6 = 13;
localparam GROWTH12 = 18;
localparam GROWTH24 = 23;
localparam MSB3 = (IN_WIDTH + GROWTH3) - 1;
localparam LSB3 = (IN_WIDTH + GROWTH3) - OUT_WIDTH;
localparam MSB6 = (IN_WIDTH + GROWTH6) - 1;
localparam LSB6 = (IN_WIDTH + GROWTH6) - OUT_WIDTH;
localparam MSB12 = (IN_WIDTH + GROWTH12) - 1;
localparam LSB12 = (IN_WIDTH + GROWTH12) - OUT_WIDTH;
localparam MSB24 = (IN_WIDTH + GROWTH24) - 1;
localparam LSB24 = (IN_WIDTH + GROWTH24) - OUT_WIDTH;
localparam GROWTH5 = 12;
localparam GROWTH10 = 17;
localparam GROWTH20 = 22;
localparam GROWTH40 = 27;
localparam MSB5 = (IN_WIDTH + GROWTH5) - 1;
localparam LSB5 = (IN_WIDTH + GROWTH5) - OUT_WIDTH;
localparam MSB10 = (IN_WIDTH + GROWTH10) - 1;
localparam LSB10 = (IN_WIDTH + GROWTH10) - OUT_WIDTH;
localparam MSB20 = (IN_WIDTH + GROWTH20) - 1;
localparam LSB20 = (IN_WIDTH + GROWTH20) - OUT_WIDTH;
localparam MSB40 = (IN_WIDTH + GROWTH40) - 1;
localparam LSB40 = (IN_WIDTH + GROWTH40) - OUT_WIDTH;
generate
if (CICRATE == 10)
always @(posedge clock)
case (decimation)
2: out_data <= comb_data[STAGES][MSB2:LSB2] + comb_data[STAGES][LSB2-1];
4: out_data <= comb_data[STAGES][MSB4:LSB4] + comb_data[STAGES][LSB4-1];
8: out_data <= comb_data[STAGES][MSB8:LSB8] + comb_data[STAGES][LSB8-1];
default: out_data <= comb_data[STAGES][MSB16:LSB16] + comb_data[STAGES][LSB16-1];
endcase
else if (CICRATE == 13)
always @(posedge clock)
case (decimation)
2: out_data <= comb_data[STAGES][MSB2:LSB2] + comb_data[STAGES][LSB2-1];
4: out_data <= comb_data[STAGES][MSB4:LSB4] + comb_data[STAGES][LSB4-1];
8: out_data <= comb_data[STAGES][MSB8:LSB8] + comb_data[STAGES][LSB8-1];
default: out_data <= comb_data[STAGES][MSB16:LSB16] + comb_data[STAGES][LSB16-1];
endcase
else if (CICRATE == 5)
always @(posedge clock)
case (decimation)
5: out_data <= comb_data[STAGES][MSB5:LSB5] + comb_data[STAGES][LSB5-1];
10: out_data <= comb_data[STAGES][MSB10:LSB10] + comb_data[STAGES][LSB10-1];
20: out_data <= comb_data[STAGES][MSB20:LSB20] + comb_data[STAGES][LSB20-1];
default: out_data <= comb_data[STAGES][MSB40:LSB40] + comb_data[STAGES][LSB40-1];
endcase
else
always @(posedge clock)
case (decimation)
3: out_data <= comb_data[STAGES][MSB3:LSB3] + comb_data[STAGES][LSB3-1];
6: out_data <= comb_data[STAGES][MSB6:LSB6] + comb_data[STAGES][LSB6-1];
12: out_data <= comb_data[STAGES][MSB12:LSB12] + comb_data[STAGES][LSB12-1];
default: out_data <= comb_data[STAGES][MSB24:LSB24] + comb_data[STAGES][LSB24-1];
endcase
endgenerate
endmodule

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// Project : Radioberry
//
// Module : Top level design radioberry.v
//
// Target Devices : Cyclone 10LP
//
// Tool : Quartus Prime Lite Edition v17.0.2
//
//------------------------------------------------------------------------------------------------------------------------------------------------------------
// Description:
//
// Radioberry v2.0 SDR firmware code.
//
//
//
// Johan Maas PA3GSB
//
// Date: 21 December 2018
//
//------------------------------------------------------------------------------------------------------------------------------------------------------------
`include "timescale.v"
module radioberry(
clk_76m8,
ad9866_clk,ad9866_rx,ad9866_tx,ad9866_rxsync,ad9866_rxclk,ad9866_txsync,ad9866_txquietn,ad9866_sclk,ad9866_sdio,ad9866_sdo,ad9866_sen_n,ad9866_rst_n,ad9866_mode,
spi_sck, spi_mosi, spi_miso, spi_ce,
rx_FIFOEmpty);
input wire clk_76m8;
input wire ad9866_clk;
input [5:0] ad9866_rx;
output [5:0] ad9866_tx;
input ad9866_rxsync;
input ad9866_rxclk;
output ad9866_txsync;
output ad9866_txquietn;
output wire ad9866_sclk;
output wire ad9866_sdio;
input wire ad9866_sdo;
output wire ad9866_sen_n;
output wire ad9866_rst_n;
output ad9866_mode;
// SPI connect to Raspberry PI SPI-0.
input wire spi_sck;
input wire spi_mosi;
output wire spi_miso;
input [1:0] spi_ce;
//rx data
output wire rx_FIFOEmpty;
logic clk_ad9866;
logic clk_ad9866_2x;
//------------------------------------------------------------------------------------------------------------------------------------------------------------
// AD9866 Control
//------------------------------------------------------------------------------------------------------------------------------------------------------------
assign ad9866_mode = 1'b1; //FULLDUPLEX
assign ad9866_rst_n = ~reset;
// RX Path
logic [11:0] rx_data_assemble;
logic [5:0] rffe_ad9866_rx_d1, rffe_ad9866_rx_d2;
logic rffe_ad9866_rxsync_d1;
always @(posedge clk_ad9866_2x) begin
rffe_ad9866_rx_d1 <= ad9866_rx;
rffe_ad9866_rx_d2 <= rffe_ad9866_rx_d1;
rffe_ad9866_rxsync_d1 <= ad9866_rxsync;
if (rffe_ad9866_rxsync_d1) rx_data_assemble <= {rffe_ad9866_rx_d2,rffe_ad9866_rx_d1};
end
// TX Path
logic [11:0] tx_data_d1;
logic tx_sync;
logic tx_en_d1;
always @(posedge clk_ad9866_2x) begin
tx_en_d1 <= 1'b0;
tx_sync <= ~tx_sync;
if (tx_en_d1) begin
if (tx_sync) begin
tx_data_d1 <= DACDp;
ad9866_tx <= tx_data_d1[5:0];
end else begin
ad9866_tx <= tx_data_d1[11:6];
end
ad9866_txsync <= tx_sync;
end else begin
ad9866_tx <= 6'h00;
ad9866_txsync <= 1'b0;
end
end
assign ad9866_txquietn = tx_en_d1;
reg [5:0] prev_rx_gain;
reg [5:0] prev_tx_gain;
always @ (posedge clk_internal)
begin
prev_rx_gain <= rx_gain;
prev_tx_gain <= tx_gain;
end
assign ad9866_rx_rqst = rx_gain != prev_rx_gain;
assign ad9866_tx_rqst = tx_gain != prev_tx_gain;
ad9866 ad9866_inst(.reset(reset),.clk(clk_internal),.sclk(ad9866_sclk),.sdio(ad9866_sdio),.sdo(ad9866_sdo),.sen_n(ad9866_sen_n),.dataout(),.ext_tx_rqst(ad9866_tx_rqst),.tx_gain(tx_gain),.ext_rx_rqst(ad9866_rx_rqst),.rx_gain(rx_gain));
//------------------------------------------------------------------------------------------------------------------------------------------------------------
// SPI Control
//------------------------------------------------------------------------------------------------------------------------------------------------------------
wire [47:0] spi_recv;
wire spi_done;
reg [2:0] nnrx;
always @ (posedge spi_done)
begin
rx_gain <= ~spi_recv[37:32];
nnrx <= spi_recv[44:42];
end
always @ (negedge spi_done)
begin
rx_freq[nnrx] <= spi_recv[31:0];
end
spi_slave spi_slave_rx_inst(.rstb(!reset),.ten(1'b1),.tdata(rxDataFromFIFO[nnrx]),.mlb(1'b1),.ss(spi_ce[0]),.sck(spi_sck),.sdin(spi_mosi), .sdout(spi_miso),.done(spi_done),.rdata(spi_recv));
//------------------------------------------------------------------------------------------------------------------------------------------------------------
// Convert frequency to phase word
//
// Calculates ratio = fo/fs = frequency/73.728Mhz where frequency is in MHz
//
//------------------------------------------------------------------------------------------------------------------------------------------------------------
wire [31:0] sync_phase_word [0:NR-1];
wire [63:0] ratio [0:NR-1];
reg[31:0] rx_freq[0:NR-1];
localparam M2 = 32'd1876499845; // B57 = 2^57. M2 = B57/CLK_FREQ = 76800000
localparam M3 = 32'd16777216; // M3 = 2^24, used to round the result
generate
genvar n;
for (n = 0; n < NR; n = n + 1) // calc freq phase word for nRx Channel
begin: MDC
assign ratio[n] = rx_freq[n] * M2 + M3;
assign sync_phase_word[n] = ratio[n][56:25];
end
endgenerate
//------------------------------------------------------------------------------
// Software Reset Handler
//------------------------------------------------------------------------------
wire reset;
reset_handler reset_handler_inst(.clock(clk_internal), .reset(reset));
//------------------------------------------------------------------------------
// Pipeline for adc fanout
//------------------------------------------------------------------------------
reg [11:0] adcpipe [0:7];
always @ (posedge clk_ad9866) begin
adcpipe[0] <= rx_data_assemble;
adcpipe[1] <= rx_data_assemble;
adcpipe[2] <= rx_data_assemble;
adcpipe[3] <= rx_data_assemble;
adcpipe[4] <= rx_data_assemble;
adcpipe[5] <= rx_data_assemble;
adcpipe[6] <= rx_data_assemble;
adcpipe[7] <= rx_data_assemble;
end
//------------------------------------------------------------------------------------------------------------------------------------------------------------
// Receiver module nRx
//------------------------------------------------------------------------------------------------------------------------------------------------------------
`ifdef wsprberry_cl025
localparam NR = 5; // Number of Receivers
`else
localparam NR = 3; // Number of Receivers
`endif
wire [23:0] rx_I [0:NR-1];
wire [23:0] rx_Q [0:NR-1];
wire rx_strobe [0:NR-1];
localparam CICRATE = 6'd16;
wire [47:0] rxDataFromFIFO [0:NR-1];
wire emptyFIFO[0:NR-1];
generate
genvar c;
for (c = 0; c < NR; c = c + 1)
begin: NRX
receiver #(.CICRATE(CICRATE)) receiver_inst( .clock(clk_ad9866),
.clock_2x(clk_ad9866_2x),
.rate(6'd24),
.frequency(sync_phase_word[c]),
.out_strobe(rx_strobe[c]),
.in_data(adcpipe[c]),
.out_data_I(rx_I[c]),
.out_data_Q(rx_Q[c]));
rxFIFO rxFIFO_inst( .aclr(reset),
.wrclk(clk_ad9866),.data({rx_I[c], rx_Q[c]}),.wrreq(rx_strobe[c]), .wrempty(emptyFIFO[c]),
.rdclk(~spi_ce[0]),.q(rxDataFromFIFO[c]),.rdreq(nnrx==c ? 1'b1 : 1'b0 ));
end
endgenerate
`ifdef wsprberry_cl025
assign rx_FIFOEmpty = emptyFIFO[0] || emptyFIFO[1] || emptyFIFO[2] || emptyFIFO[3] || emptyFIFO[4];
`else
assign rx_FIFOEmpty = emptyFIFO[0] || emptyFIFO[1] || emptyFIFO[2];
`endif
wire clk_envelope;
wire clk_internal;
ad9866pll ad9866pll_inst (.inclk0(clk_76m8), .c0(clk_ad9866), .c1(clk_ad9866_2x), .c2(clk_envelope), .c3(clk_internal), .locked());
wire [11:0] DAC;
reg [11:0] DACDp;
always @ (negedge clk_ad9866) DACDp <= DAC;
//------------------------------------------------------------------------------
// Running...
//------------------------------------------------------------------------------
reg [26:0]counter;
always @(posedge clk_internal)
begin
if (reset)
counter <= 26'b0;
else
counter <= counter + 1'b1;
end
wire gain_update;
assign gain_update = counter[22];
endmodule

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// Project: RXSDR
//
// Design: Reset handler
// Module: reset_handler
// Johan Maas PA3GSB
// Date: 8 December 2010
`include "timescale.v"
module reset_handler(clock, reset);
input clock;
output reset;
reg reset;
reg [23:0] reset_counter;
always @(posedge clock)
begin
if (reset_counter > 24'h0F0000)
reset <= 1'b0;
else begin
reset <= 1'b1;
reset_counter <= reset_counter +1;
end
end
initial
begin
reset_counter = 24'h000000;
reset = 1'b1;
$display ("Reset handler initialization done");
end
endmodule

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//------------------------------------------------------------------------------------------------------------------------------------------------------------
//
// SPI Verilog (copied from opencores.org).
//
//------------------------------------------------------------------------------------------------------------------------------------------------------------
/* SPI MODE 3
CHANGE DATA (sdout) @ NEGEDGE SCK
read data (sdin) @posedge SCK
*/
`include "timescale.v"
module spi_slave (rstb,ten,tdata,mlb,ss,sck,sdin, sdout,done,rdata);
parameter WIDTH = 48;
input rstb,ss,sck,sdin,ten,mlb;
input [WIDTH-1:0] tdata;
output sdout; //slave out master in
output reg done;
output reg [WIDTH-1:0] rdata;
reg [WIDTH-1:0] treg,rreg;
reg [6:0] nb;
wire sout;
assign sout=mlb?treg[WIDTH-1]:treg[0];
assign sdout=( (!ss)&&ten )?sout:1'bz; //if 1=> send data else TRI-STATE sdout
//read from sdout
always @(posedge sck or negedge rstb)
begin
if (rstb==0)
begin rreg = 0; rdata = 0; done = 0; nb = 0; end //
else if (!ss) begin
if(mlb==0) //LSB first, in@msb -> right shift
begin rreg ={sdin,rreg[WIDTH-1:1]}; end
else //MSB first, in@lsb -> left shift
begin rreg ={rreg[WIDTH-2:0],sdin}; end
//increment bit count
nb=nb+1;
if(nb!=WIDTH) done=0;
else begin rdata=rreg; done=1; nb=0; end
end //if(!ss)_END if(nb==8)
end
//send to sdout
always @(negedge sck or negedge rstb)
begin
if (rstb==0)
begin treg = 48'hFF; end
else begin
if(!ss) begin
if(nb==0) treg=tdata;
else begin
if(mlb==0) //LSB first, out=lsb -> right shift
begin treg = {1'b1,treg[WIDTH-1:1]}; end
else //MSB first, out=msb -> left shift
begin treg = {treg[WIDTH-2:0],1'b1}; end
end
end //!ss
end //rstb
end //always
endmodule

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`timescale 1ns / 10ps

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WSPRBerry/wsprberry-verilog-fpga/rtl/transmitter.v 100644
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//------------------------------------------------------------------------------------------------------------------------------------------------------------
// Transmitter code
//------------------------------------------------------------------------------------------------------------------------------------------------------------
module transmitter(
reset,
clk,
frequency,
tsiq_data,
tsiq_read_strobe,
tsiq_valid,
CW_RF,
out_data,
PTT,
CW_PTT,
LED);
input wire reset;
input wire clk;
input [31:0] frequency;
input wire [31:0]tsiq_data;
output wire tsiq_read_strobe;
input wire tsiq_valid;
input wire [15:0] CW_RF;
output reg [11:0] out_data;
input wire PTT;
input wire CW_PTT;
output wire LED;
//------------------------------------------------------------------------------------------------------------------------------------------------------------
// Read IQ data from txFIFO
//------------------------------------------------------------------------------------------------------------------------------------------------------------
reg signed [15:0]fir_i;
reg signed [15:0]fir_q;
assign tsiq_read_strobe = req1;
// latch I&Q data on strobe from FIR
always @ (posedge clk)
begin
if (req1 & tsiq_valid ) begin
fir_i <= tsiq_data[31:16];
fir_q <= tsiq_data[15:0];
end
end
// Interpolate I/Q samples from 48 kHz to the clock frequency
wire req1, req2;
wire [19:0] y1_r, y1_i;
wire [15:0] y2_r, y2_i;
FirInterp8_1024 fi (clk, req2, req1, fir_i, fir_q, y1_r, y1_i); // req2 enables an output sample, req1 requests next input sample.
// GBITS reduced to 31
CicInterpM5 #(.RRRR(200), .IBITS(20), .OBITS(16), .GBITS(31)) in2 ( clk, 1'd1, req2, y1_r, y1_i, y2_r, y2_i);
//---------------------------------------------------------
// CORDIC NCO
//---------------------------------------------------------
wire signed [15:0] cordic_i_out;
cpl_cordic #(.OUT_WIDTH(16))
cordic_inst (.clock(clk), .frequency(frequency), .in_data_I(CW_PTT? CW_RF: y2_i),
.in_data_Q(CW_PTT? 16'd0: y2_r), .out_data_I(cordic_i_out), .out_data_Q());
wire signed [15:0] gated;
assign gated = PTT ? (cordic_i_out >>> 4) : 16'd0;
always @ (negedge clk) out_data <= gated[11:0];
//------------------------------------------------------------------------------------------------------------------------------------------------------------
// Heartbeat (LED flashes twice as fast when PTT active)
//------------------------------------------------------------------------------------------------------------------------------------------------------------
reg[26:0]counter;
always @(posedge clk) counter = counter + 1'b1;
assign LED = PTT ? counter[24] : counter[26];
endmodule

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set_time_format -unit ns -decimal_places 3
create_clock -name spi_sck -period 15.625MHz [get_ports spi_sck]
create_clock -name spi_ce0 -period 0.400MHz [get_ports {spi_ce[0]}]
create_clock -name spi_ce1 -period 0.400MHz [get_ports {spi_ce[1]}]
create_clock -name {spi_slave:spi_slave_rx2_inst|done} -period 0.400MHz [get_registers {spi_slave:spi_slave_rx2_inst|done}]
create_clock -name {spi_slave:spi_slave_rx_inst|done} -period 0.400MHz [get_registers {spi_slave:spi_slave_rx_inst|done}]
create_clock -name clk_76m8 -period 76.800MHz [get_ports clk_76m8]
create_clock -name virt_ad9866_rxclk_rx -period 153.600MHz
create_clock -name virt_ad9866_rxclk_tx -period 153.600MHz
create_clock -name {ad9866:ad9866_inst|dut1_pc[0]} -period 10.000 [get_registers {ad9866:ad9866_inst|dut1_pc[0]}]
derive_pll_clocks
derive_clock_uncertainty
set_clock_groups -asynchronous \
-group { clk_76m8 }\
-group { ad9866pll_inst|altpll_component|auto_generated|pll1|clk[0]} \
-group { ad9866pll_inst|altpll_component|auto_generated|pll1|clk[1]} \
-group { ad9866pll_inst|altpll_component|auto_generated|pll1|clk[2]} \
-group { ad9866pll_inst|altpll_component|auto_generated|pll1|clk[3]} \
-group { spi_ce0 } \
-group { spi_ce1 } \
-group { spi_slave:spi_slave_rx_inst|done } \
-group { spi_slave:spi_slave_rx2_inst|done } \
-group { ad9866:ad9866_inst|dut1_pc[0]}
# CLOCK
set_false_path -from {ad9866pll_inst|altpll_component|auto_generated|pll1|clk[3]}
# IO
set_false_path -from [get_ports {spi_mosi}]
set_false_path -to [get_ports {spi_miso}]
set_false_path -from [get_ports {spi_ce[*]}]
set_false_path -to [get_ports {rx_FIFOEmpty}]
## AD9866 RX Path
## See http://billauer.co.il/blog/2017/04/altera-intel-fpga-io-ff-packing/
set_input_delay -add_delay -max -clock virt_ad9866_rxclk_rx 5.0 [get_ports {ad9866_rxsync}]
set_input_delay -add_delay -min -clock virt_ad9866_rxclk_rx 0.0 [get_ports {ad9866_rxsync}]
set_input_delay -add_delay -max -clock virt_ad9866_rxclk_rx 5.0 [get_ports {ad9866_rx[*]}]
set_input_delay -add_delay -min -clock virt_ad9866_rxclk_rx 0.0 [get_ports {ad9866_rx[*]}]
## AD9866 TX Path
set_output_delay -add_delay -max -clock virt_ad9866_rxclk_tx 2.5 [get_ports {ad9866_txsync}]
set_output_delay -add_delay -min -clock virt_ad9866_rxclk_tx 0.0 [get_ports {ad9866_txsync}]
set_output_delay -add_delay -max -clock virt_ad9866_rxclk_tx 2.5 [get_ports {ad9866_tx[*]}]
set_output_delay -add_delay -min -clock virt_ad9866_rxclk_tx 0.0 [get_ports {ad9866_tx[*]}]
## AD9866 Other IO
set_false_path -to [get_ports {ad9866_sclk}]
set_false_path -to [get_ports {ad9866_sdio}]
set_false_path -from [get_ports {ad9866_sdo}]
set_false_path -to [get_ports {ad9866_sen_n}]
set_false_path -to [get_ports {ad9866_rst_n}]
set_false_path -to [get_ports {ad9866_mode}]
set_false_path -to [get_ports {ad9866_txquietn}]
## Additional timing constraints
set_max_delay -from nnrx[*] -to spi_slave:spi_slave_rx_inst|treg[*] 7
set_max_delay -from spi_slave:spi_slave_rx_inst|rdata[*] -to rx_freq[*][*] 4
set_max_delay -from rxFIFO:NRX[*].rxFIFO_inst|dcfifo:dcfifo_component|dcfifo_8pj1:auto_generated|wrptr_g[*] -to rx_FIFOEmpty 16
set_max_delay -from rxFIFO:NRX[*].rxFIFO_inst|dcfifo:dcfifo_component|dcfifo_8pj1:auto_generated|ws_dgrp_reg[*] -to rx_FIFOEmpty 16
set_max_delay -from rxFIFO:NRX[*].rxFIFO_inst|dcfifo:dcfifo_component|dcfifo_8pj1:auto_generated|altsyncram_hv61:fifo_ram|q_b[*] -to spi_slave:spi_slave_rx_inst|treg[*] 6
## end of constraints

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set_global_assignment -name VERILOG_FILE rtl/ad9866.v
set_global_assignment -name VERILOG_FILE rtl/ddr_mux.v
set_global_assignment -name VERILOG_FILE rtl/radioberry.v
set_global_assignment -name VERILOG_FILE rtl/reset_handler.v
set_global_assignment -name VERILOG_FILE rtl/spi_slave.v
set_global_assignment -name VERILOG_FILE rtl/timescale.v
set_global_assignment -name VERILOG_FILE rtl/transmitter.v
set_global_assignment -name VERILOG_FILE rtl/cyclone_ip/rxFIFO.v
set_global_assignment -name VERILOG_FILE rtl/cyclone_ip/txFIFO.v
set_global_assignment -name VERILOG_FILE rtl/cyclone_ip/counter.v
set_global_assignment -name VERILOG_FILE rtl/cyclone_ip/sqroot.v
set_global_assignment -name VERILOG_FILE rtl/cyclone_ip/square.v
set_global_assignment -name VERILOG_FILE rtl/cyclone_ip/ad9866pll.v
set_global_assignment -name VERILOG_FILE rtl/cyclone_ip/commandFIFO.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/cic.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/CicInterpM5.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/cic_comb.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/cic_integrator.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/cordic.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/cpl_cordic.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/firfilt.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/FirInterp8_1024.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/firram36.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/firram36I_1024.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/receiver.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/varcic.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/FirInterp5_1025_EER.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/FirInterp8_1024.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/firram36.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/firram36I_1024.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/firram36I_205.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/firrom1_1025.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/firrom/firromH.v
set_global_assignment -name VERILOG_FILE rtl/radio_openhpsdr/firrom/firromI_1024.v

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set_global_assignment -name FAMILY "Cyclone 10 LP"
#set_global_assignment -name DEVICE 10CL025YE144C8G
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name ALLOW_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"

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WSPRBerry/wsprberry-verilog-fpga/tcl/locations_radioberry_fd.tcl 100644
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set_location_assignment PIN_53 -to clk_76m8
set_location_assignment PIN_50 -to spi_ce[1]
set_location_assignment PIN_51 -to spi_ce[0]
set_location_assignment PIN_59 -to spi_miso
set_location_assignment PIN_60 -to spi_mosi
set_location_assignment PIN_58 -to spi_sck
set_location_assignment PIN_13 -to rx_FIFOEmpty
set_location_assignment PIN_111 -to ad9866_mode
set_location_assignment PIN_114 -to ad9866_rst_n
set_location_assignment PIN_65 -to ad9866_sen_n
set_location_assignment PIN_66 -to ad9866_sclk
set_location_assignment PIN_68 -to ad9866_sdio
set_location_assignment PIN_67 -to ad9866_sdo
set_location_assignment PIN_71 -to ad9866_rxclk
set_location_assignment PIN_69 -to ad9866_clk
set_location_assignment PIN_80 -to ad9866_rx[0]
set_location_assignment PIN_83 -to ad9866_rx[1]
set_location_assignment PIN_85 -to ad9866_rx[2]
set_location_assignment PIN_86 -to ad9866_rx[3]
set_location_assignment PIN_87 -to ad9866_rx[4]
set_location_assignment PIN_98 -to ad9866_rx[5]
set_location_assignment PIN_77 -to ad9866_rxsync
set_location_assignment PIN_99 -to ad9866_tx[0]
set_location_assignment PIN_100 -to ad9866_tx[1]
set_location_assignment PIN_101 -to ad9866_tx[2]
set_location_assignment PIN_103 -to ad9866_tx[3]
set_location_assignment PIN_105 -to ad9866_tx[4]
set_location_assignment PIN_106 -to ad9866_tx[5]
set_location_assignment PIN_72 -to ad9866_txquietn
set_location_assignment PIN_76 -to ad9866_txsync
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ad9866_tx[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ad9866_txsync
set_instance_assignment -name FAST_INPUT_REGISTER ON -to ad9866_rx[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to ad9866_rxsync
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ad9866_sdio
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ad9866_sen_n
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ad9866_sclk
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ad9866_rst_n
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ad9866_txquietn
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to *

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docs/wiki/radioberry-quisk-rpi-radio.JPG 100644
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fd-firmware/verilog-fpga/radioberry.qws
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