kopia lustrzana https://github.com/pa3gsb/Radioberry-2.x
radioberry v2.0 beta2
pa3gsb
rodzic
3e18ff7d94
commit
9c0cfbda74
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@ -0,0 +1,7 @@
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# no backup files
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*.bak
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/Firmware/db/**/
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/Firmware/output_files/**/
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/Firmware/greybox_tmp/**/
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/Firmware/incremental_db/**/
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27
README.md
27
README.md
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@ -1 +1,26 @@
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# Radioberry-2.x
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RadioBerry V2.0 - Ham radio cape for Raspberry PI
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==============================================
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## Main purpose of the project:
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- Building a HAM Radio
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- Learning (from noob to guru)
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## Radioberry:
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- Raspberry PI 3 Model B
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- Radio extension board (cape)
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- using AD9866 (12 bit) for RX and TX modes.
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## Radioberry Configurations:
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- Hermes emulator
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Supporting Openhpsdr protocol 1 enabling working with PowerSDR, Quisk, Spark and others.
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- Standalone transceiver
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By running pihpsdr.
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Plik binarny nie jest wyświetlany.
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Po Szerokość: | Wysokość: | Rozmiar: 499 KiB |
Plik binarny nie jest wyświetlany.
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Po Szerokość: | Wysokość: | Rozmiar: 664 KiB |
Plik binarny nie jest wyświetlany.
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Po Szerokość: | Wysokość: | Rozmiar: 494 KiB |
Plik binarny nie jest wyświetlany.
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Po Szerokość: | Wysokość: | Rozmiar: 472 KiB |
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@ -0,0 +1,3 @@
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db/
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greybox_tmp/
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incremental_db/
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Plik diff jest za duży
Load Diff
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@ -2,4 +2,3 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
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set_global_assignment -name IP_TOOL_VERSION "17.0"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "firram36.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "firram36_bb.v"]
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@ -14,7 +14,7 @@
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
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// ************************************************************
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@ -210,5 +210,5 @@ endmodule
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// Retrieval info: GEN_FILE: TYPE_NORMAL firram36.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL firram36.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL firram36_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL firram36_bb.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL firram36_bb.v FALSE
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// Retrieval info: LIB_FILE: altera_mf
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@ -14,7 +14,7 @@
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
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// ************************************************************
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@ -0,0 +1,4 @@
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set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
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set_global_assignment -name IP_TOOL_VERSION "17.0"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone 10 LP}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "firromH.v"]
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@ -14,7 +14,7 @@
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
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// ************************************************************
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@ -41,9 +41,9 @@ module firromH (
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address,
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clock,
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q);
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parameter MifFile = "missing_file.mif";
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parameter MifFile = "missing_file.mif";
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input [7:0] address;
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input clock;
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output [17:0] q;
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@ -121,7 +121,7 @@ endmodule
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING "xx.mif"
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// Retrieval info: PRIVATE: MIFfilename STRING "./Polyphase_FIR/xx.mif"
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// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
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@ -136,7 +136,7 @@ endmodule
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// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: INIT_FILE STRING "xx.mif"
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// Retrieval info: CONSTANT: INIT_FILE STRING "./Polyphase_FIR/xx.mif"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
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// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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@ -154,9 +154,9 @@ endmodule
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL firromH.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL firromH.inc TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL firromH.cmp TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL firromH.bsf TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL firromH_inst.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL firromH_bb.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL firromH.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL firromH.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL firromH.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL firromH_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL firromH_bb.v FALSE
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// Retrieval info: LIB_FILE: altera_mf
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@ -14,7 +14,7 @@
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
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// ************************************************************
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@ -84,7 +84,7 @@ module firromI_1024 (
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altsyncram_component.address_aclr_a = "NONE",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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altsyncram_component.init_file = "./rtl/Polyphase_FIR/coefI8_1024.mif",
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altsyncram_component.init_file = "./Polyphase_FIR/coefI8_1024.mif",
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altsyncram_component.intended_device_family = "Cyclone 10 LP",
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altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
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altsyncram_component.lpm_type = "altsyncram",
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@ -119,7 +119,7 @@ endmodule
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING "./rtl/Polyphase_FIR/coefI8_1024.mif"
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// Retrieval info: PRIVATE: MIFfilename STRING "./Polyphase_FIR/coefI8_1024.mif"
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// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
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@ -134,7 +134,7 @@ endmodule
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// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/Polyphase_FIR/coefI8_1024.mif"
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// Retrieval info: CONSTANT: INIT_FILE STRING "./Polyphase_FIR/coefI8_1024.mif"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
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// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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@ -1,20 +0,0 @@
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INTENDED_DEVICE_FAMILY="Cyclone 10 LP"
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LPM_NUMWORDS=256
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LPM_SHOWAHEAD=OFF
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LPM_TYPE=dcfifo
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LPM_WIDTH=8
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LPM_WIDTHU=8
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OVERFLOW_CHECKING=OFF
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RDSYNC_DELAYPIPE=5
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UNDERFLOW_CHECKING=OFF
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USE_EAB=ON
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WRSYNC_DELAYPIPE=5
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DEVICE_FAMILY="Cyclone 10 LP"
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data
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rdclk
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rdreq
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wrclk
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wrreq
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q
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rdempty
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wrempty
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@ -14,7 +14,7 @@
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
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// ************************************************************
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@ -45,17 +45,15 @@ module rxFIFO (
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wrclk,
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wrreq,
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q,
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rdempty,
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wrempty);
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input aclr;
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input [7:0] data;
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input [47:0] data;
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input rdclk;
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input rdreq;
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input wrclk;
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input wrreq;
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output [7:0] q;
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output rdempty;
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output [47:0] q;
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output wrempty;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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@ -65,12 +63,10 @@ module rxFIFO (
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// synopsys translate_on
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`endif
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wire [7:0] sub_wire0;
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wire [47:0] sub_wire0;
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wire sub_wire1;
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wire sub_wire2;
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wire [7:0] q = sub_wire0[7:0];
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wire rdempty = sub_wire1;
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wire wrempty = sub_wire2;
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wire [47:0] q = sub_wire0[47:0];
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wire wrempty = sub_wire1;
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dcfifo dcfifo_component (
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.aclr (aclr),
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@ -80,27 +76,27 @@ module rxFIFO (
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.wrclk (wrclk),
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.wrreq (wrreq),
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.q (sub_wire0),
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.rdempty (sub_wire1),
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.wrempty (sub_wire2),
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.wrempty (sub_wire1),
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.eccstatus (),
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.rdempty (),
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.rdfull (),
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.rdusedw (),
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.wrfull (),
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.wrusedw ());
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defparam
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dcfifo_component.intended_device_family = "Cyclone 10 LP",
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dcfifo_component.lpm_numwords = 256,
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dcfifo_component.lpm_numwords = 512,
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dcfifo_component.lpm_showahead = "OFF",
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dcfifo_component.lpm_type = "dcfifo",
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dcfifo_component.lpm_width = 8,
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dcfifo_component.lpm_widthu = 8,
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dcfifo_component.lpm_width = 48,
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dcfifo_component.lpm_widthu = 9,
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dcfifo_component.overflow_checking = "OFF",
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dcfifo_component.rdsync_delaypipe = 5,
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dcfifo_component.rdsync_delaypipe = 11,
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dcfifo_component.read_aclr_synch = "OFF",
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dcfifo_component.underflow_checking = "OFF",
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dcfifo_component.use_eab = "ON",
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dcfifo_component.write_aclr_synch = "OFF",
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dcfifo_component.wrsync_delaypipe = 5;
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dcfifo_component.wrsync_delaypipe = 11;
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endmodule
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@ -114,7 +110,7 @@ endmodule
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// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
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// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
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// Retrieval info: PRIVATE: Clock NUMERIC "4"
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// Retrieval info: PRIVATE: Depth NUMERIC "256"
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// Retrieval info: PRIVATE: Depth NUMERIC "512"
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// Retrieval info: PRIVATE: Empty NUMERIC "1"
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// Retrieval info: PRIVATE: Full NUMERIC "1"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
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@ -127,12 +123,12 @@ endmodule
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
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// Retrieval info: PRIVATE: UsedW NUMERIC "1"
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// Retrieval info: PRIVATE: Width NUMERIC "8"
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// Retrieval info: PRIVATE: Width NUMERIC "48"
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// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
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// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
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// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
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// Retrieval info: PRIVATE: output_width NUMERIC "8"
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// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
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// Retrieval info: PRIVATE: output_width NUMERIC "48"
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// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
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// Retrieval info: PRIVATE: rsFull NUMERIC "0"
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// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
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// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
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@ -142,35 +138,33 @@ endmodule
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// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
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// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
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// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
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// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
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// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "48"
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// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
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// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
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// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
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// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "11"
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// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
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// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
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// Retrieval info: CONSTANT: USE_EAB STRING "ON"
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// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
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// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
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// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "11"
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// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
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// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
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// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
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// Retrieval info: USED_PORT: data 0 0 48 0 INPUT NODEFVAL "data[47..0]"
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||||
// Retrieval info: USED_PORT: q 0 0 48 0 OUTPUT NODEFVAL "q[47..0]"
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||||
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
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// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
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// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
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// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
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// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
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// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
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// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
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// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
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// Retrieval info: CONNECT: @data 0 0 48 0 data 0 0 48 0
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// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
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// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
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// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
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// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
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// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 48 0 @q 0 0 48 0
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// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO.inc FALSE
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@ -14,7 +14,7 @@
|
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// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
|
||||
// 17.0.2 Build 602 07/19/2017 SJ Lite Edition
|
||||
// ************************************************************
|
||||
|
||||
//Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
|
|
@ -40,17 +40,15 @@ module rxFIFO (
|
|||
wrclk,
|
||||
wrreq,
|
||||
q,
|
||||
rdempty,
|
||||
wrempty);
|
||||
|
||||
input aclr;
|
||||
input [7:0] data;
|
||||
input [47:0] data;
|
||||
input rdclk;
|
||||
input rdreq;
|
||||
input wrclk;
|
||||
input wrreq;
|
||||
output [7:0] q;
|
||||
output rdempty;
|
||||
output [47:0] q;
|
||||
output wrempty;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
|
|
@ -71,7 +69,7 @@ endmodule
|
|||
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "256"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "512"
|
||||
// Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Full NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
|
||||
|
|
@ -84,12 +82,12 @@ endmodule
|
|||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "48"
|
||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: output_width NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: output_width NUMERIC "48"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
|
|
@ -99,35 +97,33 @@ endmodule
|
|||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "48"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "11"
|
||||
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "11"
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
|
||||
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
|
||||
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
|
||||
// Retrieval info: USED_PORT: data 0 0 48 0 INPUT NODEFVAL "data[47..0]"
|
||||
// Retrieval info: USED_PORT: q 0 0 48 0 OUTPUT NODEFVAL "q[47..0]"
|
||||
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
|
||||
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
|
||||
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
|
||||
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 48 0 data 0 0 48 0
|
||||
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
|
||||
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 48 0 @q 0 0 48 0
|
||||
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rxFIFO.inc FALSE
|
||||
|
|
|
|||
Plik binarny nie jest wyświetlany.
|
|
@ -1,2 +0,0 @@
|
|||
{ "Info" "IQEXE_TCL_SCRIPT_STATUS" "c:/intelfpga_lite/17.0/quartus/common/tcl/internal/ip_regen/ip_regen.tcl " "Evaluation of Tcl script c:/intelfpga_lite/17.0/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful" { } { } 0 23030 "Evaluation of Tcl script %1!s! was successful" 0 0 "Shell" 0 -1 1505482192099 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Shell 0 s 0 s Quartus Prime " "Quartus Prime Shell was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "742 " "Peak virtual memory: 742 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1505482192099 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 15:29:52 2017 " "Processing ended: Fri Sep 15 15:29:52 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1505482192099 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1505482192099 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1505482192099 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Shell" 0 -1 1505482192099 ""}
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
--a_graycounter DEVICE_FAMILY="Cyclone 10 LP" PVALUE=1 WIDTH=12 aclr clock cnt_en q
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources = reg 16
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "{-to counter3a0} POWER_UP_LEVEL=HIGH;{-to parity4} POWER_UP_LEVEL=HIGH";
|
||||
|
||||
SUBDESIGN a_graycounter_077
|
||||
(
|
||||
aclr : input;
|
||||
clock : input;
|
||||
cnt_en : input;
|
||||
q[11..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
counter3a0 : dffeas
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
counter3a1 : dffeas;
|
||||
counter3a2 : dffeas;
|
||||
counter3a3 : dffeas;
|
||||
counter3a4 : dffeas;
|
||||
counter3a5 : dffeas;
|
||||
counter3a6 : dffeas;
|
||||
counter3a7 : dffeas;
|
||||
counter3a8 : dffeas;
|
||||
counter3a9 : dffeas;
|
||||
counter3a10 : dffeas;
|
||||
counter3a11 : dffeas;
|
||||
parity4 : dffeas
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
sub_parity5a[2..0] : dffeas;
|
||||
cntr_cout[11..0] : WIRE;
|
||||
parity_cout : WIRE;
|
||||
sclr : NODE;
|
||||
updown : NODE;
|
||||
|
||||
BEGIN
|
||||
counter3a[11..0].clk = clock;
|
||||
counter3a[11..1].clrn = (! aclr);
|
||||
counter3a[11..0].d = ( (counter3a[11].q $ cntr_cout[10..10]), (counter3a[10].q $ (counter3a[9].q & cntr_cout[9..9])), (counter3a[9].q $ (counter3a[8].q & cntr_cout[8..8])), (counter3a[8].q $ (counter3a[7].q & cntr_cout[7..7])), (counter3a[7].q $ (counter3a[6].q & cntr_cout[6..6])), (counter3a[6].q $ (counter3a[5].q & cntr_cout[5..5])), (counter3a[5].q $ (counter3a[4].q & cntr_cout[4..4])), (counter3a[4].q $ (counter3a[3].q & cntr_cout[3..3])), (counter3a[3].q $ (counter3a[2].q & cntr_cout[2..2])), (counter3a[2].q $ (counter3a[1].q & cntr_cout[1..1])), (counter3a[1].q $ (counter3a[0].q & cntr_cout[0..0])), ((cnt_en & (counter3a[0].q $ (! parity_cout))) # ((! cnt_en) & counter3a[0].q)));
|
||||
counter3a[0].prn = (! aclr);
|
||||
counter3a[11..0].sclr = sclr;
|
||||
parity4.clk = clock;
|
||||
parity4.d = ((cnt_en & ((sub_parity5a[0..0].q $ sub_parity5a[1..1].q) $ sub_parity5a[2..2].q)) # ((! cnt_en) & parity4.q));
|
||||
parity4.prn = (! aclr);
|
||||
parity4.sclr = sclr;
|
||||
sub_parity5a[].clk = ( clock, clock, clock);
|
||||
sub_parity5a[].clrn = ( (! aclr), (! aclr), (! aclr));
|
||||
sub_parity5a[].d = ( ((cnt_en & (((counter3a[8..8].q $ counter3a[9..9].q) $ counter3a[10..10].q) $ counter3a[11..11].q)) # ((! cnt_en) & sub_parity5a[2].q)), ((cnt_en & (((counter3a[4..4].q $ counter3a[5..5].q) $ counter3a[6..6].q) $ counter3a[7..7].q)) # ((! cnt_en) & sub_parity5a[1].q)), ((cnt_en & (((counter3a[0..0].q $ counter3a[1..1].q) $ counter3a[2..2].q) $ counter3a[3..3].q)) # ((! cnt_en) & sub_parity5a[0].q)));
|
||||
sub_parity5a[].sclr = ( sclr, sclr, sclr);
|
||||
cntr_cout[] = ( B"0", (cntr_cout[9..9] & (! counter3a[9].q)), (cntr_cout[8..8] & (! counter3a[8].q)), (cntr_cout[7..7] & (! counter3a[7].q)), (cntr_cout[6..6] & (! counter3a[6].q)), (cntr_cout[5..5] & (! counter3a[5].q)), (cntr_cout[4..4] & (! counter3a[4].q)), (cntr_cout[3..3] & (! counter3a[3].q)), (cntr_cout[2..2] & (! counter3a[2].q)), (cntr_cout[1..1] & (! counter3a[1].q)), (cntr_cout[0..0] & (! counter3a[0].q)), (cnt_en & parity_cout));
|
||||
parity_cout = (((! parity4.q) $ updown) & cnt_en);
|
||||
q[] = counter3a[11..0].q;
|
||||
sclr = GND;
|
||||
updown = VCC;
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,70 +0,0 @@
|
|||
--a_graycounter DEVICE_FAMILY="Cyclone 10 LP" PVALUE=1 WIDTH=9 clock cnt_en q ALTERA_INTERNAL_OPTIONS=suppress_da_rule_internal=S102
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources = reg 13
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "suppress_da_rule_internal=S102;{-to counter8a0} POWER_UP_LEVEL=HIGH;{-to parity9} POWER_UP_LEVEL=HIGH";
|
||||
|
||||
SUBDESIGN a_graycounter_g5c
|
||||
(
|
||||
clock : input;
|
||||
cnt_en : input;
|
||||
q[8..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
counter8a0 : dffeas
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
counter8a1 : dffeas;
|
||||
counter8a2 : dffeas;
|
||||
counter8a3 : dffeas;
|
||||
counter8a4 : dffeas;
|
||||
counter8a5 : dffeas;
|
||||
counter8a6 : dffeas;
|
||||
counter8a7 : dffeas;
|
||||
counter8a8 : dffeas;
|
||||
parity9 : dffeas
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
sub_parity10a[2..0] : dffeas;
|
||||
cntr_cout[8..0] : WIRE;
|
||||
parity_cout : WIRE;
|
||||
sclr : NODE;
|
||||
updown : NODE;
|
||||
|
||||
BEGIN
|
||||
counter8a[8..0].clk = clock;
|
||||
counter8a[8..0].d = ( (counter8a[8].q $ cntr_cout[7..7]), (counter8a[7].q $ (counter8a[6].q & cntr_cout[6..6])), (counter8a[6].q $ (counter8a[5].q & cntr_cout[5..5])), (counter8a[5].q $ (counter8a[4].q & cntr_cout[4..4])), (counter8a[4].q $ (counter8a[3].q & cntr_cout[3..3])), (counter8a[3].q $ (counter8a[2].q & cntr_cout[2..2])), (counter8a[2].q $ (counter8a[1].q & cntr_cout[1..1])), (counter8a[1].q $ (counter8a[0].q & cntr_cout[0..0])), ((cnt_en & (counter8a[0].q $ (! parity_cout))) # ((! cnt_en) & counter8a[0].q)));
|
||||
counter8a[8..0].sclr = sclr;
|
||||
parity9.clk = clock;
|
||||
parity9.d = ((cnt_en & ((sub_parity10a[0..0].q $ sub_parity10a[1..1].q) $ sub_parity10a[2..2].q)) # ((! cnt_en) & parity9.q));
|
||||
parity9.sclr = sclr;
|
||||
sub_parity10a[].clk = ( clock, clock, clock);
|
||||
sub_parity10a[].d = ( ((cnt_en & counter8a[8..8].q) # ((! cnt_en) & sub_parity10a[2].q)), ((cnt_en & (((counter8a[4..4].q $ counter8a[5..5].q) $ counter8a[6..6].q) $ counter8a[7..7].q)) # ((! cnt_en) & sub_parity10a[1].q)), ((cnt_en & (((counter8a[0..0].q $ counter8a[1..1].q) $ counter8a[2..2].q) $ counter8a[3..3].q)) # ((! cnt_en) & sub_parity10a[0].q)));
|
||||
sub_parity10a[].sclr = ( sclr, sclr, sclr);
|
||||
cntr_cout[] = ( B"0", (cntr_cout[6..6] & (! counter8a[6].q)), (cntr_cout[5..5] & (! counter8a[5].q)), (cntr_cout[4..4] & (! counter8a[4].q)), (cntr_cout[3..3] & (! counter8a[3].q)), (cntr_cout[2..2] & (! counter8a[2].q)), (cntr_cout[1..1] & (! counter8a[1].q)), (cntr_cout[0..0] & (! counter8a[0].q)), (cnt_en & parity_cout));
|
||||
parity_cout = (((! parity9.q) $ updown) & cnt_en);
|
||||
q[] = counter8a[8..0].q;
|
||||
sclr = GND;
|
||||
updown = VCC;
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
--a_graycounter DEVICE_FAMILY="Cyclone 10 LP" PVALUE=1 WIDTH=9 aclr clock cnt_en q ALTERA_INTERNAL_OPTIONS=suppress_da_rule_internal=S102
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources = reg 13
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "suppress_da_rule_internal=S102;{-to counter6a0} POWER_UP_LEVEL=HIGH;{-to parity7} POWER_UP_LEVEL=HIGH";
|
||||
|
||||
SUBDESIGN a_graycounter_ijc
|
||||
(
|
||||
aclr : input;
|
||||
clock : input;
|
||||
cnt_en : input;
|
||||
q[8..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
counter6a0 : dffeas
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
counter6a1 : dffeas;
|
||||
counter6a2 : dffeas;
|
||||
counter6a3 : dffeas;
|
||||
counter6a4 : dffeas;
|
||||
counter6a5 : dffeas;
|
||||
counter6a6 : dffeas;
|
||||
counter6a7 : dffeas;
|
||||
counter6a8 : dffeas;
|
||||
parity7 : dffeas
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
sub_parity8a[2..0] : dffeas;
|
||||
cntr_cout[8..0] : WIRE;
|
||||
parity_cout : WIRE;
|
||||
sclr : NODE;
|
||||
updown : NODE;
|
||||
|
||||
BEGIN
|
||||
counter6a[8..0].clk = clock;
|
||||
counter6a[8..1].clrn = (! aclr);
|
||||
counter6a[8..0].d = ( (counter6a[8].q $ cntr_cout[7..7]), (counter6a[7].q $ (counter6a[6].q & cntr_cout[6..6])), (counter6a[6].q $ (counter6a[5].q & cntr_cout[5..5])), (counter6a[5].q $ (counter6a[4].q & cntr_cout[4..4])), (counter6a[4].q $ (counter6a[3].q & cntr_cout[3..3])), (counter6a[3].q $ (counter6a[2].q & cntr_cout[2..2])), (counter6a[2].q $ (counter6a[1].q & cntr_cout[1..1])), (counter6a[1].q $ (counter6a[0].q & cntr_cout[0..0])), ((cnt_en & (counter6a[0].q $ (! parity_cout))) # ((! cnt_en) & counter6a[0].q)));
|
||||
counter6a[0].prn = (! aclr);
|
||||
counter6a[8..0].sclr = sclr;
|
||||
parity7.clk = clock;
|
||||
parity7.d = ((cnt_en & ((sub_parity8a[0..0].q $ sub_parity8a[1..1].q) $ sub_parity8a[2..2].q)) # ((! cnt_en) & parity7.q));
|
||||
parity7.prn = (! aclr);
|
||||
parity7.sclr = sclr;
|
||||
sub_parity8a[].clk = ( clock, clock, clock);
|
||||
sub_parity8a[].clrn = ( (! aclr), (! aclr), (! aclr));
|
||||
sub_parity8a[].d = ( ((cnt_en & counter6a[8..8].q) # ((! cnt_en) & sub_parity8a[2].q)), ((cnt_en & (((counter6a[4..4].q $ counter6a[5..5].q) $ counter6a[6..6].q) $ counter6a[7..7].q)) # ((! cnt_en) & sub_parity8a[1].q)), ((cnt_en & (((counter6a[0..0].q $ counter6a[1..1].q) $ counter6a[2..2].q) $ counter6a[3..3].q)) # ((! cnt_en) & sub_parity8a[0].q)));
|
||||
sub_parity8a[].sclr = ( sclr, sclr, sclr);
|
||||
cntr_cout[] = ( B"0", (cntr_cout[6..6] & (! counter6a[6].q)), (cntr_cout[5..5] & (! counter6a[5].q)), (cntr_cout[4..4] & (! counter6a[4].q)), (cntr_cout[3..3] & (! counter6a[3].q)), (cntr_cout[2..2] & (! counter6a[2].q)), (cntr_cout[1..1] & (! counter6a[1].q)), (cntr_cout[0..0] & (! counter6a[0].q)), (cnt_en & parity_cout));
|
||||
parity_cout = (((! parity7.q) $ updown) & cnt_en);
|
||||
q[] = counter6a[8..0].q;
|
||||
sclr = GND;
|
||||
updown = VCC;
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,70 +0,0 @@
|
|||
--a_graycounter DEVICE_FAMILY="Cyclone 10 LP" PVALUE=1 WIDTH=9 clock cnt_en q
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources = reg 13
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "{-to counter5a0} POWER_UP_LEVEL=HIGH;{-to parity6} POWER_UP_LEVEL=HIGH";
|
||||
|
||||
SUBDESIGN a_graycounter_kn6
|
||||
(
|
||||
clock : input;
|
||||
cnt_en : input;
|
||||
q[8..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
counter5a0 : dffeas
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
counter5a1 : dffeas;
|
||||
counter5a2 : dffeas;
|
||||
counter5a3 : dffeas;
|
||||
counter5a4 : dffeas;
|
||||
counter5a5 : dffeas;
|
||||
counter5a6 : dffeas;
|
||||
counter5a7 : dffeas;
|
||||
counter5a8 : dffeas;
|
||||
parity6 : dffeas
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
sub_parity7a[2..0] : dffeas;
|
||||
cntr_cout[8..0] : WIRE;
|
||||
parity_cout : WIRE;
|
||||
sclr : NODE;
|
||||
updown : NODE;
|
||||
|
||||
BEGIN
|
||||
counter5a[8..0].clk = clock;
|
||||
counter5a[8..0].d = ( (counter5a[8].q $ cntr_cout[7..7]), (counter5a[7].q $ (counter5a[6].q & cntr_cout[6..6])), (counter5a[6].q $ (counter5a[5].q & cntr_cout[5..5])), (counter5a[5].q $ (counter5a[4].q & cntr_cout[4..4])), (counter5a[4].q $ (counter5a[3].q & cntr_cout[3..3])), (counter5a[3].q $ (counter5a[2].q & cntr_cout[2..2])), (counter5a[2].q $ (counter5a[1].q & cntr_cout[1..1])), (counter5a[1].q $ (counter5a[0].q & cntr_cout[0..0])), ((cnt_en & (counter5a[0].q $ (! parity_cout))) # ((! cnt_en) & counter5a[0].q)));
|
||||
counter5a[8..0].sclr = sclr;
|
||||
parity6.clk = clock;
|
||||
parity6.d = ((cnt_en & ((sub_parity7a[0..0].q $ sub_parity7a[1..1].q) $ sub_parity7a[2..2].q)) # ((! cnt_en) & parity6.q));
|
||||
parity6.sclr = sclr;
|
||||
sub_parity7a[].clk = ( clock, clock, clock);
|
||||
sub_parity7a[].d = ( ((cnt_en & counter5a[8..8].q) # ((! cnt_en) & sub_parity7a[2].q)), ((cnt_en & (((counter5a[4..4].q $ counter5a[5..5].q) $ counter5a[6..6].q) $ counter5a[7..7].q)) # ((! cnt_en) & sub_parity7a[1].q)), ((cnt_en & (((counter5a[0..0].q $ counter5a[1..1].q) $ counter5a[2..2].q) $ counter5a[3..3].q)) # ((! cnt_en) & sub_parity7a[0].q)));
|
||||
sub_parity7a[].sclr = ( sclr, sclr, sclr);
|
||||
cntr_cout[] = ( B"0", (cntr_cout[6..6] & (! counter5a[6].q)), (cntr_cout[5..5] & (! counter5a[5].q)), (cntr_cout[4..4] & (! counter5a[4].q)), (cntr_cout[3..3] & (! counter5a[3].q)), (cntr_cout[2..2] & (! counter5a[2].q)), (cntr_cout[1..1] & (! counter5a[1].q)), (cntr_cout[0..0] & (! counter5a[0].q)), (cnt_en & parity_cout));
|
||||
parity_cout = (((! parity6.q) $ updown) & cnt_en);
|
||||
q[] = counter5a[8..0].q;
|
||||
sclr = GND;
|
||||
updown = VCC;
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
--a_graycounter DEVICE_FAMILY="Cyclone 10 LP" PVALUE=1 WIDTH=9 aclr clock cnt_en q
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources = reg 13
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "{-to counter3a0} POWER_UP_LEVEL=HIGH;{-to parity4} POWER_UP_LEVEL=HIGH";
|
||||
|
||||
SUBDESIGN a_graycounter_m57
|
||||
(
|
||||
aclr : input;
|
||||
clock : input;
|
||||
cnt_en : input;
|
||||
q[8..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
counter3a0 : dffeas
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
counter3a1 : dffeas;
|
||||
counter3a2 : dffeas;
|
||||
counter3a3 : dffeas;
|
||||
counter3a4 : dffeas;
|
||||
counter3a5 : dffeas;
|
||||
counter3a6 : dffeas;
|
||||
counter3a7 : dffeas;
|
||||
counter3a8 : dffeas;
|
||||
parity4 : dffeas
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
sub_parity5a[2..0] : dffeas;
|
||||
cntr_cout[8..0] : WIRE;
|
||||
parity_cout : WIRE;
|
||||
sclr : NODE;
|
||||
updown : NODE;
|
||||
|
||||
BEGIN
|
||||
counter3a[8..0].clk = clock;
|
||||
counter3a[8..1].clrn = (! aclr);
|
||||
counter3a[8..0].d = ( (counter3a[8].q $ cntr_cout[7..7]), (counter3a[7].q $ (counter3a[6].q & cntr_cout[6..6])), (counter3a[6].q $ (counter3a[5].q & cntr_cout[5..5])), (counter3a[5].q $ (counter3a[4].q & cntr_cout[4..4])), (counter3a[4].q $ (counter3a[3].q & cntr_cout[3..3])), (counter3a[3].q $ (counter3a[2].q & cntr_cout[2..2])), (counter3a[2].q $ (counter3a[1].q & cntr_cout[1..1])), (counter3a[1].q $ (counter3a[0].q & cntr_cout[0..0])), ((cnt_en & (counter3a[0].q $ (! parity_cout))) # ((! cnt_en) & counter3a[0].q)));
|
||||
counter3a[0].prn = (! aclr);
|
||||
counter3a[8..0].sclr = sclr;
|
||||
parity4.clk = clock;
|
||||
parity4.d = ((cnt_en & ((sub_parity5a[0..0].q $ sub_parity5a[1..1].q) $ sub_parity5a[2..2].q)) # ((! cnt_en) & parity4.q));
|
||||
parity4.prn = (! aclr);
|
||||
parity4.sclr = sclr;
|
||||
sub_parity5a[].clk = ( clock, clock, clock);
|
||||
sub_parity5a[].clrn = ( (! aclr), (! aclr), (! aclr));
|
||||
sub_parity5a[].d = ( ((cnt_en & counter3a[8..8].q) # ((! cnt_en) & sub_parity5a[2].q)), ((cnt_en & (((counter3a[4..4].q $ counter3a[5..5].q) $ counter3a[6..6].q) $ counter3a[7..7].q)) # ((! cnt_en) & sub_parity5a[1].q)), ((cnt_en & (((counter3a[0..0].q $ counter3a[1..1].q) $ counter3a[2..2].q) $ counter3a[3..3].q)) # ((! cnt_en) & sub_parity5a[0].q)));
|
||||
sub_parity5a[].sclr = ( sclr, sclr, sclr);
|
||||
cntr_cout[] = ( B"0", (cntr_cout[6..6] & (! counter3a[6].q)), (cntr_cout[5..5] & (! counter3a[5].q)), (cntr_cout[4..4] & (! counter3a[4].q)), (cntr_cout[3..3] & (! counter3a[3].q)), (cntr_cout[2..2] & (! counter3a[2].q)), (cntr_cout[1..1] & (! counter3a[1].q)), (cntr_cout[0..0] & (! counter3a[0].q)), (cnt_en & parity_cout));
|
||||
parity_cout = (((! parity4.q) $ updown) & cnt_en);
|
||||
q[] = counter3a[8..0].q;
|
||||
sclr = GND;
|
||||
updown = VCC;
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
--a_graycounter DEVICE_FAMILY="Cyclone 10 LP" PVALUE=1 WIDTH=12 aclr clock cnt_en q ALTERA_INTERNAL_OPTIONS=suppress_da_rule_internal=S102
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources = reg 16
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "suppress_da_rule_internal=S102;{-to counter6a0} POWER_UP_LEVEL=HIGH;{-to parity7} POWER_UP_LEVEL=HIGH";
|
||||
|
||||
SUBDESIGN a_graycounter_skc
|
||||
(
|
||||
aclr : input;
|
||||
clock : input;
|
||||
cnt_en : input;
|
||||
q[11..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
counter6a0 : dffeas
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
counter6a1 : dffeas;
|
||||
counter6a2 : dffeas;
|
||||
counter6a3 : dffeas;
|
||||
counter6a4 : dffeas;
|
||||
counter6a5 : dffeas;
|
||||
counter6a6 : dffeas;
|
||||
counter6a7 : dffeas;
|
||||
counter6a8 : dffeas;
|
||||
counter6a9 : dffeas;
|
||||
counter6a10 : dffeas;
|
||||
counter6a11 : dffeas;
|
||||
parity7 : dffeas
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
sub_parity8a[2..0] : dffeas;
|
||||
cntr_cout[11..0] : WIRE;
|
||||
parity_cout : WIRE;
|
||||
sclr : NODE;
|
||||
updown : NODE;
|
||||
|
||||
BEGIN
|
||||
counter6a[11..0].clk = clock;
|
||||
counter6a[11..1].clrn = (! aclr);
|
||||
counter6a[11..0].d = ( (counter6a[11].q $ cntr_cout[10..10]), (counter6a[10].q $ (counter6a[9].q & cntr_cout[9..9])), (counter6a[9].q $ (counter6a[8].q & cntr_cout[8..8])), (counter6a[8].q $ (counter6a[7].q & cntr_cout[7..7])), (counter6a[7].q $ (counter6a[6].q & cntr_cout[6..6])), (counter6a[6].q $ (counter6a[5].q & cntr_cout[5..5])), (counter6a[5].q $ (counter6a[4].q & cntr_cout[4..4])), (counter6a[4].q $ (counter6a[3].q & cntr_cout[3..3])), (counter6a[3].q $ (counter6a[2].q & cntr_cout[2..2])), (counter6a[2].q $ (counter6a[1].q & cntr_cout[1..1])), (counter6a[1].q $ (counter6a[0].q & cntr_cout[0..0])), ((cnt_en & (counter6a[0].q $ (! parity_cout))) # ((! cnt_en) & counter6a[0].q)));
|
||||
counter6a[0].prn = (! aclr);
|
||||
counter6a[11..0].sclr = sclr;
|
||||
parity7.clk = clock;
|
||||
parity7.d = ((cnt_en & ((sub_parity8a[0..0].q $ sub_parity8a[1..1].q) $ sub_parity8a[2..2].q)) # ((! cnt_en) & parity7.q));
|
||||
parity7.prn = (! aclr);
|
||||
parity7.sclr = sclr;
|
||||
sub_parity8a[].clk = ( clock, clock, clock);
|
||||
sub_parity8a[].clrn = ( (! aclr), (! aclr), (! aclr));
|
||||
sub_parity8a[].d = ( ((cnt_en & (((counter6a[8..8].q $ counter6a[9..9].q) $ counter6a[10..10].q) $ counter6a[11..11].q)) # ((! cnt_en) & sub_parity8a[2].q)), ((cnt_en & (((counter6a[4..4].q $ counter6a[5..5].q) $ counter6a[6..6].q) $ counter6a[7..7].q)) # ((! cnt_en) & sub_parity8a[1].q)), ((cnt_en & (((counter6a[0..0].q $ counter6a[1..1].q) $ counter6a[2..2].q) $ counter6a[3..3].q)) # ((! cnt_en) & sub_parity8a[0].q)));
|
||||
sub_parity8a[].sclr = ( sclr, sclr, sclr);
|
||||
cntr_cout[] = ( B"0", (cntr_cout[9..9] & (! counter6a[9].q)), (cntr_cout[8..8] & (! counter6a[8].q)), (cntr_cout[7..7] & (! counter6a[7].q)), (cntr_cout[6..6] & (! counter6a[6].q)), (cntr_cout[5..5] & (! counter6a[5].q)), (cntr_cout[4..4] & (! counter6a[4].q)), (cntr_cout[3..3] & (! counter6a[3].q)), (cntr_cout[2..2] & (! counter6a[2].q)), (cntr_cout[1..1] & (! counter6a[1].q)), (cntr_cout[0..0] & (! counter6a[0].q)), (cnt_en & parity_cout));
|
||||
parity_cout = (((! parity7.q) $ updown) & cnt_en);
|
||||
q[] = counter6a[11..0].q;
|
||||
sclr = GND;
|
||||
updown = VCC;
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
--dffpipe DELAY=2 WIDTH=9 clock clrn d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_altdpram 2017:04:25:18:06:29:SJ cbx_altera_counter 2017:04:25:18:06:29:SJ cbx_altera_gray_counter 2017:04:25:18:06:29:SJ cbx_altera_syncram 2017:04:25:18:06:29:SJ cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_dcfifo 2017:04:25:18:06:29:SJ cbx_fifo_common 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_counter 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_scfifo 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION dffpipe_hd9 (clock, clrn, d[8..0])
|
||||
RETURNS ( q[8..0]);
|
||||
|
||||
--synthesis_resources = reg 18
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW";
|
||||
|
||||
SUBDESIGN alt_synch_pipe_0ol
|
||||
(
|
||||
clock : input;
|
||||
clrn : input;
|
||||
d[8..0] : input;
|
||||
q[8..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
dffpipe10 : dffpipe_hd9;
|
||||
|
||||
BEGIN
|
||||
dffpipe10.clock = clock;
|
||||
dffpipe10.clrn = clrn;
|
||||
dffpipe10.d[] = d[];
|
||||
q[] = dffpipe10.q[];
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
--dffpipe DELAY=2 WIDTH=12 clock clrn d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_altdpram 2017:04:25:18:06:29:SJ cbx_altera_counter 2017:04:25:18:06:29:SJ cbx_altera_gray_counter 2017:04:25:18:06:29:SJ cbx_altera_syncram 2017:04:25:18:06:29:SJ cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_dcfifo 2017:04:25:18:06:29:SJ cbx_fifo_common 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_counter 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_scfifo 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION dffpipe_re9 (clock, clrn, d[11..0])
|
||||
RETURNS ( q[11..0]);
|
||||
|
||||
--synthesis_resources = reg 24
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW";
|
||||
|
||||
SUBDESIGN alt_synch_pipe_apl
|
||||
(
|
||||
clock : input;
|
||||
clrn : input;
|
||||
d[11..0] : input;
|
||||
q[11..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
dffpipe10 : dffpipe_re9;
|
||||
|
||||
BEGIN
|
||||
dffpipe10.clock = clock;
|
||||
dffpipe10.clrn = clrn;
|
||||
dffpipe10.d[] = d[];
|
||||
q[] = dffpipe10.q[];
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
--dffpipe DELAY=2 WIDTH=12 clock clrn d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_altdpram 2017:04:25:18:06:29:SJ cbx_altera_counter 2017:04:25:18:06:29:SJ cbx_altera_gray_counter 2017:04:25:18:06:29:SJ cbx_altera_syncram 2017:04:25:18:06:29:SJ cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_dcfifo 2017:04:25:18:06:29:SJ cbx_fifo_common 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_counter 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_scfifo 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION dffpipe_se9 (clock, clrn, d[11..0])
|
||||
RETURNS ( q[11..0]);
|
||||
|
||||
--synthesis_resources = reg 24
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW";
|
||||
|
||||
SUBDESIGN alt_synch_pipe_bpl
|
||||
(
|
||||
clock : input;
|
||||
clrn : input;
|
||||
d[11..0] : input;
|
||||
q[11..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
dffpipe3 : dffpipe_se9;
|
||||
|
||||
BEGIN
|
||||
dffpipe3.clock = clock;
|
||||
dffpipe3.clrn = clrn;
|
||||
dffpipe3.d[] = d[];
|
||||
q[] = dffpipe3.q[];
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
--dffpipe DELAY=2 WIDTH=9 clock d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_altdpram 2017:04:25:18:06:29:SJ cbx_altera_counter 2017:04:25:18:06:29:SJ cbx_altera_gray_counter 2017:04:25:18:06:29:SJ cbx_altera_syncram 2017:04:25:18:06:29:SJ cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_dcfifo 2017:04:25:18:06:29:SJ cbx_fifo_common 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_counter 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_scfifo 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION dffpipe_2v8 (clock, d[8..0])
|
||||
RETURNS ( q[8..0]);
|
||||
|
||||
--synthesis_resources = reg 18
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW";
|
||||
|
||||
SUBDESIGN alt_synch_pipe_h9l
|
||||
(
|
||||
clock : input;
|
||||
d[8..0] : input;
|
||||
q[8..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
dffpipe12 : dffpipe_2v8;
|
||||
|
||||
BEGIN
|
||||
dffpipe12.clock = clock;
|
||||
dffpipe12.d[] = d[];
|
||||
q[] = dffpipe12.q[];
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
--dffpipe DELAY=2 WIDTH=9 clock d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_altdpram 2017:04:25:18:06:29:SJ cbx_altera_counter 2017:04:25:18:06:29:SJ cbx_altera_gray_counter 2017:04:25:18:06:29:SJ cbx_altera_syncram 2017:04:25:18:06:29:SJ cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_dcfifo 2017:04:25:18:06:29:SJ cbx_fifo_common 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_counter 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_scfifo 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION dffpipe_3v8 (clock, d[8..0])
|
||||
RETURNS ( q[8..0]);
|
||||
|
||||
--synthesis_resources = reg 18
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW";
|
||||
|
||||
SUBDESIGN alt_synch_pipe_i9l
|
||||
(
|
||||
clock : input;
|
||||
d[8..0] : input;
|
||||
q[8..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
dffpipe15 : dffpipe_3v8;
|
||||
|
||||
BEGIN
|
||||
dffpipe15.clock = clock;
|
||||
dffpipe15.d[] = d[];
|
||||
q[] = dffpipe15.q[];
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
--dffpipe DELAY=2 WIDTH=9 clock d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_altdpram 2017:04:25:18:06:29:SJ cbx_altera_counter 2017:04:25:18:06:29:SJ cbx_altera_gray_counter 2017:04:25:18:06:29:SJ cbx_altera_syncram 2017:04:25:18:06:29:SJ cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_dcfifo 2017:04:25:18:06:29:SJ cbx_fifo_common 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_counter 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_scfifo 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION dffpipe_4v8 (clock, d[8..0])
|
||||
RETURNS ( q[8..0]);
|
||||
|
||||
--synthesis_resources = reg 18
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;PRESERVE_REGISTER=ON;DONT_MERGE_REGISTER=ON;ADV_NETLIST_OPT_ALLOWED=NEVER_ALLOW";
|
||||
|
||||
SUBDESIGN alt_synch_pipe_j9l
|
||||
(
|
||||
clock : input;
|
||||
d[8..0] : input;
|
||||
q[8..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
dffpipe3 : dffpipe_4v8;
|
||||
|
||||
BEGIN
|
||||
dffpipe3.clock = clock;
|
||||
dffpipe3.d[] = d[];
|
||||
q[] = dffpipe3.q[];
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,440 +0,0 @@
|
|||
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone 10 LP" ENABLE_RUNTIME_MOD="NO" INIT_FILE="./Polyphase_FIR/coefI8_1024.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=18 WIDTH_BYTEENA_A=1 WIDTHAD_A=10 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cyclone10lp_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
|
||||
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
|
||||
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
|
||||
|
||||
--synthesis_resources = M9K 2
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
|
||||
|
||||
SUBDESIGN altsyncram_23b1
|
||||
(
|
||||
address_a[9..0] : input;
|
||||
clock0 : input;
|
||||
q_a[17..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
ram_block1a0 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 0,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a1 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 1,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a2 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 2,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a3 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 3,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a4 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 4,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a5 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 5,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a6 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 6,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a7 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 7,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a8 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 8,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a9 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 9,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a10 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 10,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a11 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 11,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a12 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 12,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a13 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 13,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a14 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 14,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a15 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 15,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a16 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 16,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a17 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 17,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
address_a_wire[9..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
ram_block1a[17..0].clk0 = clock0;
|
||||
ram_block1a[17..0].portaaddr[] = ( address_a_wire[9..0]);
|
||||
ram_block1a[17..0].portare = B"111111111111111111";
|
||||
address_a_wire[] = address_a[];
|
||||
q_a[] = ( ram_block1a[17..0].portadataout[0..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,440 +0,0 @@
|
|||
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone 10 LP" ENABLE_RUNTIME_MOD="NO" INIT_FILE="./rtl/Polyphase_FIR/coefI8_1024.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=18 WIDTH_BYTEENA_A=1 WIDTHAD_A=10 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cyclone10lp_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
|
||||
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
|
||||
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
|
||||
|
||||
--synthesis_resources = M9K 2
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
|
||||
|
||||
SUBDESIGN altsyncram_3fb1
|
||||
(
|
||||
address_a[9..0] : input;
|
||||
clock0 : input;
|
||||
q_a[17..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
ram_block1a0 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 0,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a1 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 1,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a2 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 2,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a3 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 3,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a4 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 4,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a5 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 5,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a6 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 6,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a7 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 7,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a8 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 8,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a9 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 9,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a10 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 10,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a11 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 11,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a12 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 12,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a13 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 13,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a14 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 14,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a15 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 15,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a16 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 16,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a17 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "./rtl/Polyphase_FIR/coefI8_1024.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 10,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 17,
|
||||
PORT_A_LAST_ADDRESS = 1023,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 1024,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
address_a_wire[9..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
ram_block1a[17..0].clk0 = clock0;
|
||||
ram_block1a[17..0].portaaddr[] = ( address_a_wire[9..0]);
|
||||
ram_block1a[17..0].portare = B"111111111111111111";
|
||||
address_a_wire[] = address_a[];
|
||||
q_a[] = ( ram_block1a[17..0].portadataout[0..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,440 +0,0 @@
|
|||
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone 10 LP" ENABLE_RUNTIME_MOD="NO" INIT_FILE="coefL8A.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=18 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cyclone10lp_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
|
||||
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
|
||||
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
|
||||
|
||||
--synthesis_resources = M9K 1
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
|
||||
|
||||
SUBDESIGN altsyncram_ca91
|
||||
(
|
||||
address_a[7..0] : input;
|
||||
clock0 : input;
|
||||
q_a[17..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
ram_block1a0 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 0,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a1 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 1,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a2 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 2,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a3 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 3,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a4 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 4,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a5 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 5,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a6 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 6,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a7 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 7,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a8 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 8,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a9 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 9,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a10 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 10,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a11 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 11,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a12 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 12,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a13 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 13,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a14 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 14,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a15 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 15,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a16 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 16,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a17 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8A.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 17,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
address_a_wire[7..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
ram_block1a[17..0].clk0 = clock0;
|
||||
ram_block1a[17..0].portaaddr[] = ( address_a_wire[7..0]);
|
||||
ram_block1a[17..0].portare = B"111111111111111111";
|
||||
address_a_wire[] = address_a[];
|
||||
q_a[] = ( ram_block1a[17..0].portadataout[0..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,440 +0,0 @@
|
|||
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone 10 LP" ENABLE_RUNTIME_MOD="NO" INIT_FILE="coefL8B.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=18 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cyclone10lp_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
|
||||
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
|
||||
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
|
||||
|
||||
--synthesis_resources = M9K 1
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
|
||||
|
||||
SUBDESIGN altsyncram_da91
|
||||
(
|
||||
address_a[7..0] : input;
|
||||
clock0 : input;
|
||||
q_a[17..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
ram_block1a0 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 0,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a1 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 1,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a2 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 2,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a3 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 3,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a4 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 4,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a5 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 5,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a6 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 6,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a7 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 7,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a8 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 8,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a9 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 9,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a10 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 10,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a11 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 11,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a12 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 12,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a13 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 13,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a14 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 14,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a15 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 15,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a16 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 16,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a17 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8B.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 17,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
address_a_wire[7..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
ram_block1a[17..0].clk0 = clock0;
|
||||
ram_block1a[17..0].portaaddr[] = ( address_a_wire[7..0]);
|
||||
ram_block1a[17..0].portare = B"111111111111111111";
|
||||
address_a_wire[] = address_a[];
|
||||
q_a[] = ( ram_block1a[17..0].portadataout[0..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,440 +0,0 @@
|
|||
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone 10 LP" ENABLE_RUNTIME_MOD="NO" INIT_FILE="coefL8C.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=18 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cyclone10lp_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
|
||||
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
|
||||
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
|
||||
|
||||
--synthesis_resources = M9K 1
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
|
||||
|
||||
SUBDESIGN altsyncram_ea91
|
||||
(
|
||||
address_a[7..0] : input;
|
||||
clock0 : input;
|
||||
q_a[17..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
ram_block1a0 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 0,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a1 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 1,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a2 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 2,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a3 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 3,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a4 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 4,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a5 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 5,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a6 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 6,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a7 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 7,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a8 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 8,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a9 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 9,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a10 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 10,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a11 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 11,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a12 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 12,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a13 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 13,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a14 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 14,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a15 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 15,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a16 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 16,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a17 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8C.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 17,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
address_a_wire[7..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
ram_block1a[17..0].clk0 = clock0;
|
||||
ram_block1a[17..0].portaaddr[] = ( address_a_wire[7..0]);
|
||||
ram_block1a[17..0].portare = B"111111111111111111";
|
||||
address_a_wire[] = address_a[];
|
||||
q_a[] = ( ram_block1a[17..0].portadataout[0..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,440 +0,0 @@
|
|||
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone 10 LP" ENABLE_RUNTIME_MOD="NO" INIT_FILE="coefL8D.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=18 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cyclone10lp_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
|
||||
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
|
||||
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
|
||||
|
||||
--synthesis_resources = M9K 1
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
|
||||
|
||||
SUBDESIGN altsyncram_fa91
|
||||
(
|
||||
address_a[7..0] : input;
|
||||
clock0 : input;
|
||||
q_a[17..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
ram_block1a0 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 0,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a1 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 1,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a2 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 2,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a3 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 3,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a4 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 4,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a5 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 5,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a6 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 6,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a7 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 7,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a8 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 8,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a9 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 9,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a10 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 10,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a11 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 11,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a12 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 12,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a13 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 13,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a14 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 14,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a15 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 15,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a16 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 16,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a17 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8D.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 17,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
address_a_wire[7..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
ram_block1a[17..0].clk0 = clock0;
|
||||
ram_block1a[17..0].portaaddr[] = ( address_a_wire[7..0]);
|
||||
ram_block1a[17..0].portare = B"111111111111111111";
|
||||
address_a_wire[] = address_a[];
|
||||
q_a[] = ( ram_block1a[17..0].portadataout[0..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,440 +0,0 @@
|
|||
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone 10 LP" ENABLE_RUNTIME_MOD="NO" INIT_FILE="coefL8E.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=18 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cyclone10lp_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
|
||||
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
|
||||
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
|
||||
|
||||
--synthesis_resources = M9K 1
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
|
||||
|
||||
SUBDESIGN altsyncram_ga91
|
||||
(
|
||||
address_a[7..0] : input;
|
||||
clock0 : input;
|
||||
q_a[17..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
ram_block1a0 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 0,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a1 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 1,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a2 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 2,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a3 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 3,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a4 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 4,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a5 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 5,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a6 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 6,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a7 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 7,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a8 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 8,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a9 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 9,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a10 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 10,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a11 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 11,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a12 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 12,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a13 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 13,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a14 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 14,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a15 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 15,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a16 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 16,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a17 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8E.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 17,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
address_a_wire[7..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
ram_block1a[17..0].clk0 = clock0;
|
||||
ram_block1a[17..0].portaaddr[] = ( address_a_wire[7..0]);
|
||||
ram_block1a[17..0].portare = B"111111111111111111";
|
||||
address_a_wire[] = address_a[];
|
||||
q_a[] = ( ram_block1a[17..0].portadataout[0..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,440 +0,0 @@
|
|||
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone 10 LP" ENABLE_RUNTIME_MOD="NO" INIT_FILE="coefL8F.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=18 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cyclone10lp_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
|
||||
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
|
||||
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
|
||||
|
||||
--synthesis_resources = M9K 1
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
|
||||
|
||||
SUBDESIGN altsyncram_ha91
|
||||
(
|
||||
address_a[7..0] : input;
|
||||
clock0 : input;
|
||||
q_a[17..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
ram_block1a0 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 0,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a1 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 1,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a2 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 2,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a3 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 3,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a4 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 4,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a5 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 5,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a6 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 6,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a7 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 7,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a8 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 8,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a9 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 9,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a10 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 10,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a11 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 11,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a12 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 12,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a13 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 13,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a14 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 14,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a15 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 15,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a16 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 16,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a17 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8F.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 17,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
address_a_wire[7..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
ram_block1a[17..0].clk0 = clock0;
|
||||
ram_block1a[17..0].portaaddr[] = ( address_a_wire[7..0]);
|
||||
ram_block1a[17..0].portare = B"111111111111111111";
|
||||
address_a_wire[] = address_a[];
|
||||
q_a[] = ( ram_block1a[17..0].portadataout[0..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,324 +0,0 @@
|
|||
--altsyncram ADDRESS_ACLR_B="CLEAR1" ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone 10 LP" ENABLE_ECC="FALSE" LOW_POWER_MODE="AUTO" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="CLEAR1" OUTDATA_REG_B="CLOCK1" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_ECCSTATUS=2 WIDTHAD_A=8 WIDTHAD_B=8 aclr1 address_a address_b addressstall_b clock0 clock1 clocken1 data_a q_b wren_a
|
||||
--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cyclone10lp_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
|
||||
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
|
||||
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
|
||||
|
||||
--synthesis_resources = M9K 1
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
|
||||
|
||||
SUBDESIGN altsyncram_hs61
|
||||
(
|
||||
aclr1 : input;
|
||||
address_a[7..0] : input;
|
||||
address_b[7..0] : input;
|
||||
addressstall_b : input;
|
||||
clock0 : input;
|
||||
clock1 : input;
|
||||
clocken1 : input;
|
||||
data_a[7..0] : input;
|
||||
q_b[7..0] : output;
|
||||
wren_a : input;
|
||||
)
|
||||
VARIABLE
|
||||
ram_block9a0 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 0,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "clear1",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "clear1",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 0,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block9a1 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 1,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "clear1",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "clear1",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 1,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block9a2 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 2,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "clear1",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "clear1",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 2,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block9a3 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 3,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "clear1",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "clear1",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 3,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block9a4 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 4,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "clear1",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "clear1",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 4,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block9a5 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 5,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "clear1",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "clear1",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 5,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block9a6 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 6,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "clear1",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "clear1",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 6,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block9a7 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 7,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "clear1",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "clear1",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 7,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
address_a_wire[7..0] : WIRE;
|
||||
address_b_wire[7..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
ram_block9a[7..0].clk0 = clock0;
|
||||
ram_block9a[7..0].clk1 = clock1;
|
||||
ram_block9a[7..0].clr1 = aclr1;
|
||||
ram_block9a[7..0].ena0 = wren_a;
|
||||
ram_block9a[7..0].ena1 = clocken1;
|
||||
ram_block9a[7..0].portaaddr[] = ( address_a_wire[7..0]);
|
||||
ram_block9a[0].portadatain[] = ( data_a[0..0]);
|
||||
ram_block9a[1].portadatain[] = ( data_a[1..1]);
|
||||
ram_block9a[2].portadatain[] = ( data_a[2..2]);
|
||||
ram_block9a[3].portadatain[] = ( data_a[3..3]);
|
||||
ram_block9a[4].portadatain[] = ( data_a[4..4]);
|
||||
ram_block9a[5].portadatain[] = ( data_a[5..5]);
|
||||
ram_block9a[6].portadatain[] = ( data_a[6..6]);
|
||||
ram_block9a[7].portadatain[] = ( data_a[7..7]);
|
||||
ram_block9a[7..0].portawe = wren_a;
|
||||
ram_block9a[7..0].portbaddr[] = ( address_b_wire[7..0]);
|
||||
ram_block9a[7..0].portbaddrstall = addressstall_b;
|
||||
ram_block9a[7..0].portbre = B"11111111";
|
||||
address_a_wire[] = address_a[];
|
||||
address_b_wire[] = address_b[];
|
||||
q_b[] = ( ram_block9a[7..0].portbdataout[0..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,440 +0,0 @@
|
|||
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone 10 LP" ENABLE_RUNTIME_MOD="NO" INIT_FILE="coefL8G.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=18 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cyclone10lp_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
|
||||
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
|
||||
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
|
||||
|
||||
--synthesis_resources = M9K 1
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
|
||||
|
||||
SUBDESIGN altsyncram_ia91
|
||||
(
|
||||
address_a[7..0] : input;
|
||||
clock0 : input;
|
||||
q_a[17..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
ram_block1a0 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 0,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a1 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 1,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a2 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 2,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a3 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 3,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a4 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 4,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a5 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 5,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a6 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 6,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a7 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 7,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a8 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 8,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a9 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 9,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a10 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 10,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a11 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 11,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a12 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 12,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a13 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 13,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a14 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 14,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a15 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 15,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a16 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 16,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a17 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8G.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 17,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
address_a_wire[7..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
ram_block1a[17..0].clk0 = clock0;
|
||||
ram_block1a[17..0].portaaddr[] = ( address_a_wire[7..0]);
|
||||
ram_block1a[17..0].portare = B"111111111111111111";
|
||||
address_a_wire[] = address_a[];
|
||||
q_a[] = ( ram_block1a[17..0].portadataout[0..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,440 +0,0 @@
|
|||
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone 10 LP" ENABLE_RUNTIME_MOD="NO" INIT_FILE="coefL8H.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=18 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cyclone10lp_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
|
||||
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
|
||||
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
|
||||
|
||||
--synthesis_resources = M9K 1
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
|
||||
|
||||
SUBDESIGN altsyncram_ja91
|
||||
(
|
||||
address_a[7..0] : input;
|
||||
clock0 : input;
|
||||
q_a[17..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
ram_block1a0 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 0,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a1 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 1,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a2 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 2,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a3 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 3,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a4 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 4,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a5 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 5,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a6 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 6,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a7 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 7,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a8 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 8,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a9 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 9,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a10 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 10,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a11 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 11,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a12 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 12,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a13 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 13,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a14 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 14,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a15 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 15,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a16 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 16,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block1a17 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "none",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK0_OUTPUT_CLOCK_ENABLE = "none",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
INIT_FILE = "coefL8H.mif",
|
||||
INIT_FILE_LAYOUT = "port_a",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
OPERATION_MODE = "rom",
|
||||
PORT_A_ADDRESS_CLEAR = "none",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_OUT_CLEAR = "none",
|
||||
PORT_A_DATA_OUT_CLOCK = "clock0",
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 17,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 18,
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
address_a_wire[7..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
ram_block1a[17..0].clk0 = clock0;
|
||||
ram_block1a[17..0].portaaddr[] = ( address_a_wire[7..0]);
|
||||
ram_block1a[17..0].portare = B"111111111111111111";
|
||||
address_a_wire[] = address_a[];
|
||||
q_a[] = ( ram_block1a[17..0].portadataout[0..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
|
|
@ -1,322 +0,0 @@
|
|||
--altsyncram ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone 10 LP" ENABLE_ECC="FALSE" LOW_POWER_MODE="AUTO" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="CLEAR1" OUTDATA_REG_B="CLOCK1" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_ECCSTATUS=2 WIDTHAD_A=8 WIDTHAD_B=8 address_a address_b addressstall_b clock0 clock1 clocken1 data_a q_b wren_a
|
||||
--VERSION_BEGIN 17.0 cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cyclone10lp_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
|
||||
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
|
||||
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
|
||||
|
||||
--synthesis_resources = M9K 1
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
|
||||
|
||||
SUBDESIGN altsyncram_t841
|
||||
(
|
||||
address_a[7..0] : input;
|
||||
address_b[7..0] : input;
|
||||
addressstall_b : input;
|
||||
clock0 : input;
|
||||
clock1 : input;
|
||||
clocken1 : input;
|
||||
data_a[7..0] : input;
|
||||
q_b[7..0] : output;
|
||||
wren_a : input;
|
||||
)
|
||||
VARIABLE
|
||||
ram_block11a0 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 0,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 0,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block11a1 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 1,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 1,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block11a2 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 2,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 2,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block11a3 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 3,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 3,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block11a4 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 4,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 4,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block11a5 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 5,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 5,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block11a6 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 6,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 6,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
ram_block11a7 : cyclone10lp_ram_block
|
||||
WITH (
|
||||
CLK0_CORE_CLOCK_ENABLE = "ena0",
|
||||
CLK0_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_CORE_CLOCK_ENABLE = "none",
|
||||
CLK1_INPUT_CLOCK_ENABLE = "none",
|
||||
CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
|
||||
CONNECTIVITY_CHECKING = "OFF",
|
||||
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
||||
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
|
||||
OPERATION_MODE = "dual_port",
|
||||
PORT_A_ADDRESS_WIDTH = 8,
|
||||
PORT_A_DATA_WIDTH = 1,
|
||||
PORT_A_FIRST_ADDRESS = 0,
|
||||
PORT_A_FIRST_BIT_NUMBER = 7,
|
||||
PORT_A_LAST_ADDRESS = 255,
|
||||
PORT_A_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_ADDRESS_CLEAR = "none",
|
||||
PORT_B_ADDRESS_CLOCK = "clock1",
|
||||
PORT_B_ADDRESS_WIDTH = 8,
|
||||
PORT_B_DATA_OUT_CLEAR = "none",
|
||||
PORT_B_DATA_OUT_CLOCK = "clock1",
|
||||
PORT_B_DATA_WIDTH = 1,
|
||||
PORT_B_FIRST_ADDRESS = 0,
|
||||
PORT_B_FIRST_BIT_NUMBER = 7,
|
||||
PORT_B_LAST_ADDRESS = 255,
|
||||
PORT_B_LOGICAL_RAM_DEPTH = 256,
|
||||
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
||||
PORT_B_READ_ENABLE_CLOCK = "clock1",
|
||||
RAM_BLOCK_TYPE = "AUTO"
|
||||
);
|
||||
address_a_wire[7..0] : WIRE;
|
||||
address_b_wire[7..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
ram_block11a[7..0].clk0 = clock0;
|
||||
ram_block11a[7..0].clk1 = clock1;
|
||||
ram_block11a[7..0].ena0 = wren_a;
|
||||
ram_block11a[7..0].ena1 = clocken1;
|
||||
ram_block11a[7..0].portaaddr[] = ( address_a_wire[7..0]);
|
||||
ram_block11a[0].portadatain[] = ( data_a[0..0]);
|
||||
ram_block11a[1].portadatain[] = ( data_a[1..1]);
|
||||
ram_block11a[2].portadatain[] = ( data_a[2..2]);
|
||||
ram_block11a[3].portadatain[] = ( data_a[3..3]);
|
||||
ram_block11a[4].portadatain[] = ( data_a[4..4]);
|
||||
ram_block11a[5].portadatain[] = ( data_a[5..5]);
|
||||
ram_block11a[6].portadatain[] = ( data_a[6..6]);
|
||||
ram_block11a[7].portadatain[] = ( data_a[7..7]);
|
||||
ram_block11a[7..0].portawe = wren_a;
|
||||
ram_block11a[7..0].portbaddr[] = ( address_b_wire[7..0]);
|
||||
ram_block11a[7..0].portbaddrstall = addressstall_b;
|
||||
ram_block11a[7..0].portbre = B"11111111";
|
||||
address_a_wire[] = address_a[];
|
||||
address_b_wire[] = address_b[];
|
||||
q_b[] = ( ram_block11a[7..0].portbdataout[0..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -1,42 +0,0 @@
|
|||
--lpm_compare DEVICE_FAMILY="Cyclone 10 LP" LPM_WIDTH=4 aeb dataa datab
|
||||
--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources =
|
||||
SUBDESIGN cmpr_366
|
||||
(
|
||||
aeb : output;
|
||||
dataa[3..0] : input;
|
||||
datab[3..0] : input;
|
||||
)
|
||||
VARIABLE
|
||||
aeb_result_wire[0..0] : WIRE;
|
||||
aneb_result_wire[0..0] : WIRE;
|
||||
data_wire[9..0] : WIRE;
|
||||
eq_wire : WIRE;
|
||||
|
||||
BEGIN
|
||||
aeb = eq_wire;
|
||||
aeb_result_wire[] = (! aneb_result_wire[]);
|
||||
aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]);
|
||||
data_wire[] = ( datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], ((data_wire[6..6] $ data_wire[7..7]) # (data_wire[8..8] $ data_wire[9..9])), ((data_wire[2..2] $ data_wire[3..3]) # (data_wire[4..4] $ data_wire[5..5])));
|
||||
eq_wire = aeb_result_wire[];
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
--lpm_compare DEVICE_FAMILY="Cyclone 10 LP" LPM_WIDTH=5 aeb dataa datab
|
||||
--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources =
|
||||
SUBDESIGN cmpr_466
|
||||
(
|
||||
aeb : output;
|
||||
dataa[4..0] : input;
|
||||
datab[4..0] : input;
|
||||
)
|
||||
VARIABLE
|
||||
aeb_result_wire[0..0] : WIRE;
|
||||
aneb_result_wire[0..0] : WIRE;
|
||||
data_wire[12..0] : WIRE;
|
||||
eq_wire : WIRE;
|
||||
|
||||
BEGIN
|
||||
aeb = eq_wire;
|
||||
aeb_result_wire[] = (! aneb_result_wire[]);
|
||||
aneb_result_wire[] = ((data_wire[0..0] # data_wire[1..1]) # data_wire[2..2]);
|
||||
data_wire[] = ( datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[11..11] $ data_wire[12..12]), ((data_wire[7..7] $ data_wire[8..8]) # (data_wire[9..9] $ data_wire[10..10])), ((data_wire[3..3] $ data_wire[4..4]) # (data_wire[5..5] $ data_wire[6..6])));
|
||||
eq_wire = aeb_result_wire[];
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
--lpm_compare DEVICE_FAMILY="Cyclone 10 LP" LPM_WIDTH=9 aeb dataa datab
|
||||
--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources =
|
||||
SUBDESIGN cmpr_866
|
||||
(
|
||||
aeb : output;
|
||||
dataa[8..0] : input;
|
||||
datab[8..0] : input;
|
||||
)
|
||||
VARIABLE
|
||||
aeb_result_wire[0..0] : WIRE;
|
||||
aneb_result_wire[0..0] : WIRE;
|
||||
data_wire[24..0] : WIRE;
|
||||
eq_wire : WIRE;
|
||||
|
||||
BEGIN
|
||||
aeb = eq_wire;
|
||||
aeb_result_wire[] = (! aneb_result_wire[]);
|
||||
aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]);
|
||||
data_wire[] = ( datab[8..8], dataa[8..8], datab[7..7], dataa[7..7], datab[6..6], dataa[6..6], datab[5..5], dataa[5..5], datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[23..23] $ data_wire[24..24]), ((data_wire[19..19] $ data_wire[20..20]) # (data_wire[21..21] $ data_wire[22..22])), ((data_wire[15..15] $ data_wire[16..16]) # (data_wire[17..17] $ data_wire[18..18])), ((data_wire[11..11] $ data_wire[12..12]) # (data_wire[13..13] $ data_wire[14..14])), ((data_wire[7..7] $ data_wire[8..8]) # (data_wire[9..9] $ data_wire[10..10])), data_wire[6..6], (((data_wire[2..2] # data_wire[3..3]) # data_wire[4..4]) # data_wire[5..5]));
|
||||
eq_wire = aeb_result_wire[];
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
--lpm_compare DEVICE_FAMILY="Cyclone 10 LP" LPM_WIDTH=12 aeb dataa datab
|
||||
--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources =
|
||||
SUBDESIGN cmpr_i76
|
||||
(
|
||||
aeb : output;
|
||||
dataa[11..0] : input;
|
||||
datab[11..0] : input;
|
||||
)
|
||||
VARIABLE
|
||||
aeb_result_wire[0..0] : WIRE;
|
||||
aneb_result_wire[0..0] : WIRE;
|
||||
data_wire[31..0] : WIRE;
|
||||
eq_wire : WIRE;
|
||||
|
||||
BEGIN
|
||||
aeb = eq_wire;
|
||||
aeb_result_wire[] = (! aneb_result_wire[]);
|
||||
aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]);
|
||||
data_wire[] = ( datab[11..11], dataa[11..11], datab[10..10], dataa[10..10], datab[9..9], dataa[9..9], datab[8..8], dataa[8..8], datab[7..7], dataa[7..7], datab[6..6], dataa[6..6], datab[5..5], dataa[5..5], datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], ((data_wire[28..28] $ data_wire[29..29]) # (data_wire[30..30] $ data_wire[31..31])), ((data_wire[24..24] $ data_wire[25..25]) # (data_wire[26..26] $ data_wire[27..27])), ((data_wire[20..20] $ data_wire[21..21]) # (data_wire[22..22] $ data_wire[23..23])), ((data_wire[16..16] $ data_wire[17..17]) # (data_wire[18..18] $ data_wire[19..19])), ((data_wire[12..12] $ data_wire[13..13]) # (data_wire[14..14] $ data_wire[15..15])), ((data_wire[8..8] $ data_wire[9..9]) # (data_wire[10..10] $ data_wire[11..11])), (data_wire[6..6] # data_wire[7..7]), (((data_wire[2..2] # data_wire[3..3]) # data_wire[4..4]) # data_wire[5..5]));
|
||||
eq_wire = aeb_result_wire[];
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,170 +0,0 @@
|
|||
--dcfifo_mixed_widths CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone 10 LP" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=256 LPM_SHOWAHEAD="OFF" LPM_WIDTH=8 LPM_WIDTH_R=8 LPM_WIDTHU=8 LPM_WIDTHU_R=8 OVERFLOW_CHECKING="OFF" RDSYNC_DELAYPIPE=5 UNDERFLOW_CHECKING="OFF" USE_EAB="ON" WRSYNC_DELAYPIPE=5 data q rdclk rdempty rdreq wrclk wrfull wrreq CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone 10 LP" LOW_POWER_MODE="AUTO" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_altdpram 2017:04:25:18:06:29:SJ cbx_altera_counter 2017:04:25:18:06:29:SJ cbx_altera_gray_counter 2017:04:25:18:06:29:SJ cbx_altera_syncram 2017:04:25:18:06:29:SJ cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_dcfifo 2017:04:25:18:06:29:SJ cbx_fifo_common 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_counter 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_scfifo 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION a_graycounter_kn6 (clock, cnt_en)
|
||||
RETURNS ( q[8..0]);
|
||||
FUNCTION a_graycounter_g5c (clock, cnt_en)
|
||||
RETURNS ( q[8..0]);
|
||||
FUNCTION altsyncram_t841 (address_a[7..0], address_b[7..0], addressstall_b, clock0, clock1, clocken1, data_a[7..0], wren_a)
|
||||
RETURNS ( q_b[7..0]);
|
||||
FUNCTION alt_synch_pipe_h9l (clock, d[8..0])
|
||||
RETURNS ( q[8..0]);
|
||||
FUNCTION alt_synch_pipe_i9l (clock, d[8..0])
|
||||
RETURNS ( q[8..0]);
|
||||
FUNCTION cmpr_466 (dataa[4..0], datab[4..0])
|
||||
RETURNS ( aeb);
|
||||
FUNCTION cmpr_366 (dataa[3..0], datab[3..0])
|
||||
RETURNS ( aeb);
|
||||
FUNCTION mux_c28 (data[1..0], sel[0..0])
|
||||
RETURNS ( result[0..0]);
|
||||
|
||||
--synthesis_resources = lut 4 M9K 1 reg 111
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;SYNCHRONIZER_IDENTIFICATION=OFF;SYNCHRONIZATION_REGISTER_CHAIN_LENGTH = 3;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;suppress_da_rule_internal=d103;{-to rdemp_eq_comp_lsb_aeb} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to rdemp_eq_comp_lsb_aeb} PRESERVE_REGISTER=ON;{-to rdemp_eq_comp_lsb_aeb} POWER_UP_LEVEL=HIGH;{-to rdemp_eq_comp_msb_aeb} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to rdemp_eq_comp_msb_aeb} PRESERVE_REGISTER=ON;{-to rdemp_eq_comp_msb_aeb} POWER_UP_LEVEL=HIGH;{-to rs_dgwp_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to rs_dgwp_reg} PRESERVE_REGISTER=ON;{-to wrfull_eq_comp_lsb_mux_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to wrfull_eq_comp_lsb_mux_reg} PRESERVE_REGISTER=ON;{-to wrfull_eq_comp_msb_mux_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to wrfull_eq_comp_msb_mux_reg} PRESERVE_REGISTER=ON;{-to wrptr_g} suppress_da_rule_internal=S102;{-to wrptr_g} POWER_UP_LEVEL=LOW;{-to ws_dgrp_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to ws_dgrp_reg} PRESERVE_REGISTER=ON;-name CUT ON -from rdptr_g -to ws_dgrp|dffpipe_3v8:dffpipe15|dffe16a;-name SDC_STATEMENT ""set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_3v8:dffpipe15|dffe16a* "";-name CUT ON -from delayed_wrptr_g -to rs_dgwp|dffpipe_2v8:dffpipe12|dffe13a;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_2v8:dffpipe12|dffe13a* """;
|
||||
|
||||
SUBDESIGN dcfifo_2of1
|
||||
(
|
||||
data[7..0] : input;
|
||||
q[7..0] : output;
|
||||
rdclk : input;
|
||||
rdempty : output;
|
||||
rdreq : input;
|
||||
wrclk : input;
|
||||
wrfull : output;
|
||||
wrreq : input;
|
||||
)
|
||||
VARIABLE
|
||||
rdptr_g1p : a_graycounter_kn6;
|
||||
wrptr_g1p : a_graycounter_g5c;
|
||||
fifo_ram : altsyncram_t841;
|
||||
delayed_wrptr_g[8..0] : dffe;
|
||||
rdemp_eq_comp_lsb_aeb : dffe
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
rdemp_eq_comp_msb_aeb : dffe
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
rdptr_g[8..0] : dffe;
|
||||
rs_dgwp_reg[8..0] : dffe;
|
||||
wrfull_eq_comp_lsb_mux_reg : dffe;
|
||||
wrfull_eq_comp_msb_mux_reg : dffe;
|
||||
wrptr_g[8..0] : dffe
|
||||
WITH (
|
||||
power_up = "low"
|
||||
);
|
||||
ws_dgrp_reg[8..0] : dffe;
|
||||
rs_dgwp : alt_synch_pipe_h9l;
|
||||
ws_dgrp : alt_synch_pipe_i9l;
|
||||
rdempty_eq_comp1_lsb : cmpr_466;
|
||||
rdempty_eq_comp1_msb : cmpr_366;
|
||||
rdempty_eq_comp_lsb : cmpr_466;
|
||||
rdempty_eq_comp_msb : cmpr_366;
|
||||
wrfull_eq_comp1_lsb : cmpr_466;
|
||||
wrfull_eq_comp1_msb : cmpr_366;
|
||||
wrfull_eq_comp_lsb : cmpr_466;
|
||||
wrfull_eq_comp_msb : cmpr_366;
|
||||
rdemp_eq_comp_lsb_mux : mux_c28;
|
||||
rdemp_eq_comp_msb_mux : mux_c28;
|
||||
wrfull_eq_comp_lsb_mux : mux_c28;
|
||||
wrfull_eq_comp_msb_mux : mux_c28;
|
||||
int_rdempty : WIRE;
|
||||
int_wrfull : WIRE;
|
||||
ram_address_a[7..0] : WIRE;
|
||||
ram_address_b[7..0] : WIRE;
|
||||
valid_rdreq : WIRE;
|
||||
valid_wrreq : WIRE;
|
||||
wrptr_g1s[8..0] : WIRE;
|
||||
wrptr_gs[8..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
rdptr_g1p.clock = rdclk;
|
||||
rdptr_g1p.cnt_en = valid_rdreq;
|
||||
wrptr_g1p.clock = wrclk;
|
||||
wrptr_g1p.cnt_en = valid_wrreq;
|
||||
fifo_ram.address_a[] = ram_address_a[];
|
||||
fifo_ram.address_b[] = ram_address_b[];
|
||||
fifo_ram.addressstall_b = (! valid_rdreq);
|
||||
fifo_ram.clock0 = wrclk;
|
||||
fifo_ram.clock1 = rdclk;
|
||||
fifo_ram.clocken1 = valid_rdreq;
|
||||
fifo_ram.data_a[] = data[];
|
||||
fifo_ram.wren_a = valid_wrreq;
|
||||
delayed_wrptr_g[].clk = wrclk;
|
||||
delayed_wrptr_g[].d = wrptr_g[].q;
|
||||
rdemp_eq_comp_lsb_aeb.clk = rdclk;
|
||||
rdemp_eq_comp_lsb_aeb.d = rdemp_eq_comp_lsb_mux.result[];
|
||||
rdemp_eq_comp_msb_aeb.clk = rdclk;
|
||||
rdemp_eq_comp_msb_aeb.d = rdemp_eq_comp_msb_mux.result[];
|
||||
rdptr_g[].clk = rdclk;
|
||||
rdptr_g[].d = rdptr_g1p.q[];
|
||||
rdptr_g[].ena = valid_rdreq;
|
||||
rs_dgwp_reg[].clk = rdclk;
|
||||
rs_dgwp_reg[].d = rs_dgwp.q[];
|
||||
wrfull_eq_comp_lsb_mux_reg.clk = wrclk;
|
||||
wrfull_eq_comp_lsb_mux_reg.d = wrfull_eq_comp_lsb_mux.result[];
|
||||
wrfull_eq_comp_msb_mux_reg.clk = wrclk;
|
||||
wrfull_eq_comp_msb_mux_reg.d = wrfull_eq_comp_msb_mux.result[];
|
||||
wrptr_g[].clk = wrclk;
|
||||
wrptr_g[].d = wrptr_g1p.q[];
|
||||
wrptr_g[].ena = valid_wrreq;
|
||||
ws_dgrp_reg[].clk = wrclk;
|
||||
ws_dgrp_reg[].d = ws_dgrp.q[];
|
||||
rs_dgwp.clock = rdclk;
|
||||
rs_dgwp.d[] = delayed_wrptr_g[].q;
|
||||
ws_dgrp.clock = wrclk;
|
||||
ws_dgrp.d[] = rdptr_g[].q;
|
||||
rdempty_eq_comp1_lsb.dataa[4..0] = rs_dgwp.q[4..0];
|
||||
rdempty_eq_comp1_lsb.datab[4..0] = rdptr_g1p.q[4..0];
|
||||
rdempty_eq_comp1_msb.dataa[3..0] = rs_dgwp.q[8..5];
|
||||
rdempty_eq_comp1_msb.datab[3..0] = rdptr_g1p.q[8..5];
|
||||
rdempty_eq_comp_lsb.dataa[4..0] = rs_dgwp.q[4..0];
|
||||
rdempty_eq_comp_lsb.datab[4..0] = rdptr_g[4..0].q;
|
||||
rdempty_eq_comp_msb.dataa[3..0] = rs_dgwp.q[8..5];
|
||||
rdempty_eq_comp_msb.datab[3..0] = rdptr_g[8..5].q;
|
||||
wrfull_eq_comp1_lsb.dataa[4..0] = ws_dgrp.q[4..0];
|
||||
wrfull_eq_comp1_lsb.datab[4..0] = wrptr_g1s[4..0];
|
||||
wrfull_eq_comp1_msb.dataa[3..0] = ws_dgrp.q[8..5];
|
||||
wrfull_eq_comp1_msb.datab[3..0] = wrptr_g1s[8..5];
|
||||
wrfull_eq_comp_lsb.dataa[4..0] = ws_dgrp.q[4..0];
|
||||
wrfull_eq_comp_lsb.datab[4..0] = wrptr_gs[4..0];
|
||||
wrfull_eq_comp_msb.dataa[3..0] = ws_dgrp.q[8..5];
|
||||
wrfull_eq_comp_msb.datab[3..0] = wrptr_gs[8..5];
|
||||
rdemp_eq_comp_lsb_mux.data[] = ( rdempty_eq_comp1_lsb.aeb, rdempty_eq_comp_lsb.aeb);
|
||||
rdemp_eq_comp_lsb_mux.sel[] = valid_rdreq;
|
||||
rdemp_eq_comp_msb_mux.data[] = ( rdempty_eq_comp1_msb.aeb, rdempty_eq_comp_msb.aeb);
|
||||
rdemp_eq_comp_msb_mux.sel[] = valid_rdreq;
|
||||
wrfull_eq_comp_lsb_mux.data[] = ( wrfull_eq_comp1_lsb.aeb, wrfull_eq_comp_lsb.aeb);
|
||||
wrfull_eq_comp_lsb_mux.sel[] = valid_wrreq;
|
||||
wrfull_eq_comp_msb_mux.data[] = ( wrfull_eq_comp1_msb.aeb, wrfull_eq_comp_msb.aeb);
|
||||
wrfull_eq_comp_msb_mux.sel[] = valid_wrreq;
|
||||
int_rdempty = (rdemp_eq_comp_lsb_aeb.q & rdemp_eq_comp_msb_aeb.q);
|
||||
int_wrfull = (wrfull_eq_comp_lsb_mux_reg.q & wrfull_eq_comp_msb_mux_reg.q);
|
||||
q[] = fifo_ram.q_b[];
|
||||
ram_address_a[] = ( (wrptr_g[8..8].q $ wrptr_g[7..7].q), wrptr_g[6..0].q);
|
||||
ram_address_b[] = ( (rdptr_g1p.q[8..8] $ rdptr_g1p.q[7..7]), rdptr_g1p.q[6..0]);
|
||||
rdempty = int_rdempty;
|
||||
valid_rdreq = rdreq;
|
||||
valid_wrreq = wrreq;
|
||||
wrfull = int_wrfull;
|
||||
wrptr_g1s[] = ( (! wrptr_g1p.q[8..8]), (! wrptr_g1p.q[7..7]), wrptr_g1p.q[6..0]);
|
||||
wrptr_gs[] = ( (! wrptr_g[8..8].q), (! wrptr_g[7..7].q), wrptr_g[6..0].q);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,186 +0,0 @@
|
|||
--dcfifo_mixed_widths CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone 10 LP" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=256 LPM_SHOWAHEAD="OFF" LPM_WIDTH=8 LPM_WIDTH_R=8 LPM_WIDTHU=8 LPM_WIDTHU_R=8 OVERFLOW_CHECKING="OFF" RDSYNC_DELAYPIPE=5 READ_ACLR_SYNCH="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" WRITE_ACLR_SYNCH="OFF" WRSYNC_DELAYPIPE=5 aclr data q rdclk rdempty rdreq wrclk wrempty wrreq CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone 10 LP" LOW_POWER_MODE="AUTO" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_altdpram 2017:04:25:18:06:29:SJ cbx_altera_counter 2017:04:25:18:06:29:SJ cbx_altera_gray_counter 2017:04:25:18:06:29:SJ cbx_altera_syncram 2017:04:25:18:06:29:SJ cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_dcfifo 2017:04:25:18:06:29:SJ cbx_fifo_common 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_counter 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_scfifo 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION a_graycounter_m57 (aclr, clock, cnt_en)
|
||||
RETURNS ( q[8..0]);
|
||||
FUNCTION a_graycounter_ijc (aclr, clock, cnt_en)
|
||||
RETURNS ( q[8..0]);
|
||||
FUNCTION altsyncram_hs61 (aclr1, address_a[7..0], address_b[7..0], addressstall_b, clock0, clock1, clocken1, data_a[7..0], wren_a)
|
||||
RETURNS ( q_b[7..0]);
|
||||
FUNCTION alt_synch_pipe_0ol (clock, clrn, d[8..0])
|
||||
RETURNS ( q[8..0]);
|
||||
FUNCTION cmpr_466 (dataa[4..0], datab[4..0])
|
||||
RETURNS ( aeb);
|
||||
FUNCTION cmpr_366 (dataa[3..0], datab[3..0])
|
||||
RETURNS ( aeb);
|
||||
FUNCTION cmpr_866 (dataa[8..0], datab[8..0])
|
||||
RETURNS ( aeb);
|
||||
FUNCTION mux_c28 (data[1..0], sel[0..0])
|
||||
RETURNS ( result[0..0]);
|
||||
|
||||
--synthesis_resources = M9K 1 reg 111
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;SYNCHRONIZER_IDENTIFICATION=OFF;SYNCHRONIZATION_REGISTER_CHAIN_LENGTH = 3;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;suppress_da_rule_internal=d103;{-to rdemp_eq_comp_lsb_aeb} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to rdemp_eq_comp_lsb_aeb} PRESERVE_REGISTER=ON;{-to rdemp_eq_comp_lsb_aeb} POWER_UP_LEVEL=HIGH;{-to rdemp_eq_comp_msb_aeb} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to rdemp_eq_comp_msb_aeb} PRESERVE_REGISTER=ON;{-to rdemp_eq_comp_msb_aeb} POWER_UP_LEVEL=HIGH;{-to rs_dgwp_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to rs_dgwp_reg} PRESERVE_REGISTER=ON;{-to wrfull_eq_comp_lsb_mux_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to wrfull_eq_comp_lsb_mux_reg} PRESERVE_REGISTER=ON;{-to wrfull_eq_comp_msb_mux_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to wrfull_eq_comp_msb_mux_reg} PRESERVE_REGISTER=ON;{-to wrptr_g} suppress_da_rule_internal=S102;{-to wrptr_g} POWER_UP_LEVEL=LOW;{-to ws_dgrp_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to ws_dgrp_reg} PRESERVE_REGISTER=ON;-name CUT ON -from delayed_wrptr_g -to rs_dgwp|dffpipe_hd9:dffpipe10|dffe11a;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_hd9:dffpipe10|dffe11a* """;
|
||||
|
||||
SUBDESIGN dcfifo_9ek1
|
||||
(
|
||||
aclr : input;
|
||||
data[7..0] : input;
|
||||
q[7..0] : output;
|
||||
rdclk : input;
|
||||
rdempty : output;
|
||||
rdreq : input;
|
||||
wrclk : input;
|
||||
wrempty : output;
|
||||
wrreq : input;
|
||||
)
|
||||
VARIABLE
|
||||
rdptr_g1p : a_graycounter_m57;
|
||||
wrptr_g1p : a_graycounter_ijc;
|
||||
fifo_ram : altsyncram_hs61;
|
||||
delayed_wrptr_g[8..0] : dffe;
|
||||
rdemp_eq_comp_lsb_aeb : dffe
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
rdemp_eq_comp_msb_aeb : dffe
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
rdptr_g[8..0] : dffe;
|
||||
rs_dgwp_reg[8..0] : dffe;
|
||||
wrfull_eq_comp_lsb_mux_reg : dffe;
|
||||
wrfull_eq_comp_msb_mux_reg : dffe;
|
||||
wrptr_g[8..0] : dffe
|
||||
WITH (
|
||||
power_up = "low"
|
||||
);
|
||||
ws_dgrp_reg[8..0] : dffe;
|
||||
rs_dgwp : alt_synch_pipe_0ol;
|
||||
ws_dgrp : alt_synch_pipe_0ol;
|
||||
rdempty_eq_comp1_lsb : cmpr_466;
|
||||
rdempty_eq_comp1_msb : cmpr_366;
|
||||
rdempty_eq_comp_lsb : cmpr_466;
|
||||
rdempty_eq_comp_msb : cmpr_366;
|
||||
wrempty_eq_comp : cmpr_866;
|
||||
wrfull_eq_comp1_lsb : cmpr_466;
|
||||
wrfull_eq_comp1_msb : cmpr_366;
|
||||
wrfull_eq_comp_lsb : cmpr_466;
|
||||
wrfull_eq_comp_msb : cmpr_366;
|
||||
rdemp_eq_comp_lsb_mux : mux_c28;
|
||||
rdemp_eq_comp_msb_mux : mux_c28;
|
||||
wrfull_eq_comp_lsb_mux : mux_c28;
|
||||
wrfull_eq_comp_msb_mux : mux_c28;
|
||||
int_rdempty : WIRE;
|
||||
ram_address_a[7..0] : WIRE;
|
||||
ram_address_b[7..0] : WIRE;
|
||||
valid_rdreq : WIRE;
|
||||
valid_wrreq : WIRE;
|
||||
wrptr_g1s[8..0] : WIRE;
|
||||
wrptr_gs[8..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
rdptr_g1p.aclr = aclr;
|
||||
rdptr_g1p.clock = rdclk;
|
||||
rdptr_g1p.cnt_en = valid_rdreq;
|
||||
wrptr_g1p.aclr = aclr;
|
||||
wrptr_g1p.clock = wrclk;
|
||||
wrptr_g1p.cnt_en = valid_wrreq;
|
||||
fifo_ram.aclr1 = aclr;
|
||||
fifo_ram.address_a[] = ram_address_a[];
|
||||
fifo_ram.address_b[] = ram_address_b[];
|
||||
fifo_ram.addressstall_b = (! valid_rdreq);
|
||||
fifo_ram.clock0 = wrclk;
|
||||
fifo_ram.clock1 = rdclk;
|
||||
fifo_ram.clocken1 = valid_rdreq;
|
||||
fifo_ram.data_a[] = data[];
|
||||
fifo_ram.wren_a = valid_wrreq;
|
||||
delayed_wrptr_g[].clk = wrclk;
|
||||
delayed_wrptr_g[].clrn = (! aclr);
|
||||
delayed_wrptr_g[].d = wrptr_g[].q;
|
||||
rdemp_eq_comp_lsb_aeb.clk = rdclk;
|
||||
rdemp_eq_comp_lsb_aeb.d = rdemp_eq_comp_lsb_mux.result[];
|
||||
rdemp_eq_comp_lsb_aeb.prn = (! aclr);
|
||||
rdemp_eq_comp_msb_aeb.clk = rdclk;
|
||||
rdemp_eq_comp_msb_aeb.d = rdemp_eq_comp_msb_mux.result[];
|
||||
rdemp_eq_comp_msb_aeb.prn = (! aclr);
|
||||
rdptr_g[].clk = rdclk;
|
||||
rdptr_g[].clrn = (! aclr);
|
||||
rdptr_g[].d = rdptr_g1p.q[];
|
||||
rdptr_g[].ena = valid_rdreq;
|
||||
rs_dgwp_reg[].clk = rdclk;
|
||||
rs_dgwp_reg[].clrn = (! aclr);
|
||||
rs_dgwp_reg[].d = rs_dgwp.q[];
|
||||
wrfull_eq_comp_lsb_mux_reg.clk = wrclk;
|
||||
wrfull_eq_comp_lsb_mux_reg.clrn = (! aclr);
|
||||
wrfull_eq_comp_lsb_mux_reg.d = wrfull_eq_comp_lsb_mux.result[];
|
||||
wrfull_eq_comp_msb_mux_reg.clk = wrclk;
|
||||
wrfull_eq_comp_msb_mux_reg.clrn = (! aclr);
|
||||
wrfull_eq_comp_msb_mux_reg.d = wrfull_eq_comp_msb_mux.result[];
|
||||
wrptr_g[].clk = wrclk;
|
||||
wrptr_g[].clrn = (! aclr);
|
||||
wrptr_g[].d = wrptr_g1p.q[];
|
||||
wrptr_g[].ena = valid_wrreq;
|
||||
ws_dgrp_reg[].clk = wrclk;
|
||||
ws_dgrp_reg[].clrn = (! aclr);
|
||||
ws_dgrp_reg[].d = ws_dgrp.q[];
|
||||
rs_dgwp.clock = rdclk;
|
||||
rs_dgwp.clrn = (! aclr);
|
||||
rs_dgwp.d[] = delayed_wrptr_g[].q;
|
||||
ws_dgrp.clock = wrclk;
|
||||
ws_dgrp.clrn = (! aclr);
|
||||
ws_dgrp.d[] = rdptr_g[].q;
|
||||
rdempty_eq_comp1_lsb.dataa[4..0] = rs_dgwp.q[4..0];
|
||||
rdempty_eq_comp1_lsb.datab[4..0] = rdptr_g1p.q[4..0];
|
||||
rdempty_eq_comp1_msb.dataa[3..0] = rs_dgwp.q[8..5];
|
||||
rdempty_eq_comp1_msb.datab[3..0] = rdptr_g1p.q[8..5];
|
||||
rdempty_eq_comp_lsb.dataa[4..0] = rs_dgwp.q[4..0];
|
||||
rdempty_eq_comp_lsb.datab[4..0] = rdptr_g[4..0].q;
|
||||
rdempty_eq_comp_msb.dataa[3..0] = rs_dgwp.q[8..5];
|
||||
rdempty_eq_comp_msb.datab[3..0] = rdptr_g[8..5].q;
|
||||
wrempty_eq_comp.dataa[] = ws_dgrp_reg[].q;
|
||||
wrempty_eq_comp.datab[] = wrptr_g[].q;
|
||||
wrfull_eq_comp1_lsb.dataa[4..0] = ws_dgrp.q[4..0];
|
||||
wrfull_eq_comp1_lsb.datab[4..0] = wrptr_g1s[4..0];
|
||||
wrfull_eq_comp1_msb.dataa[3..0] = ws_dgrp.q[8..5];
|
||||
wrfull_eq_comp1_msb.datab[3..0] = wrptr_g1s[8..5];
|
||||
wrfull_eq_comp_lsb.dataa[4..0] = ws_dgrp.q[4..0];
|
||||
wrfull_eq_comp_lsb.datab[4..0] = wrptr_gs[4..0];
|
||||
wrfull_eq_comp_msb.dataa[3..0] = ws_dgrp.q[8..5];
|
||||
wrfull_eq_comp_msb.datab[3..0] = wrptr_gs[8..5];
|
||||
rdemp_eq_comp_lsb_mux.data[] = ( rdempty_eq_comp1_lsb.aeb, rdempty_eq_comp_lsb.aeb);
|
||||
rdemp_eq_comp_lsb_mux.sel[] = valid_rdreq;
|
||||
rdemp_eq_comp_msb_mux.data[] = ( rdempty_eq_comp1_msb.aeb, rdempty_eq_comp_msb.aeb);
|
||||
rdemp_eq_comp_msb_mux.sel[] = valid_rdreq;
|
||||
wrfull_eq_comp_lsb_mux.data[] = ( wrfull_eq_comp1_lsb.aeb, wrfull_eq_comp_lsb.aeb);
|
||||
wrfull_eq_comp_lsb_mux.sel[] = valid_wrreq;
|
||||
wrfull_eq_comp_msb_mux.data[] = ( wrfull_eq_comp1_msb.aeb, wrfull_eq_comp_msb.aeb);
|
||||
wrfull_eq_comp_msb_mux.sel[] = valid_wrreq;
|
||||
int_rdempty = (rdemp_eq_comp_lsb_aeb.q & rdemp_eq_comp_msb_aeb.q);
|
||||
q[] = fifo_ram.q_b[];
|
||||
ram_address_a[] = ( (wrptr_g[8..8].q $ wrptr_g[7..7].q), wrptr_g[6..0].q);
|
||||
ram_address_b[] = ( (rdptr_g1p.q[8..8] $ rdptr_g1p.q[7..7]), rdptr_g1p.q[6..0]);
|
||||
rdempty = int_rdempty;
|
||||
valid_rdreq = rdreq;
|
||||
valid_wrreq = wrreq;
|
||||
wrempty = wrempty_eq_comp.aeb;
|
||||
wrptr_g1s[] = ( (! wrptr_g1p.q[8..8]), (! wrptr_g1p.q[7..7]), wrptr_g1p.q[6..0]);
|
||||
wrptr_gs[] = ( (! wrptr_g[8..8].q), (! wrptr_g[7..7].q), wrptr_g[6..0].q);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,120 +0,0 @@
|
|||
--dcfifo_mixed_widths CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone 10 LP" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=2048 LPM_SHOWAHEAD="OFF" LPM_WIDTH=32 LPM_WIDTH_R=32 LPM_WIDTHU=11 LPM_WIDTHU_R=11 OVERFLOW_CHECKING="OFF" RDSYNC_DELAYPIPE=4 READ_ACLR_SYNCH="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" WRITE_ACLR_SYNCH="OFF" WRSYNC_DELAYPIPE=4 aclr data q rdclk rdempty rdfull rdreq wrclk wrreq CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone III" LOW_POWER_MODE="AUTO" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_altdpram 2017:04:25:18:06:29:SJ cbx_altera_counter 2017:04:25:18:06:29:SJ cbx_altera_gray_counter 2017:04:25:18:06:29:SJ cbx_altera_syncram 2017:04:25:18:06:29:SJ cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_dcfifo 2017:04:25:18:06:29:SJ cbx_fifo_common 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_counter 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_scfifo 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION a_graycounter_077 (aclr, clock, cnt_en)
|
||||
RETURNS ( q[11..0]);
|
||||
FUNCTION a_graycounter_skc (aclr, clock, cnt_en)
|
||||
RETURNS ( q[11..0]);
|
||||
FUNCTION altsyncram_v171 (aclr1, address_a[10..0], address_b[10..0], addressstall_b, clock0, clock1, clocken1, data_a[31..0], wren_a)
|
||||
RETURNS ( q_b[31..0]);
|
||||
FUNCTION alt_synch_pipe_apl (clock, clrn, d[11..0])
|
||||
RETURNS ( q[11..0]);
|
||||
FUNCTION cmpr_i76 (dataa[11..0], datab[11..0])
|
||||
RETURNS ( aeb);
|
||||
|
||||
--synthesis_resources = M9K 8 reg 116
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;SYNCHRONIZER_IDENTIFICATION=OFF;SYNCHRONIZATION_REGISTER_CHAIN_LENGTH = 2;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;suppress_da_rule_internal=d103;{-to wrptr_g} suppress_da_rule_internal=S102;{-to wrptr_g} POWER_UP_LEVEL=LOW;-name CUT ON -from delayed_wrptr_g -to rs_dgwp|dffpipe_re9:dffpipe10|dffe11a;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_re9:dffpipe10|dffe11a* """;
|
||||
|
||||
SUBDESIGN dcfifo_lfk1
|
||||
(
|
||||
aclr : input;
|
||||
data[31..0] : input;
|
||||
q[31..0] : output;
|
||||
rdclk : input;
|
||||
rdempty : output;
|
||||
rdfull : output;
|
||||
rdreq : input;
|
||||
wrclk : input;
|
||||
wrreq : input;
|
||||
)
|
||||
VARIABLE
|
||||
rdptr_g1p : a_graycounter_077;
|
||||
wrptr_g1p : a_graycounter_skc;
|
||||
fifo_ram : altsyncram_v171;
|
||||
delayed_wrptr_g[11..0] : dffe;
|
||||
rdptr_g[11..0] : dffe;
|
||||
wrptr_g[11..0] : dffe
|
||||
WITH (
|
||||
power_up = "low"
|
||||
);
|
||||
rs_dgwp : alt_synch_pipe_apl;
|
||||
ws_dgrp : alt_synch_pipe_apl;
|
||||
rdempty_eq_comp : cmpr_i76;
|
||||
rdfull_eq_comp : cmpr_i76;
|
||||
wrfull_eq_comp : cmpr_i76;
|
||||
int_rdempty : WIRE;
|
||||
ram_address_a[10..0] : WIRE;
|
||||
ram_address_b[10..0] : WIRE;
|
||||
rdptr_gs[11..0] : WIRE;
|
||||
valid_rdreq : WIRE;
|
||||
valid_wrreq : WIRE;
|
||||
wrptr_gs[11..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
rdptr_g1p.aclr = aclr;
|
||||
rdptr_g1p.clock = rdclk;
|
||||
rdptr_g1p.cnt_en = valid_rdreq;
|
||||
wrptr_g1p.aclr = aclr;
|
||||
wrptr_g1p.clock = wrclk;
|
||||
wrptr_g1p.cnt_en = valid_wrreq;
|
||||
fifo_ram.aclr1 = aclr;
|
||||
fifo_ram.address_a[] = ram_address_a[];
|
||||
fifo_ram.address_b[] = ram_address_b[];
|
||||
fifo_ram.addressstall_b = (! valid_rdreq);
|
||||
fifo_ram.clock0 = wrclk;
|
||||
fifo_ram.clock1 = rdclk;
|
||||
fifo_ram.clocken1 = valid_rdreq;
|
||||
fifo_ram.data_a[] = data[];
|
||||
fifo_ram.wren_a = valid_wrreq;
|
||||
delayed_wrptr_g[].clk = wrclk;
|
||||
delayed_wrptr_g[].clrn = (! aclr);
|
||||
delayed_wrptr_g[].d = wrptr_g[].q;
|
||||
rdptr_g[].clk = rdclk;
|
||||
rdptr_g[].clrn = (! aclr);
|
||||
rdptr_g[].d = rdptr_g1p.q[];
|
||||
rdptr_g[].ena = valid_rdreq;
|
||||
wrptr_g[].clk = wrclk;
|
||||
wrptr_g[].clrn = (! aclr);
|
||||
wrptr_g[].d = wrptr_g1p.q[];
|
||||
wrptr_g[].ena = valid_wrreq;
|
||||
rs_dgwp.clock = rdclk;
|
||||
rs_dgwp.clrn = (! aclr);
|
||||
rs_dgwp.d[] = delayed_wrptr_g[].q;
|
||||
ws_dgrp.clock = wrclk;
|
||||
ws_dgrp.clrn = (! aclr);
|
||||
ws_dgrp.d[] = rdptr_g[].q;
|
||||
rdempty_eq_comp.dataa[] = rs_dgwp.q[];
|
||||
rdempty_eq_comp.datab[] = rdptr_g[].q;
|
||||
rdfull_eq_comp.dataa[] = rs_dgwp.q[];
|
||||
rdfull_eq_comp.datab[] = rdptr_gs[];
|
||||
wrfull_eq_comp.dataa[] = ws_dgrp.q[];
|
||||
wrfull_eq_comp.datab[] = wrptr_gs[];
|
||||
int_rdempty = rdempty_eq_comp.aeb;
|
||||
q[] = fifo_ram.q_b[];
|
||||
ram_address_a[] = ( (wrptr_g[11..11].q $ wrptr_g[10..10].q), wrptr_g[9..0].q);
|
||||
ram_address_b[] = ( (rdptr_g1p.q[11..11] $ rdptr_g1p.q[10..10]), rdptr_g1p.q[9..0]);
|
||||
rdempty = int_rdempty;
|
||||
rdfull = rdfull_eq_comp.aeb;
|
||||
rdptr_gs[] = ( (! rdptr_g[11..11].q), (! rdptr_g[10..10].q), rdptr_g[9..0].q);
|
||||
valid_rdreq = rdreq;
|
||||
valid_wrreq = wrreq;
|
||||
wrptr_gs[] = ( (! wrptr_g[11..11].q), (! wrptr_g[10..10].q), wrptr_g[9..0].q);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,122 +0,0 @@
|
|||
--dcfifo_mixed_widths CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone 10 LP" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=2048 LPM_SHOWAHEAD="OFF" LPM_WIDTH=32 LPM_WIDTH_R=32 LPM_WIDTHU=11 LPM_WIDTHU_R=11 OVERFLOW_CHECKING="OFF" RDSYNC_DELAYPIPE=4 READ_ACLR_SYNCH="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" WRITE_ACLR_SYNCH="OFF" WRSYNC_DELAYPIPE=4 aclr data q rdclk rdempty rdfull rdreq wrclk wrreq CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone 10 LP" LOW_POWER_MODE="AUTO" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_altdpram 2017:04:25:18:06:29:SJ cbx_altera_counter 2017:04:25:18:06:29:SJ cbx_altera_gray_counter 2017:04:25:18:06:29:SJ cbx_altera_syncram 2017:04:25:18:06:29:SJ cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_dcfifo 2017:04:25:18:06:29:SJ cbx_fifo_common 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_counter 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_scfifo 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION a_graycounter_077 (aclr, clock, cnt_en)
|
||||
RETURNS ( q[11..0]);
|
||||
FUNCTION a_graycounter_skc (aclr, clock, cnt_en)
|
||||
RETURNS ( q[11..0]);
|
||||
FUNCTION altsyncram_v171 (aclr1, address_a[10..0], address_b[10..0], addressstall_b, clock0, clock1, clocken1, data_a[31..0], wren_a)
|
||||
RETURNS ( q_b[31..0]);
|
||||
FUNCTION alt_synch_pipe_bpl (clock, clrn, d[11..0])
|
||||
RETURNS ( q[11..0]);
|
||||
FUNCTION alt_synch_pipe_apl (clock, clrn, d[11..0])
|
||||
RETURNS ( q[11..0]);
|
||||
FUNCTION cmpr_i76 (dataa[11..0], datab[11..0])
|
||||
RETURNS ( aeb);
|
||||
|
||||
--synthesis_resources = reg 60
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;SYNCHRONIZER_IDENTIFICATION=OFF;SYNCHRONIZATION_REGISTER_CHAIN_LENGTH = 2;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;suppress_da_rule_internal=d103;{-to wrptr_g} suppress_da_rule_internal=S102;{-to wrptr_g} POWER_UP_LEVEL=LOW;-name CUT ON -from delayed_wrptr_g -to rs_dgwp|dffpipe_se9:dffpipe3|dffe4a;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_se9:dffpipe3|dffe4a* """;
|
||||
|
||||
SUBDESIGN dcfifo_ngk1
|
||||
(
|
||||
aclr : input;
|
||||
data[31..0] : input;
|
||||
q[31..0] : output;
|
||||
rdclk : input;
|
||||
rdempty : output;
|
||||
rdfull : output;
|
||||
rdreq : input;
|
||||
wrclk : input;
|
||||
wrreq : input;
|
||||
)
|
||||
VARIABLE
|
||||
rdptr_g1p : a_graycounter_077;
|
||||
wrptr_g1p : a_graycounter_skc;
|
||||
fifo_ram : altsyncram_v171;
|
||||
delayed_wrptr_g[11..0] : dffe;
|
||||
rdptr_g[11..0] : dffe;
|
||||
wrptr_g[11..0] : dffe
|
||||
WITH (
|
||||
power_up = "low"
|
||||
);
|
||||
rs_dgwp : alt_synch_pipe_bpl;
|
||||
ws_dgrp : alt_synch_pipe_apl;
|
||||
rdempty_eq_comp : cmpr_i76;
|
||||
rdfull_eq_comp : cmpr_i76;
|
||||
wrfull_eq_comp : cmpr_i76;
|
||||
int_rdempty : WIRE;
|
||||
ram_address_a[10..0] : WIRE;
|
||||
ram_address_b[10..0] : WIRE;
|
||||
rdptr_gs[11..0] : WIRE;
|
||||
valid_rdreq : WIRE;
|
||||
valid_wrreq : WIRE;
|
||||
wrptr_gs[11..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
rdptr_g1p.aclr = aclr;
|
||||
rdptr_g1p.clock = rdclk;
|
||||
rdptr_g1p.cnt_en = valid_rdreq;
|
||||
wrptr_g1p.aclr = aclr;
|
||||
wrptr_g1p.clock = wrclk;
|
||||
wrptr_g1p.cnt_en = valid_wrreq;
|
||||
fifo_ram.aclr1 = aclr;
|
||||
fifo_ram.address_a[] = ram_address_a[];
|
||||
fifo_ram.address_b[] = ram_address_b[];
|
||||
fifo_ram.addressstall_b = (! valid_rdreq);
|
||||
fifo_ram.clock0 = wrclk;
|
||||
fifo_ram.clock1 = rdclk;
|
||||
fifo_ram.clocken1 = valid_rdreq;
|
||||
fifo_ram.data_a[] = data[];
|
||||
fifo_ram.wren_a = valid_wrreq;
|
||||
delayed_wrptr_g[].clk = wrclk;
|
||||
delayed_wrptr_g[].clrn = (! aclr);
|
||||
delayed_wrptr_g[].d = wrptr_g[].q;
|
||||
rdptr_g[].clk = rdclk;
|
||||
rdptr_g[].clrn = (! aclr);
|
||||
rdptr_g[].d = rdptr_g1p.q[];
|
||||
rdptr_g[].ena = valid_rdreq;
|
||||
wrptr_g[].clk = wrclk;
|
||||
wrptr_g[].clrn = (! aclr);
|
||||
wrptr_g[].d = wrptr_g1p.q[];
|
||||
wrptr_g[].ena = valid_wrreq;
|
||||
rs_dgwp.clock = rdclk;
|
||||
rs_dgwp.clrn = (! aclr);
|
||||
rs_dgwp.d[] = delayed_wrptr_g[].q;
|
||||
ws_dgrp.clock = wrclk;
|
||||
ws_dgrp.clrn = (! aclr);
|
||||
ws_dgrp.d[] = rdptr_g[].q;
|
||||
rdempty_eq_comp.dataa[] = rs_dgwp.q[];
|
||||
rdempty_eq_comp.datab[] = rdptr_g[].q;
|
||||
rdfull_eq_comp.dataa[] = rs_dgwp.q[];
|
||||
rdfull_eq_comp.datab[] = rdptr_gs[];
|
||||
wrfull_eq_comp.dataa[] = ws_dgrp.q[];
|
||||
wrfull_eq_comp.datab[] = wrptr_gs[];
|
||||
int_rdempty = rdempty_eq_comp.aeb;
|
||||
q[] = fifo_ram.q_b[];
|
||||
ram_address_a[] = ( (wrptr_g[11..11].q $ wrptr_g[10..10].q), wrptr_g[9..0].q);
|
||||
ram_address_b[] = ( (rdptr_g1p.q[11..11] $ rdptr_g1p.q[10..10]), rdptr_g1p.q[9..0]);
|
||||
rdempty = int_rdempty;
|
||||
rdfull = rdfull_eq_comp.aeb;
|
||||
rdptr_gs[] = ( (! rdptr_g[11..11].q), (! rdptr_g[10..10].q), rdptr_g[9..0].q);
|
||||
valid_rdreq = rdreq;
|
||||
valid_wrreq = wrreq;
|
||||
wrptr_gs[] = ( (! wrptr_g[11..11].q), (! wrptr_g[10..10].q), wrptr_g[9..0].q);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,173 +0,0 @@
|
|||
--dcfifo_mixed_widths CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone 10 LP" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=256 LPM_SHOWAHEAD="OFF" LPM_WIDTH=8 LPM_WIDTH_R=8 LPM_WIDTHU=8 LPM_WIDTHU_R=8 OVERFLOW_CHECKING="OFF" RDSYNC_DELAYPIPE=5 UNDERFLOW_CHECKING="OFF" USE_EAB="ON" WRSYNC_DELAYPIPE=5 data q rdclk rdempty rdreq wrclk wrempty wrreq CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone 10 LP" LOW_POWER_MODE="AUTO" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
|
||||
--VERSION_BEGIN 17.0 cbx_a_gray2bin 2017:04:25:18:06:29:SJ cbx_a_graycounter 2017:04:25:18:06:29:SJ cbx_altdpram 2017:04:25:18:06:29:SJ cbx_altera_counter 2017:04:25:18:06:29:SJ cbx_altera_gray_counter 2017:04:25:18:06:29:SJ cbx_altera_syncram 2017:04:25:18:06:29:SJ cbx_altera_syncram_nd_impl 2017:04:25:18:06:29:SJ cbx_altsyncram 2017:04:25:18:06:29:SJ cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_dcfifo 2017:04:25:18:06:29:SJ cbx_fifo_common 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_compare 2017:04:25:18:06:29:SJ cbx_lpm_counter 2017:04:25:18:06:29:SJ cbx_lpm_decode 2017:04:25:18:06:29:SJ cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_scfifo 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_stratixiii 2017:04:25:18:06:30:SJ cbx_stratixv 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION a_graycounter_kn6 (clock, cnt_en)
|
||||
RETURNS ( q[8..0]);
|
||||
FUNCTION a_graycounter_g5c (clock, cnt_en)
|
||||
RETURNS ( q[8..0]);
|
||||
FUNCTION altsyncram_t841 (address_a[7..0], address_b[7..0], addressstall_b, clock0, clock1, clocken1, data_a[7..0], wren_a)
|
||||
RETURNS ( q_b[7..0]);
|
||||
FUNCTION alt_synch_pipe_j9l (clock, d[8..0])
|
||||
RETURNS ( q[8..0]);
|
||||
FUNCTION alt_synch_pipe_h9l (clock, d[8..0])
|
||||
RETURNS ( q[8..0]);
|
||||
FUNCTION cmpr_466 (dataa[4..0], datab[4..0])
|
||||
RETURNS ( aeb);
|
||||
FUNCTION cmpr_366 (dataa[3..0], datab[3..0])
|
||||
RETURNS ( aeb);
|
||||
FUNCTION cmpr_866 (dataa[8..0], datab[8..0])
|
||||
RETURNS ( aeb);
|
||||
FUNCTION mux_c28 (data[1..0], sel[0..0])
|
||||
RETURNS ( result[0..0]);
|
||||
|
||||
--synthesis_resources = reg 67
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;SYNCHRONIZER_IDENTIFICATION=OFF;SYNCHRONIZATION_REGISTER_CHAIN_LENGTH = 3;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;suppress_da_rule_internal=d103;{-to rdemp_eq_comp_lsb_aeb} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to rdemp_eq_comp_lsb_aeb} PRESERVE_REGISTER=ON;{-to rdemp_eq_comp_lsb_aeb} POWER_UP_LEVEL=HIGH;{-to rdemp_eq_comp_msb_aeb} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to rdemp_eq_comp_msb_aeb} PRESERVE_REGISTER=ON;{-to rdemp_eq_comp_msb_aeb} POWER_UP_LEVEL=HIGH;{-to rs_dgwp_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to rs_dgwp_reg} PRESERVE_REGISTER=ON;{-to wrfull_eq_comp_lsb_mux_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to wrfull_eq_comp_lsb_mux_reg} PRESERVE_REGISTER=ON;{-to wrfull_eq_comp_msb_mux_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to wrfull_eq_comp_msb_mux_reg} PRESERVE_REGISTER=ON;{-to wrptr_g} suppress_da_rule_internal=S102;{-to wrptr_g} POWER_UP_LEVEL=LOW;{-to ws_dgrp_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to ws_dgrp_reg} PRESERVE_REGISTER=ON;-name CUT ON -from delayed_wrptr_g -to rs_dgwp|dffpipe_4v8:dffpipe3|dffe4a;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_4v8:dffpipe3|dffe4a* """;
|
||||
|
||||
SUBDESIGN dcfifo_urf1
|
||||
(
|
||||
data[7..0] : input;
|
||||
q[7..0] : output;
|
||||
rdclk : input;
|
||||
rdempty : output;
|
||||
rdreq : input;
|
||||
wrclk : input;
|
||||
wrempty : output;
|
||||
wrreq : input;
|
||||
)
|
||||
VARIABLE
|
||||
rdptr_g1p : a_graycounter_kn6;
|
||||
wrptr_g1p : a_graycounter_g5c;
|
||||
fifo_ram : altsyncram_t841;
|
||||
delayed_wrptr_g[8..0] : dffe;
|
||||
rdemp_eq_comp_lsb_aeb : dffe
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
rdemp_eq_comp_msb_aeb : dffe
|
||||
WITH (
|
||||
power_up = "high"
|
||||
);
|
||||
rdptr_g[8..0] : dffe;
|
||||
rs_dgwp_reg[8..0] : dffe;
|
||||
wrfull_eq_comp_lsb_mux_reg : dffe;
|
||||
wrfull_eq_comp_msb_mux_reg : dffe;
|
||||
wrptr_g[8..0] : dffe
|
||||
WITH (
|
||||
power_up = "low"
|
||||
);
|
||||
ws_dgrp_reg[8..0] : dffe;
|
||||
rs_dgwp : alt_synch_pipe_j9l;
|
||||
ws_dgrp : alt_synch_pipe_h9l;
|
||||
rdempty_eq_comp1_lsb : cmpr_466;
|
||||
rdempty_eq_comp1_msb : cmpr_366;
|
||||
rdempty_eq_comp_lsb : cmpr_466;
|
||||
rdempty_eq_comp_msb : cmpr_366;
|
||||
wrempty_eq_comp : cmpr_866;
|
||||
wrfull_eq_comp1_lsb : cmpr_466;
|
||||
wrfull_eq_comp1_msb : cmpr_366;
|
||||
wrfull_eq_comp_lsb : cmpr_466;
|
||||
wrfull_eq_comp_msb : cmpr_366;
|
||||
rdemp_eq_comp_lsb_mux : mux_c28;
|
||||
rdemp_eq_comp_msb_mux : mux_c28;
|
||||
wrfull_eq_comp_lsb_mux : mux_c28;
|
||||
wrfull_eq_comp_msb_mux : mux_c28;
|
||||
int_rdempty : WIRE;
|
||||
ram_address_a[7..0] : WIRE;
|
||||
ram_address_b[7..0] : WIRE;
|
||||
valid_rdreq : WIRE;
|
||||
valid_wrreq : WIRE;
|
||||
wrptr_g1s[8..0] : WIRE;
|
||||
wrptr_gs[8..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
rdptr_g1p.clock = rdclk;
|
||||
rdptr_g1p.cnt_en = valid_rdreq;
|
||||
wrptr_g1p.clock = wrclk;
|
||||
wrptr_g1p.cnt_en = valid_wrreq;
|
||||
fifo_ram.address_a[] = ram_address_a[];
|
||||
fifo_ram.address_b[] = ram_address_b[];
|
||||
fifo_ram.addressstall_b = (! valid_rdreq);
|
||||
fifo_ram.clock0 = wrclk;
|
||||
fifo_ram.clock1 = rdclk;
|
||||
fifo_ram.clocken1 = valid_rdreq;
|
||||
fifo_ram.data_a[] = data[];
|
||||
fifo_ram.wren_a = valid_wrreq;
|
||||
delayed_wrptr_g[].clk = wrclk;
|
||||
delayed_wrptr_g[].d = wrptr_g[].q;
|
||||
rdemp_eq_comp_lsb_aeb.clk = rdclk;
|
||||
rdemp_eq_comp_lsb_aeb.d = rdemp_eq_comp_lsb_mux.result[];
|
||||
rdemp_eq_comp_msb_aeb.clk = rdclk;
|
||||
rdemp_eq_comp_msb_aeb.d = rdemp_eq_comp_msb_mux.result[];
|
||||
rdptr_g[].clk = rdclk;
|
||||
rdptr_g[].d = rdptr_g1p.q[];
|
||||
rdptr_g[].ena = valid_rdreq;
|
||||
rs_dgwp_reg[].clk = rdclk;
|
||||
rs_dgwp_reg[].d = rs_dgwp.q[];
|
||||
wrfull_eq_comp_lsb_mux_reg.clk = wrclk;
|
||||
wrfull_eq_comp_lsb_mux_reg.d = wrfull_eq_comp_lsb_mux.result[];
|
||||
wrfull_eq_comp_msb_mux_reg.clk = wrclk;
|
||||
wrfull_eq_comp_msb_mux_reg.d = wrfull_eq_comp_msb_mux.result[];
|
||||
wrptr_g[].clk = wrclk;
|
||||
wrptr_g[].d = wrptr_g1p.q[];
|
||||
wrptr_g[].ena = valid_wrreq;
|
||||
ws_dgrp_reg[].clk = wrclk;
|
||||
ws_dgrp_reg[].d = ws_dgrp.q[];
|
||||
rs_dgwp.clock = rdclk;
|
||||
rs_dgwp.d[] = delayed_wrptr_g[].q;
|
||||
ws_dgrp.clock = wrclk;
|
||||
ws_dgrp.d[] = rdptr_g[].q;
|
||||
rdempty_eq_comp1_lsb.dataa[4..0] = rs_dgwp.q[4..0];
|
||||
rdempty_eq_comp1_lsb.datab[4..0] = rdptr_g1p.q[4..0];
|
||||
rdempty_eq_comp1_msb.dataa[3..0] = rs_dgwp.q[8..5];
|
||||
rdempty_eq_comp1_msb.datab[3..0] = rdptr_g1p.q[8..5];
|
||||
rdempty_eq_comp_lsb.dataa[4..0] = rs_dgwp.q[4..0];
|
||||
rdempty_eq_comp_lsb.datab[4..0] = rdptr_g[4..0].q;
|
||||
rdempty_eq_comp_msb.dataa[3..0] = rs_dgwp.q[8..5];
|
||||
rdempty_eq_comp_msb.datab[3..0] = rdptr_g[8..5].q;
|
||||
wrempty_eq_comp.dataa[] = ws_dgrp_reg[].q;
|
||||
wrempty_eq_comp.datab[] = wrptr_g[].q;
|
||||
wrfull_eq_comp1_lsb.dataa[4..0] = ws_dgrp.q[4..0];
|
||||
wrfull_eq_comp1_lsb.datab[4..0] = wrptr_g1s[4..0];
|
||||
wrfull_eq_comp1_msb.dataa[3..0] = ws_dgrp.q[8..5];
|
||||
wrfull_eq_comp1_msb.datab[3..0] = wrptr_g1s[8..5];
|
||||
wrfull_eq_comp_lsb.dataa[4..0] = ws_dgrp.q[4..0];
|
||||
wrfull_eq_comp_lsb.datab[4..0] = wrptr_gs[4..0];
|
||||
wrfull_eq_comp_msb.dataa[3..0] = ws_dgrp.q[8..5];
|
||||
wrfull_eq_comp_msb.datab[3..0] = wrptr_gs[8..5];
|
||||
rdemp_eq_comp_lsb_mux.data[] = ( rdempty_eq_comp1_lsb.aeb, rdempty_eq_comp_lsb.aeb);
|
||||
rdemp_eq_comp_lsb_mux.sel[] = valid_rdreq;
|
||||
rdemp_eq_comp_msb_mux.data[] = ( rdempty_eq_comp1_msb.aeb, rdempty_eq_comp_msb.aeb);
|
||||
rdemp_eq_comp_msb_mux.sel[] = valid_rdreq;
|
||||
wrfull_eq_comp_lsb_mux.data[] = ( wrfull_eq_comp1_lsb.aeb, wrfull_eq_comp_lsb.aeb);
|
||||
wrfull_eq_comp_lsb_mux.sel[] = valid_wrreq;
|
||||
wrfull_eq_comp_msb_mux.data[] = ( wrfull_eq_comp1_msb.aeb, wrfull_eq_comp_msb.aeb);
|
||||
wrfull_eq_comp_msb_mux.sel[] = valid_wrreq;
|
||||
int_rdempty = (rdemp_eq_comp_lsb_aeb.q & rdemp_eq_comp_msb_aeb.q);
|
||||
q[] = fifo_ram.q_b[];
|
||||
ram_address_a[] = ( (wrptr_g[8..8].q $ wrptr_g[7..7].q), wrptr_g[6..0].q);
|
||||
ram_address_b[] = ( (rdptr_g1p.q[8..8] $ rdptr_g1p.q[7..7]), rdptr_g1p.q[6..0]);
|
||||
rdempty = int_rdempty;
|
||||
valid_rdreq = rdreq;
|
||||
valid_wrreq = wrreq;
|
||||
wrempty = wrempty_eq_comp.aeb;
|
||||
wrptr_g1s[] = ( (! wrptr_g1p.q[8..8]), (! wrptr_g1p.q[7..7]), wrptr_g1p.q[6..0]);
|
||||
wrptr_gs[] = ( (! wrptr_g[8..8].q), (! wrptr_g[7..7].q), wrptr_g[6..0].q);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
--dffpipe DELAY=2 WIDTH=9 clock d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
|
||||
--VERSION_BEGIN 17.0 cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources = reg 18
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
|
||||
|
||||
SUBDESIGN dffpipe_2v8
|
||||
(
|
||||
clock : input;
|
||||
d[8..0] : input;
|
||||
q[8..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
dffe13a[8..0] : dffe;
|
||||
dffe14a[8..0] : dffe;
|
||||
clrn : NODE;
|
||||
ena : NODE;
|
||||
prn : NODE;
|
||||
sclr : NODE;
|
||||
|
||||
BEGIN
|
||||
dffe13a[].clk = clock;
|
||||
dffe13a[].clrn = clrn;
|
||||
dffe13a[].d = (d[] & (! sclr));
|
||||
dffe13a[].ena = ena;
|
||||
dffe13a[].prn = prn;
|
||||
dffe14a[].clk = clock;
|
||||
dffe14a[].clrn = clrn;
|
||||
dffe14a[].d = (dffe13a[].q & (! sclr));
|
||||
dffe14a[].ena = ena;
|
||||
dffe14a[].prn = prn;
|
||||
clrn = VCC;
|
||||
ena = VCC;
|
||||
prn = VCC;
|
||||
q[] = dffe14a[].q;
|
||||
sclr = GND;
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
--dffpipe DELAY=2 WIDTH=9 clock d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
|
||||
--VERSION_BEGIN 17.0 cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources = reg 18
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
|
||||
|
||||
SUBDESIGN dffpipe_3v8
|
||||
(
|
||||
clock : input;
|
||||
d[8..0] : input;
|
||||
q[8..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
dffe16a[8..0] : dffe;
|
||||
dffe17a[8..0] : dffe;
|
||||
clrn : NODE;
|
||||
ena : NODE;
|
||||
prn : NODE;
|
||||
sclr : NODE;
|
||||
|
||||
BEGIN
|
||||
dffe16a[].clk = clock;
|
||||
dffe16a[].clrn = clrn;
|
||||
dffe16a[].d = (d[] & (! sclr));
|
||||
dffe16a[].ena = ena;
|
||||
dffe16a[].prn = prn;
|
||||
dffe17a[].clk = clock;
|
||||
dffe17a[].clrn = clrn;
|
||||
dffe17a[].d = (dffe16a[].q & (! sclr));
|
||||
dffe17a[].ena = ena;
|
||||
dffe17a[].prn = prn;
|
||||
clrn = VCC;
|
||||
ena = VCC;
|
||||
prn = VCC;
|
||||
q[] = dffe17a[].q;
|
||||
sclr = GND;
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
--dffpipe DELAY=2 WIDTH=9 clock d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
|
||||
--VERSION_BEGIN 17.0 cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources = reg 18
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
|
||||
|
||||
SUBDESIGN dffpipe_4v8
|
||||
(
|
||||
clock : input;
|
||||
d[8..0] : input;
|
||||
q[8..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
dffe4a[8..0] : dffe;
|
||||
dffe5a[8..0] : dffe;
|
||||
clrn : NODE;
|
||||
ena : NODE;
|
||||
prn : NODE;
|
||||
sclr : NODE;
|
||||
|
||||
BEGIN
|
||||
dffe4a[].clk = clock;
|
||||
dffe4a[].clrn = clrn;
|
||||
dffe4a[].d = (d[] & (! sclr));
|
||||
dffe4a[].ena = ena;
|
||||
dffe4a[].prn = prn;
|
||||
dffe5a[].clk = clock;
|
||||
dffe5a[].clrn = clrn;
|
||||
dffe5a[].d = (dffe4a[].q & (! sclr));
|
||||
dffe5a[].ena = ena;
|
||||
dffe5a[].prn = prn;
|
||||
clrn = VCC;
|
||||
ena = VCC;
|
||||
prn = VCC;
|
||||
q[] = dffe5a[].q;
|
||||
sclr = GND;
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
--dffpipe DELAY=2 WIDTH=9 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
|
||||
--VERSION_BEGIN 17.0 cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources = reg 18
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
|
||||
|
||||
SUBDESIGN dffpipe_hd9
|
||||
(
|
||||
clock : input;
|
||||
clrn : input;
|
||||
d[8..0] : input;
|
||||
q[8..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
dffe11a[8..0] : dffe;
|
||||
dffe12a[8..0] : dffe;
|
||||
ena : NODE;
|
||||
prn : NODE;
|
||||
sclr : NODE;
|
||||
|
||||
BEGIN
|
||||
dffe11a[].clk = clock;
|
||||
dffe11a[].clrn = clrn;
|
||||
dffe11a[].d = (d[] & (! sclr));
|
||||
dffe11a[].ena = ena;
|
||||
dffe11a[].prn = prn;
|
||||
dffe12a[].clk = clock;
|
||||
dffe12a[].clrn = clrn;
|
||||
dffe12a[].d = (dffe11a[].q & (! sclr));
|
||||
dffe12a[].ena = ena;
|
||||
dffe12a[].prn = prn;
|
||||
ena = VCC;
|
||||
prn = VCC;
|
||||
q[] = dffe12a[].q;
|
||||
sclr = GND;
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
--dffpipe DELAY=2 WIDTH=12 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
|
||||
--VERSION_BEGIN 17.0 cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources = reg 24
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
|
||||
|
||||
SUBDESIGN dffpipe_re9
|
||||
(
|
||||
clock : input;
|
||||
clrn : input;
|
||||
d[11..0] : input;
|
||||
q[11..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
dffe11a[11..0] : dffe;
|
||||
dffe12a[11..0] : dffe;
|
||||
ena : NODE;
|
||||
prn : NODE;
|
||||
sclr : NODE;
|
||||
|
||||
BEGIN
|
||||
dffe11a[].clk = clock;
|
||||
dffe11a[].clrn = clrn;
|
||||
dffe11a[].d = (d[] & (! sclr));
|
||||
dffe11a[].ena = ena;
|
||||
dffe11a[].prn = prn;
|
||||
dffe12a[].clk = clock;
|
||||
dffe12a[].clrn = clrn;
|
||||
dffe12a[].d = (dffe11a[].q & (! sclr));
|
||||
dffe12a[].ena = ena;
|
||||
dffe12a[].prn = prn;
|
||||
ena = VCC;
|
||||
prn = VCC;
|
||||
q[] = dffe12a[].q;
|
||||
sclr = GND;
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
--dffpipe DELAY=2 WIDTH=12 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
|
||||
--VERSION_BEGIN 17.0 cbx_mgl 2017:04:25:18:09:28:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources = reg 24
|
||||
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
|
||||
|
||||
SUBDESIGN dffpipe_se9
|
||||
(
|
||||
clock : input;
|
||||
clrn : input;
|
||||
d[11..0] : input;
|
||||
q[11..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
dffe4a[11..0] : dffe;
|
||||
dffe5a[11..0] : dffe;
|
||||
ena : NODE;
|
||||
prn : NODE;
|
||||
sclr : NODE;
|
||||
|
||||
BEGIN
|
||||
dffe4a[].clk = clock;
|
||||
dffe4a[].clrn = clrn;
|
||||
dffe4a[].d = (d[] & (! sclr));
|
||||
dffe4a[].ena = ena;
|
||||
dffe4a[].prn = prn;
|
||||
dffe5a[].clk = clock;
|
||||
dffe5a[].clrn = clrn;
|
||||
dffe5a[].d = (dffe4a[].q & (! sclr));
|
||||
dffe5a[].ena = ena;
|
||||
dffe5a[].prn = prn;
|
||||
ena = VCC;
|
||||
prn = VCC;
|
||||
q[] = dffe5a[].q;
|
||||
sclr = GND;
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,59 +0,0 @@
|
|||
--lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone 10 LP" DSP_BLOCK_BALANCING="Auto" INPUT_A_IS_CONSTANT="NO" INPUT_B_IS_CONSTANT="NO" LPM_REPRESENTATION="SIGNED" LPM_WIDTHA=18 LPM_WIDTHB=18 LPM_WIDTHP=36 LPM_WIDTHS=1 MAXIMIZE_SPEED=6 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_mult 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_padd 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cyclone10lp_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb)
|
||||
WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock)
|
||||
RETURNS ( dataout[dataa_width+datab_width-1..0]);
|
||||
FUNCTION cyclone10lp_mac_out (aclr, clk, dataa[dataa_width-1..0], ena)
|
||||
WITH ( dataa_width = 0, output_clock)
|
||||
RETURNS ( dataout[dataa_width-1..0]);
|
||||
|
||||
--synthesis_resources = dsp_9bit 2
|
||||
SUBDESIGN mult_56t
|
||||
(
|
||||
dataa[17..0] : input;
|
||||
datab[17..0] : input;
|
||||
result[35..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
mac_mult1 : cyclone10lp_mac_mult
|
||||
WITH (
|
||||
dataa_clock = "none",
|
||||
dataa_width = 18,
|
||||
datab_clock = "none",
|
||||
datab_width = 18,
|
||||
signa_clock = "none",
|
||||
signb_clock = "none"
|
||||
);
|
||||
mac_out2 : cyclone10lp_mac_out
|
||||
WITH (
|
||||
dataa_width = 36,
|
||||
output_clock = "none"
|
||||
);
|
||||
|
||||
BEGIN
|
||||
mac_mult1.dataa[] = ( dataa[]);
|
||||
mac_mult1.datab[] = ( datab[]);
|
||||
mac_mult1.signa = B"1";
|
||||
mac_mult1.signb = B"1";
|
||||
mac_out2.dataa[] = mac_mult1.dataout[];
|
||||
result[35..0] = mac_out2.dataout[35..0];
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,138 +0,0 @@
|
|||
--lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone 10 LP" DSP_BLOCK_BALANCING="Auto" INPUT_A_IS_CONSTANT="NO" INPUT_B_IS_CONSTANT="YES" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTHA=32 LPM_WIDTHB=31 LPM_WIDTHP=63 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
--VERSION_BEGIN 17.0 cbx_cycloneii 2017:04:25:18:06:29:SJ cbx_lpm_add_sub 2017:04:25:18:06:29:SJ cbx_lpm_mult 2017:04:25:18:06:29:SJ cbx_mgl 2017:04:25:18:09:28:SJ cbx_nadder 2017:04:25:18:06:30:SJ cbx_padd 2017:04:25:18:06:30:SJ cbx_stratix 2017:04:25:18:06:30:SJ cbx_stratixii 2017:04:25:18:06:30:SJ cbx_util_mgl 2017:04:25:18:06:30:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
FUNCTION cyclone10lp_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb)
|
||||
WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock)
|
||||
RETURNS ( dataout[dataa_width+datab_width-1..0]);
|
||||
FUNCTION cyclone10lp_mac_out (aclr, clk, dataa[dataa_width-1..0], ena)
|
||||
WITH ( dataa_width = 0, output_clock)
|
||||
RETURNS ( dataout[dataa_width-1..0]);
|
||||
FUNCTION soft (in)
|
||||
RETURNS ( out);
|
||||
|
||||
--synthesis_resources = dsp_9bit 8 lut 79
|
||||
SUBDESIGN mult_igt
|
||||
(
|
||||
dataa[31..0] : input;
|
||||
datab[30..0] : input;
|
||||
result[62..0] : output;
|
||||
)
|
||||
VARIABLE
|
||||
add13_result[45..0] : WIRE;
|
||||
add9_result[32..0] : WIRE;
|
||||
mac_mult1 : cyclone10lp_mac_mult
|
||||
WITH (
|
||||
dataa_clock = "none",
|
||||
dataa_width = 18,
|
||||
datab_clock = "none",
|
||||
datab_width = 18,
|
||||
signa_clock = "none",
|
||||
signb_clock = "none"
|
||||
);
|
||||
mac_mult3 : cyclone10lp_mac_mult
|
||||
WITH (
|
||||
dataa_clock = "none",
|
||||
dataa_width = 18,
|
||||
datab_clock = "none",
|
||||
datab_width = 13,
|
||||
signa_clock = "none",
|
||||
signb_clock = "none"
|
||||
);
|
||||
mac_mult5 : cyclone10lp_mac_mult
|
||||
WITH (
|
||||
dataa_clock = "none",
|
||||
dataa_width = 14,
|
||||
datab_clock = "none",
|
||||
datab_width = 18,
|
||||
signa_clock = "none",
|
||||
signb_clock = "none"
|
||||
);
|
||||
mac_mult7 : cyclone10lp_mac_mult
|
||||
WITH (
|
||||
dataa_clock = "none",
|
||||
dataa_width = 14,
|
||||
datab_clock = "none",
|
||||
datab_width = 13,
|
||||
signa_clock = "none",
|
||||
signb_clock = "none"
|
||||
);
|
||||
mac_out2 : cyclone10lp_mac_out
|
||||
WITH (
|
||||
dataa_width = 36,
|
||||
output_clock = "none"
|
||||
);
|
||||
mac_out4 : cyclone10lp_mac_out
|
||||
WITH (
|
||||
dataa_width = 31,
|
||||
output_clock = "none"
|
||||
);
|
||||
mac_out6 : cyclone10lp_mac_out
|
||||
WITH (
|
||||
dataa_width = 32,
|
||||
output_clock = "none"
|
||||
);
|
||||
mac_out8 : cyclone10lp_mac_out
|
||||
WITH (
|
||||
dataa_width = 27,
|
||||
output_clock = "none"
|
||||
);
|
||||
sft10a[32..0] : soft;
|
||||
sft11a[32..0] : soft;
|
||||
sft12a[32..0] : soft;
|
||||
sft14a[45..0] : soft;
|
||||
sft15a[45..0] : soft;
|
||||
sft16a[45..0] : soft;
|
||||
w252w : WIRE;
|
||||
w507w[63..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
add13_result[] = sft14a[].out + sft15a[].out;
|
||||
add9_result[] = sft10a[].out + sft11a[].out;
|
||||
mac_mult1.dataa[] = ( dataa[17..0]);
|
||||
mac_mult1.datab[] = ( datab[17..0]);
|
||||
mac_mult1.signa = B"0";
|
||||
mac_mult1.signb = B"0";
|
||||
mac_mult3.dataa[] = ( dataa[17..0]);
|
||||
mac_mult3.datab[] = ( datab[30..18]);
|
||||
mac_mult3.signa = B"0";
|
||||
mac_mult3.signb = B"0";
|
||||
mac_mult5.dataa[] = ( dataa[31..18]);
|
||||
mac_mult5.datab[] = ( datab[17..0]);
|
||||
mac_mult5.signa = B"0";
|
||||
mac_mult5.signb = B"0";
|
||||
mac_mult7.dataa[] = ( dataa[31..18]);
|
||||
mac_mult7.datab[] = ( datab[30..18]);
|
||||
mac_mult7.signa = B"0";
|
||||
mac_mult7.signb = B"0";
|
||||
mac_out2.dataa[] = mac_mult1.dataout[];
|
||||
mac_out4.dataa[] = mac_mult3.dataout[];
|
||||
mac_out6.dataa[] = mac_mult5.dataout[];
|
||||
mac_out8.dataa[] = mac_mult7.dataout[];
|
||||
sft10a[].in = ( w252w, ( mac_out6.dataout[31..31], ( mac_out8.dataout[12..12], ( mac_out8.dataout[11..11], ( mac_out8.dataout[10..10], ( mac_out8.dataout[9..9], ( mac_out8.dataout[8..8], ( mac_out8.dataout[7..7], ( mac_out8.dataout[6..6], ( mac_out8.dataout[5..5], ( mac_out8.dataout[4..4], ( mac_out8.dataout[3..3], ( mac_out8.dataout[2..2], ( mac_out8.dataout[1..1], ( mac_out8.dataout[0..0], ( mac_out6.dataout[17..17], ( mac_out6.dataout[16..16], ( mac_out6.dataout[15..15], ( mac_out6.dataout[14..14], ( mac_out6.dataout[13..13], ( mac_out6.dataout[12..12], ( mac_out6.dataout[11..11], ( mac_out6.dataout[10..10], ( mac_out6.dataout[9..9], ( mac_out6.dataout[8..8], ( mac_out6.dataout[7..7], ( mac_out6.dataout[6..6], ( mac_out6.dataout[5..5], ( mac_out6.dataout[4..4], ( mac_out6.dataout[3..3], ( mac_out6.dataout[2..2], ( mac_out6.dataout[1..0]))))))))))))))))))))))))))))))));
|
||||
sft11a[].in = ( w252w, ( w252w, ( mac_out6.dataout[30..30], ( mac_out6.dataout[29..29], ( mac_out6.dataout[28..28], ( mac_out6.dataout[27..27], ( mac_out6.dataout[26..26], ( mac_out6.dataout[25..25], ( mac_out6.dataout[24..24], ( mac_out6.dataout[23..23], ( mac_out6.dataout[22..22], ( mac_out6.dataout[21..21], ( mac_out6.dataout[20..20], ( mac_out6.dataout[19..19], ( mac_out6.dataout[18..18], ( mac_out4.dataout[17..17], ( mac_out4.dataout[16..16], ( mac_out4.dataout[15..15], ( mac_out4.dataout[14..14], ( mac_out4.dataout[13..13], ( mac_out4.dataout[12..12], ( mac_out4.dataout[11..11], ( mac_out4.dataout[10..10], ( mac_out4.dataout[9..9], ( mac_out4.dataout[8..8], ( mac_out4.dataout[7..7], ( mac_out4.dataout[6..6], ( mac_out4.dataout[5..5], ( mac_out4.dataout[4..4], ( mac_out4.dataout[3..3], ( mac_out4.dataout[2..2], ( mac_out4.dataout[1..0]))))))))))))))))))))))))))))))));
|
||||
sft12a[].in = add9_result[];
|
||||
sft14a[].in = ( w252w, ( mac_out8.dataout[26..26], ( mac_out8.dataout[25..25], ( mac_out8.dataout[24..24], ( mac_out8.dataout[23..23], ( mac_out8.dataout[22..22], ( mac_out8.dataout[21..21], ( mac_out8.dataout[20..20], ( mac_out8.dataout[19..19], ( mac_out8.dataout[18..18], ( mac_out8.dataout[17..17], ( mac_out8.dataout[16..16], ( mac_out8.dataout[15..15], ( mac_out8.dataout[14..14], ( mac_out8.dataout[13..13], ( mac_out4.dataout[30..30], ( mac_out4.dataout[29..29], ( mac_out4.dataout[28..28], ( mac_out4.dataout[27..27], ( mac_out4.dataout[26..26], ( mac_out4.dataout[25..25], ( mac_out4.dataout[24..24], ( mac_out4.dataout[23..23], ( mac_out4.dataout[22..22], ( mac_out4.dataout[21..21], ( mac_out4.dataout[20..20], ( mac_out4.dataout[19..19], ( mac_out4.dataout[18..18], ( mac_out2.dataout[35..35], ( mac_out2.dataout[34..34], ( mac_out2.dataout[33..33], ( mac_out2.dataout[32..32], ( mac_out2.dataout[31..31], ( mac_out2.dataout[30..30], ( mac_out2.dataout[29..29], ( mac_out2.dataout[28..28], ( mac_out2.dataout[27..27], ( mac_out2.dataout[26..26], ( mac_out2.dataout[25..25], ( mac_out2.dataout[24..24], ( mac_out2.dataout[23..23], ( mac_out2.dataout[22..22], ( mac_out2.dataout[21..21], ( mac_out2.dataout[20..20], ( mac_out2.dataout[19..18])))))))))))))))))))))))))))))))))))))))))))));
|
||||
sft15a[].in = ( w252w, ( w252w, ( w252w, ( w252w, ( w252w, ( w252w, ( w252w, ( w252w, ( w252w, ( w252w, ( w252w, ( w252w, ( w252w, ( sft12a[32..32].out, ( sft12a[31..31].out, ( sft12a[30..30].out, ( sft12a[29..29].out, ( sft12a[28..28].out, ( sft12a[27..27].out, ( sft12a[26..26].out, ( sft12a[25..25].out, ( sft12a[24..24].out, ( sft12a[23..23].out, ( sft12a[22..22].out, ( sft12a[21..21].out, ( sft12a[20..20].out, ( sft12a[19..19].out, ( sft12a[18..18].out, ( sft12a[17..17].out, ( sft12a[16..16].out, ( sft12a[15..15].out, ( sft12a[14..14].out, ( sft12a[13..13].out, ( sft12a[12..12].out, ( sft12a[11..11].out, ( sft12a[10..10].out, ( sft12a[9..9].out, ( sft12a[8..8].out, ( sft12a[7..7].out, ( sft12a[6..6].out, ( sft12a[5..5].out, ( sft12a[4..4].out, ( sft12a[3..3].out, ( sft12a[2..2].out, ( sft12a[1..1].out, sft12a[0..0].out)))))))))))))))))))))))))))))))))))))))))))));
|
||||
sft16a[].in = add13_result[];
|
||||
result[62..0] = w507w[62..0];
|
||||
w252w = B"0";
|
||||
w507w[] = ( sft16a[45..44].out, sft16a[43..42].out, sft16a[41..40].out, sft16a[39..38].out, sft16a[37..36].out, sft16a[35..34].out, sft16a[33..32].out, sft16a[31..30].out, sft16a[29..28].out, sft16a[27..26].out, sft16a[25..24].out, sft16a[23..22].out, sft16a[21..20].out, sft16a[19..18].out, sft16a[17..16].out, sft16a[15..14].out, sft16a[13..12].out, sft16a[11..10].out, sft16a[9..8].out, sft16a[7..6].out, sft16a[5..4].out, sft16a[3..2].out, sft16a[1..0].out, mac_out2.dataout[17..17], mac_out2.dataout[16..16], mac_out2.dataout[15..15], mac_out2.dataout[14..14], mac_out2.dataout[13..13], mac_out2.dataout[12..12], mac_out2.dataout[11..11], mac_out2.dataout[10..10], mac_out2.dataout[9..9], mac_out2.dataout[8..8], mac_out2.dataout[7..7], mac_out2.dataout[6..6], mac_out2.dataout[5..5], mac_out2.dataout[4..4], mac_out2.dataout[3..3], mac_out2.dataout[2..2], mac_out2.dataout[1..1], mac_out2.dataout[0..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
--lpm_mux DEVICE_FAMILY="Cyclone 10 LP" LPM_SIZE=2 LPM_WIDTH=1 LPM_WIDTHS=1 data result sel
|
||||
--VERSION_BEGIN 17.0 cbx_lpm_mux 2017:04:25:18:06:30:SJ cbx_mgl 2017:04:25:18:09:28:SJ VERSION_END
|
||||
|
||||
|
||||
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel MegaCore Function License Agreement, or other
|
||||
-- applicable license agreement, including, without limitation,
|
||||
-- that your use is for the sole purpose of programming logic
|
||||
-- devices manufactured by Intel and sold by Intel or its
|
||||
-- authorized distributors. Please refer to the applicable
|
||||
-- agreement for further details.
|
||||
|
||||
|
||||
|
||||
--synthesis_resources = lut 1
|
||||
SUBDESIGN mux_c28
|
||||
(
|
||||
data[1..0] : input;
|
||||
result[0..0] : output;
|
||||
sel[0..0] : input;
|
||||
)
|
||||
VARIABLE
|
||||
result_node[0..0] : WIRE;
|
||||
sel_node[0..0] : WIRE;
|
||||
w_data377w[1..0] : WIRE;
|
||||
|
||||
BEGIN
|
||||
result[] = result_node[];
|
||||
result_node[] = ( ((sel_node[] & w_data377w[1..1]) # ((! sel_node[]) & w_data377w[0..0])));
|
||||
sel_node[] = ( sel[0..0]);
|
||||
w_data377w[] = ( data[1..0]);
|
||||
END;
|
||||
--VALID FILE
|
||||
File diff suppressed because one or more lines are too long
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Some files were not shown because too many files have changed in this diff Show More
Ładowanie…
Reference in New Issue