kopia lustrzana https://github.com/mikaelnousiainen/RS41ng
Fixed Si4032 buffer issues for CATS
rodzic
a09c1a4f6b
commit
ac29ed8c7c
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@ -54,12 +54,21 @@ void si4032_disable_tx()
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// If less than len, remaining bytes will need to be used to top up the buffer
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uint16_t si4032_start_tx(uint8_t *data, int len)
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{
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const uint8_t buffer_size = 64;
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// No TX header
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// Fixed packet length (don't transmit length)
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si4032_write(0x33, 0b00001000);
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// set almost full threshold to 60
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si4032_write(0x7C, 60);
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// Clear fifo
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si4032_write(0x08, 1);
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si4032_write(0x08, 0);
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// set almost full threshold to buffer_size
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si4032_write(0x7C, buffer_size);
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// set almost empty threshold
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si4032_write(0x7D, 16);
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// enable interrupts
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si4032_write(0x05, 0b11100100);
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@ -73,14 +82,10 @@ uint16_t si4032_start_tx(uint8_t *data, int len)
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// Set packet length (max 255 bytes)
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si4032_write(0x3E, len);
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// Clear fifo
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si4032_write(0x08, 1);
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si4032_write(0x08, 0);
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// Fill our FIFO
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int fifo_len = len;
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if(fifo_len > 48) {
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fifo_len = 48;
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if(fifo_len > buffer_size) {
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fifo_len = buffer_size;
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}
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for(int i = 0; i < fifo_len; i++) {
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si4032_write(0x7F, data[i]);
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@ -99,26 +104,19 @@ uint16_t si4032_start_tx(uint8_t *data, int len)
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// If less than len, you will need to keep calling this
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uint16_t si4032_refill_buffer(uint8_t *data, int len, bool *overflow)
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{
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uint8_t interrupts = si4032_read(0x03);
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uint8_t interrupts;
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int i = 0;
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// check for free buffer space
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// TX FIFO almost full
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while (!(interrupts & 0x40) && i < len) {
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// check for FIFO underflow
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if (interrupts & 0x80) {
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*overflow = true;
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return i;
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}
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si4032_write(0x7F, data[i]);
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while(i < len){
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do {
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si4032_write(0x7F, data[i]);
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i++;
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delay_us(10);
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interrupts = si4032_read(0x03);
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i++;
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}
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interrupts = si4032_read(0x03);
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} while ((interrupts & 0x20) && i < len);
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if (interrupts & 0x80) {
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*overflow = true;
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delay_us(500);
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}
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return i;
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@ -167,7 +165,10 @@ void si4032_set_tx_frequency(const float frequency_mhz)
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void si4032_set_data_rate(const uint32_t rate_bps)
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{
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uint32_t rate = (uint64_t) rate_bps * (1 << 21) * EXPECTED_SI4032_CLOCK / 1000000 / ((uint64_t) SI4032_CLOCK);
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uint32_t rate = (uint64_t) rate_bps * (1 << 21) * EXPECTED_SI4032_CLOCK / 1000000 / SI4032_CLOCK;
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log_info("Rate BPS: %lu\n", rate_bps);
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log_info("Rate (raw): %lu\n", rate);
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si4032_write(0x6E, rate >> 8);
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si4032_write(0x6F, rate & 0xFF);
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@ -225,26 +225,13 @@ void radio_handle_fifo_si4032(radio_transmit_entry *entry, radio_module_state *s
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uint8_t *data = fsk_encoder_api->get_data(fsk_enc);
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uint16_t len = fsk_encoder_api->get_data_len(fsk_enc);
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bool overflow = false;
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uint16_t written = si4032_start_tx(data, len);
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data += written;
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len -= written;
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bool overflow = false;
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while(len > 0) {
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uint16_t written = si4032_refill_buffer(data, len, &overflow);
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data += written;
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len -= written;
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// log_info("FIFO wrote %d bytes\n", written);
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/*if(overflow) {
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log_info("FIFO underflow - Aborting\n");
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shared_state->radio_transmission_finished = true;
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return;
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}*/
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}
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si4032_refill_buffer(data, len, &overflow);
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int err = si4032_wait_for_tx_complete(500);
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if(err != HAL_OK) {
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