kopia lustrzana https://github.com/oddwires/RP2040-code
78 wiersze
6.6 KiB
C
78 wiersze
6.6 KiB
C
#pragma once
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//#define NewHardware // Comment/Uncomment to select active GPIO ports
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#ifdef NewHardware
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Define GPIO connections for Pico (new hardware)...
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Phase lock:
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// Read/Write through serial port does not use DMA channels. This removes most DAC channels jitter at
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// high frequencies.
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// 1 Hz => 900 KHz - Phase sync stable
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// 900 KHz => 1 MHz - Phase sync usable - random drifting easily corrected by hitting 'return'
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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#define SPI_PORT spi1 // Using SPI port 1
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// ┌──────────┬───────────────┬─────────────┐────────────────┐
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// │ PGA2040 │ Connection │ MCP41010 │ Display module │
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// ├──────────┼───────────────┼─────────────┤────────────────┤
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#define PIN_RX 12 // │ GPIO 12 │ SPI1 RX │ (unused) │ (unused) │
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#define Display_CS 26 // │ GPIO 17 │ Chip select │ (unused) │ SS1 (white) │
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#define PIN_CLK 10 // │ GPIO 10 │ SPI1 Clock │ SCK (Pin 2) │ SCK (blue) │
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#define PIN_TX 11 // │ GPIO 11 │ SPI1 TX │ SI (Pin 3) │ SDI (green) │
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#define Level_CS 22 // │ GPIO 22 │ Chip select │ CS (Pin 1) │ (unused) │
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// └──────────┴───────────────┴─────────────┘────────────────┘
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#define DAC_A_Start 2 // First GPIO port used by DAC A
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#define DAC_B_Start 14 // First GPIO port used by DAC B
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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#else
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Define GPIO connections for Pico (Module)...
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Phase lock:
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// Read/Write through USB serial port requires DMA channel usage. This makes the DAC channels jitter at
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// high frequencies and causes phase sync issues.
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// 1 Hz => 250 KHz - Phase sync stable
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// 250 KHz => 750 KHz - Phase sync usable - some drifting noticable when using USB serial input
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// 750 KHz => 1 MHz - Phase sync unusable - random drifting
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//
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// Note: 1) The SPI Port only works through specific pins, so these connections are defined first.
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// 2) Pin assignments prevent the use of the UART for this configuration.
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// SPI Port connections...
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#define SPI_PORT spi0 // Using SPI port 0
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// ┌──────────┬───────────────┬─────────────┐────────────────┐
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// │ PGA2040 │ Connection │ MCP41010 │ Display module │
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// ├──────────┼───────────────┼─────────────┤────────────────┤
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#define PIN_RX 16 // │ GPIO 16 │ SPI0 RX │ (unused) │ (unused) │
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#define Display_CS 17 // │ GPIO 17 │ Chip select │ (unused) │ SS1 (white) │
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#define PIN_CLK 18 // │ GPIO 18 │ SPI0 Clock │ SCK (Pin 2) │ SCK (blue) │
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#define PIN_TX 19 // │ GPIO 19 │ SPI0 TX │ SI (Pin 3) │ SDI (green) │
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#define Level_CS 20 // │ GPIO 20 │ Chip select │ CS (Pin 1) │ (unused) │
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// └──────────┴───────────────┴─────────────┘────────────────┘
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#define DAC_A_Start 0 // First GPIO port used by DAC A
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#define DAC_B_Start 8 // First GPIO port used by DAC B
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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#endif
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// Definitions common to either hardware...
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#define _DAC_A 0 // DAC channel alias
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#define _DAC_B 1 // DAC channel alias
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#define _Funct_ 2
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#define _Phase_ 3
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#define _Duty_ 4
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#define _Range_ 5
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#define _Harmonic_ 10
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#define _PIOnum_ pio0 // Code will work equally well on either pio0 or pio1
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#define eof 255 // EOF in stdio.h -is -1, but getchar returns int 255 to avoid blocking
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#define CR 13
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#define MWidth 12 // Width of terminal command margin (in columns)
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// Define clock speed...
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//#define SysClock 125 // System clock for 0.488 MHz DAC output (Pico default)
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//#define SysClock 250 // System clock x 2 for 0.977 MHz DAC output
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#define SysClock 280 // Overclock for 1.000 MHz DAC output
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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