kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
306 wiersze
12 KiB
Plaintext
306 wiersze
12 KiB
Plaintext
1. Original design:
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 27/54 69/90 6/ 9
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FB2 18/18* 34/54 60/90 8/ 9
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FB3 18/18* 19/54 32/90 5/ 9
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FB4 18/18* 37/54 56/90 7/ 7*
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----- ----- ----- -----
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72/72 117/216 217/360 26/34
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2. New design, with RGB mux, switch pass throughs, etc commented out
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(failed to map sp_reg<9>, hence one less macrocell)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 26/54 51/90 7/ 9
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FB2 18/18* 25/54 33/90 6/ 9
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FB3 18/18* 35/54 61/90 8/ 9
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FB4 17/18 53/54 70/90 4/ 7
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----- ----- ----- -----
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71/72 139/216 215/360 25/34
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3. Change from csync=>S to csync=>CSYNC1 (as passthroughs still use up a macro cell).
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(now fits)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 17/18 33/54 64/90 7/ 9
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FB2 18/18* 25/54 33/90 6/ 9
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FB3 18/18* 35/54 61/90 8/ 9
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FB4 18/18* 37/54 58/90 4/ 7
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----- ----- ----- -----
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71/72 130/216 216/360 25/34
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4. Add in RGB mux:
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(still fits)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 17/18 33/54 64/90 7/ 9
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FB2 18/18* 25/54 33/90 9/ 9*
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FB3 18/18* 37/54 61/90 8/ 9
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FB4 18/18* 41/54 61/90 5/ 7
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----- ----- ----- -----
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71/72 136/216 219/360 29/34
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5. Add in SW2out <= SW2:
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(still fits)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 28/54 62/90 8/ 9
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FB2 18/18* 25/54 33/90 9/ 9*
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FB3 18/18* 37/54 61/90 8/ 9
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FB4 18/18* 48/54 64/90 6/ 7
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----- ----- ----- -----
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72/72 138/216 220/360 31/34
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6. Change to optimization effort normal->high:
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(no difference)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 28/54 62/90 8/ 9
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FB2 18/18* 25/54 33/90 9/ 9*
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FB3 18/18* 37/54 61/90 8/ 9
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FB4 18/18* 48/54 64/90 6/ 7
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----- ----- ----- -----
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72/72 138/216 220/360 31/34
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7. Change to optimization effort speed->area:
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(no difference)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 28/54 62/90 8/ 9
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FB2 18/18* 25/54 33/90 9/ 9*
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FB3 18/18* 37/54 61/90 8/ 9
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FB4 18/18* 48/54 64/90 6/ 7
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----- ----- ----- -----
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72/72 138/216 220/360 31/34
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8. Fitter Implmenetation Template: Optimize Balance-> Optimize Speed:
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(no difference)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 28/54 62/90 8/ 9
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FB2 18/18* 25/54 33/90 9/ 9*
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FB3 18/18* 37/54 61/90 8/ 9
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FB4 18/18* 48/54 64/90 6/ 7
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----- ----- ----- -----
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72/72 138/216 220/360 31/34
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9. Fitter Implmenetation Template: Optimize Speed -> Optimize Density:
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(no difference)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 28/54 62/90 8/ 9
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FB2 18/18* 25/54 33/90 9/ 9*
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FB3 18/18* 37/54 61/90 8/ 9
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FB4 18/18* 48/54 64/90 6/ 7
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----- ----- ----- -----
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72/72 138/216 220/360 31/34
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10. Reverted to original .xise file
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Cleaned up design to remove SW2/3 pass throughs
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Used gpio22/23 for mode7 / sp_data
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Used gpio19/26 for sw2/3 (not via cpld)
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(same result as 4 above)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 17/18 33/54 64/90 5/ 9
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FB2 18/18* 25/54 33/90 9/ 9*
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FB3 18/18* 37/54 61/90 8/ 9
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FB4 18/18* 41/54 61/90 7/ 7*
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----- ----- ----- -----
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71/72 136/216 219/360 29/34
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11. Final design on 5/6/2018
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(Added SW2, SW3, Link as unused inputs)
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(Added LED1 as output, driven to Z, still uses one macro cell)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 27/54 61/90 5/ 9
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FB2 18/18* 25/54 33/90 9/ 9*
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FB3 18/18* 37/54 61/90 9/ 9*
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FB4 18/18* 48/54 64/90 7/ 7*
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----- ----- ----- -----
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72/72 137/216 219/360 30/34
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12. Minor changes 1.15pm on 5/5/2018
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(Removed SW1Out passthrough)
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(csync output is back to being passthrough)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 25/54 35/90 4/ 9
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FB2 18/18* 34/54 65/90 9/ 9*
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FB3 18/18* 37/54 61/90 9/ 9*
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FB4 18/18* 39/54 58/90 7/ 7*
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----- ----- ----- -----
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72/72 135/216 219/360 29/34
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13. Removed SW1 from sp_reg assignment block
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(the is prone to noise on the prototype, as it clamped at 2V by an LED)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 25/54 35/90 3/ 9
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FB2 18/18* 34/54 65/90 9/ 9*
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FB3 18/18* 37/54 61/90 9/ 9*
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FB4 18/18* 39/54 58/90 7/ 7*
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----- ----- ----- -----
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72/72 135/216 219/360 28/34
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14. Added sp_clken and spare
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 30/54 63/90 5/ 9
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FB2 18/18* 26/54 46/90 9/ 9*
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FB3 18/18* 35/54 60/90 8/ 9
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FB4 18/18* 47/54 71/90 7/ 7*
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----- ----- ----- -----
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72/72 138/216 240/360 29/34
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15. Replaced counter2(5..3) with load saving two registers
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 40/54 72/90 5/ 9
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FB2 17/18 24/54 49/90 9/ 9*
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FB3 18/18* 34/54 60/90 8/ 9
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FB4 17/18 35/54 63/90 7/ 7*
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----- ----- ----- -----
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70/72 133/216 244/360 29/34
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16. Alternative design
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(after lots of messing to get it to route)
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(timing rubbush, 18ns)
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(68 registers)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 34/54 53/90 4/ 9
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FB2 18/18* 26/54 36/90 8/ 9
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FB3 18/18* 30/54 50/90 9/ 9*
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FB4 16/18 38/54 86/90 6/ 7
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----- ----- ----- -----
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70/72 128/216 225/360 27/34
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17. Repipelined offset and alternative_counter to improve timing
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(note big reduction in product term usage)
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(70 registers)
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(11.0ns)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 35/54 45/90 4/ 9
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FB2 17/18 25/54 35/90 8/ 9
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FB3 18/18* 30/54 50/90 9/ 9*
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FB4 18/18* 42/54 66/90 6/ 7
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----- ----- ----- -----
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71/72 132/216 196/360 27/34
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18. Sign extended offset to 3-bits
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(surprisingly no change in resource usage)
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(70 registers)
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(11.0ns)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 35/54 45/90 4/ 9
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FB2 17/18 25/54 35/90 8/ 9
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FB3 18/18* 30/54 50/90 9/ 9*
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FB4 18/18* 42/54 66/90 6/ 7
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----- ----- ----- -----
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71/72 132/216 196/360 27/34
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19. Adjust pipelining timing
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(sp_index when counter = 6 rather than 7)
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(load when counter = 1 rather than 1)
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(70 registers)
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(11.0ns)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 35/54 45/90 4/ 9
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FB2 17/18 25/54 35/90 8/ 9
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FB3 18/18* 30/54 50/90 9/ 9*
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FB4 18/18* 42/54 66/90 6/ 7
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----- ----- ----- -----
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71/72 132/216 196/360 27/34
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20. Added CPLD version output on Quad()
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 33/54 45/90 5/ 9
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FB2 17/18 26/54 36/90 8/ 9
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FB3 18/18* 30/54 58/90 9/ 9*
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FB4 18/18* 47/54 70/90 6/ 7
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----- ----- ----- -----
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71/72 136/216 209/360 28/34
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21. Added configurable half-pixel delay
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 33/54 45/90 5/ 9
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FB2 18/18* 27/54 38/90 8/ 9
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FB3 18/18* 31/54 62/90 9/ 9*
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FB4 18/18* 49/54 71/90 6/ 7
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----- ----- ----- -----
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72/72 140/216 216/360 28/34
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22. Final pinout changes - remove LED1 and LED2 as outputs
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(actually there was no change here, as the assignments to LED1/2 were always commented out)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 33/54 45/90 6/ 9
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FB2 18/18* 27/54 38/90 8/ 9
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FB3 18/18* 31/54 62/90 9/ 9*
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FB4 18/18* 49/54 71/90 5/ 7
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----- ----- ----- -----
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72/72 140/216 216/360 28/34
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23. Made csync output registered
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 33/54 45/90 6/ 9
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FB2 18/18* 27/54 38/90 8/ 9
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FB3 18/18* 31/54 62/90 9/ 9*
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FB4 17/18 49/54 70/90 5/ 7
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----- ----- ----- -----
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71/72 140/216 215/360 28/34
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24. De-glitch csync (one additional register)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 32/54 43/90 6/ 9
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FB2 18/18* 27/54 38/90 8/ 9
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FB3 18/18* 29/54 76/90 9/ 9*
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FB4 18/18* 49/54 75/90 5/ 7
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----- ----- ----- -----
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72/72 137/216 232/360 28/34
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