kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
174 wiersze
4.6 KiB
Plaintext
174 wiersze
4.6 KiB
Plaintext
This chapter documents the Backend for the PowerPC microprocessor family.
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@section Legal
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This module is written in 2002-2016 by Frank Wille and
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is covered by the vasm copyright without modifications.
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@section Additional options for this module
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This module provides the following additional options:
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@table @option
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@item -big
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Select big-endian mode.
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@item -little
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Select little-endian mode.
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@item -many
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Allow both, 32- and 64-bit instructions.
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@item -mavec, -maltivec
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Generate code for the Altivec unit.
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@item -mcom
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Allow only common PPC instructions.
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@item -m601
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Generate code for the PPC 601.
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@item -mppc32, -mppc, -m603, -m604
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Generate code for the 32-bit PowerPC 6xx family.
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@item -mppc64, -m620
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Generate code for the 64-bit PowerPC 600 family.
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@item -m7400, -m7410, -m7455
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Generate code for the 32-bit PowerPC 74xx (G4) family.
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@item -m7450
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Generate code for the 32-bit PowerPC 7450.
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@item -m403, -m405
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Generate code for the IBM/AMCC 32-bit embedded 40x family.
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@item -m440, -m460
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Generate code for the AMCC 32-bit embedded 440/460 family.
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@item -m821, -m850, -m860
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Generate code for the 32-bit MPC8xx PowerQUICC I family.
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@item -mbooke
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Generate code for the 32-bit Book-E architecture.
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@item -me300
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Generate code for the 32-bit e300 core (MPC51xx, MPC52xx, MPC83xx).
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@item -me500
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Generate code for the 32-bit e500 core (MPC85xx), including SPE,
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EFS and PMR.
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@item -mpwr
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Generate code for the POWER family.
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@item -mpwrx, -mpwr2
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Generate code for the POWER2 family.
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@item -no-regnames
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Don't predefine any register-name symbols.
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@item -opt-branch
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Enables translation of 16-bit branches into
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"B<!cc> $+8 ; B label" sequences when destination is out of range.
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@item -sd2reg=<n>
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Sets the 2nd small data base register to @code{Rn}.
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@item -sdreg=<n>
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Sets small data base register to @code{Rn}.
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@end table
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The default setting is to generate code for a 32-bit PPC G2, G3, G4 CPU
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with Altivec support.
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@section General
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This backend accepts PowerPC instructions as described in the
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instruction set manuals from IBM, Motorola, Freescale and AMCC.
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The full instruction set of the following families is supported:
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POWER, POWER2, 40x, 44x, 46x, 60x, 620, 750, 74xx, 860, Book-E,
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e300 and e500.
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The target address type is 32 or 64 bits, depending on the selected
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CPU model. Floating point constants in instructions and data are
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supported and encoded in IEEE format.
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Default alignment for sections and instructions is 4 bytes. Data is
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aligned to its natural alignment by default.
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@section Extensions
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This backend provides the following specific extensions:
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@itemize @minus
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@item When not disabled by the option @code{-no-regnames}, the registers r0 - r31,
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f0 - f31, v0 - v31, cr0 - cr7, vrsave, sp, rtoc, fp, fpscr, xer, lr, ctr,
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and the symbols lt, gt, so and un will be predefined on startup and may
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be referenced by the program.
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@end itemize
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This backend extends the selected syntax module by the following
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directives:
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@table @code
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@item .sdreg <n>
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Sets the small data base register to @code{Rn}.
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@item .sd2reg <n>
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Sets the 2nd small data base register to @code{Rn}.
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@end table
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@section Optimizations
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This backend performs the following optimizations:
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@itemize @minus
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@item 16-bit branches, where the destination is out of range, are translated
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into @code{B<!cc> $+8} and a 26-bit unconditional branch.
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@end itemize
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@section Known Problems
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Some known problems of this module at the moment:
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@itemize @minus
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@item No real differentiation between 403, 750, 860 instructions
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at the moment.
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@item There may still be some unsupported PPC models.
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@end itemize
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@section Error Messages
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This module has the following error messages:
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@itemize @minus
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@item 2002: instruction not supported on selected architecture
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@item 2003: constant integer expression required
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@item 2004: trailing garbage in operand
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@item 2005: illegal operand type
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@item 2006: missing closing parenthesis in load/store addressing mode
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@item 2007: relocation does not allow hi/lo modifier
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@item 2008: multiple relocation attributes
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@item 2009: multiple hi/lo modifiers
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@item 2010: data size %d not supported
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@item 2011: data has illegal type
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@item 2012: relocation attribute not supported by operand
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@item 2013: operand out of range: %ld (allowed: %ld to %ld)
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@item 2014: not a valid register (0-31)
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@item 2015: missing base register in load/store addressing mode
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@item 2016: missing mandatory operand
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@item 2017: ignoring fake operand
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@end itemize
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