kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
408 wiersze
16 KiB
VHDL
408 wiersze
16 KiB
VHDL
----------------------------------------------------------------------------------
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-- Engineer: David Banks
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--
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-- Create Date: 15/7/2018
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-- Module Name: RGBtoHDMI CPLD
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-- Project Name: RGBtoHDMI
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-- Target Devices: XC9572XL
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--
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-- Version: 1.0
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--
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity RGBtoHDMI is
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Port (
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-- From RGB Connector
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R3_I: in std_logic;
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G3_I: in std_logic;
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B3_I: in std_logic;
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R2_I: in std_logic;
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G2_I: in std_logic;
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B2_I: in std_logic;
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R1_I: in std_logic;
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G1_I: in std_logic;
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B1_I: in std_logic;
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R0_I: in std_logic;
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G0_I: in std_logic;
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B0_I: in std_logic;
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csync_I: in std_logic;
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vsync_I: in std_logic;
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analog: inout std_logic;
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-- From Pi
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clk: in std_logic;
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sp_clk: in std_logic;
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sp_clken: in std_logic;
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sp_data: in std_logic;
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-- To PI GPIO
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quad: out std_logic_vector(11 downto 0);
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psync: out std_logic;
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csync: out std_logic;
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-- User interface
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version: in std_logic
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);
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end RGBtoHDMI;
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architecture Behavorial of RGBtoHDMI is
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subtype counter_type is unsigned(6 downto 0);
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-- Version number: Design_Major_Minor
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-- Design: 0 = BBC CPLD
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-- 1 = Alternative CPLD
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-- 2 = Atom CPLD
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-- 3 = six bit CPLD (if required);
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-- 4 = RGB CPLD (TTL)
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-- C = RGB CPLD (Analog)
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constant VERSION_NUM_RGB_TTL : std_logic_vector(11 downto 0) := x"485";
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constant VERSION_NUM_RGB_ANALOG : std_logic_vector(11 downto 0) := x"C85";
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-- Sampling points
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constant INIT_SAMPLING_POINTS : std_logic_vector(25 downto 0) := "00000000011011011011011011";
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signal shift_R : std_logic_vector(3 downto 0);
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signal shift_G : std_logic_vector(3 downto 0);
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signal shift_B : std_logic_vector(3 downto 0);
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signal csync1 : std_logic;
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signal csync2 : std_logic;
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signal last : std_logic;
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signal csync_counter : unsigned(1 downto 0);
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-- The sampling counter runs at 96MHz
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-- - In modes 0..6 it is 6x the pixel clock
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-- - In mode 7 it is 8x the pixel clock
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--
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-- It serves several purposes:
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-- 1. Counts the 12us between the rising edge of nCSYNC and the first pixel
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-- 2. Counts within each pixel (bits 0, 1, 2)
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-- 3. Counts counts pixels within a quad pixel (bits 3 and 4)
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-- 4. Handles double buffering of alternative quad pixels (bit 5)
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--
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-- At the moment we don't count pixels with the line, the Pi does that
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signal counter : counter_type;
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-- Sample point register;
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--
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-- In Mode 7 each pixel lasts 8 clocks (96MHz / 12MHz). The original
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-- pixel clock is a regenerated 6Mhz clock, and both edges are used.
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-- Due to the way it is generated, there are three distinct phases,
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-- each with different rising/falling edge speeds, hence six sampling
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-- points are used.
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--
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-- In Modes 0..6 each pixel lasts 6 clocks (96MHz / 16MHz). The original
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-- pixel clock is a clean 16Mhz clock, so only one sample point is needed.
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-- To achieve this, all six values are set to be the same. This minimises
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-- the logic in the CPLD.
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signal sp_reg : std_logic_vector(25 downto 0) := INIT_SAMPLING_POINTS;
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-- Break out of sp_reg
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signal invert : std_logic;
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signal rate : std_logic_vector(1 downto 0);
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signal delay : unsigned(1 downto 0);
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signal half : std_logic;
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signal offset_A : std_logic_vector(2 downto 0);
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signal offset_B : std_logic_vector(2 downto 0);
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signal offset_C : std_logic_vector(2 downto 0);
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signal offset_D : std_logic_vector(2 downto 0);
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signal offset_E : std_logic_vector(2 downto 0);
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signal offset_F : std_logic_vector(2 downto 0);
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-- Pipelined offset mux output
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signal offset : std_logic_vector(2 downto 0);
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-- Index to cycle through offsets A..F
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signal index : std_logic_vector(2 downto 0);
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-- Sample pixel on next clock; pipelined to reduce the number of product terms
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signal sample : std_logic;
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-- New sample available, toggle psync on next cycle
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signal toggle : std_logic;
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-- RGB Input Mux
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signal R3 :std_logic;
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signal G3 :std_logic;
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signal B3 :std_logic;
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signal R2 :std_logic;
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signal G2 :std_logic;
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signal B2 :std_logic;
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signal divider : std_logic;
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signal mux : std_logic;
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signal mux_sync : std_logic;
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signal psync_pulse : std_logic;
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signal clamp_output : std_logic;
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signal clamp_pulse : std_logic;
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signal clamp_enable : std_logic;
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signal swap_bits_R :std_logic;
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signal swap_bits_G :std_logic;
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signal swap_bits_B :std_logic;
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begin
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offset_A <= sp_reg(2 downto 0);
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offset_B <= sp_reg(5 downto 3);
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offset_C <= sp_reg(8 downto 6);
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offset_D <= sp_reg(11 downto 9);
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offset_E <= sp_reg(14 downto 12);
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offset_F <= sp_reg(17 downto 15);
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half <= sp_reg(18);
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delay <= unsigned(sp_reg(20 downto 19));
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rate <= sp_reg(22 downto 21);
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invert <= sp_reg(23);
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divider <= sp_reg(24);
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mux <= sp_reg(25);
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mux_sync <= vsync_I when mux = '1' and version = '1' else csync_I;
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-- sp_data is overloaded as clamp on/off when rate = 00 or 01 and multiplex on/off when rate = 10 or 11
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-- rate = 00 is 3 bit capture with sp_data = clamp on/off
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-- rate = 01 is 6 bit capture with sp_data = clamp on/off
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-- rate = 10 and sp_data = 0 is 6 bit capture with 3 bit to 4 level encoding (clamp not usable in 4 level mode)
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-- rate = 10 and sp_data = 1 is 6 bit capture with multiplex enabled for 12 bit capture
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-- rate = 11 and mux = 0 is 12 bit capture
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-- rate = 11 and mux = 1 is 9 bit capture using vsync_I as replacement G1 bit (will work on 8 bit board)
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swap_bits_G <= vsync_I when rate = "10" and sp_data = '0' else '0';
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swap_bits_B <= B1_I when rate = "10" and sp_data = '0' else '0';
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swap_bits_R <= R1_I when rate = "10" and sp_data = '0' else '0';
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G3 <= G2_I when swap_bits_G = '1' else G3_I;
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G2 <= G3_I when swap_bits_G = '1' else G2_I;
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B3 <= B2_I when swap_bits_B = '1' else B3_I;
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B2 <= B3_I when swap_bits_B = '1' else B2_I;
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R3 <= R2_I when swap_bits_R = '1' else R3_I;
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R2 <= R3_I when swap_bits_R = '1' else R2_I;
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-- Shift the bits in LSB first
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process(sp_clk)
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begin
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if rising_edge(sp_clk) then
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if sp_clken = '1' then
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sp_reg <= sp_data & sp_reg(sp_reg'left downto sp_reg'right + 1);
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end if;
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end if;
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end process;
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process(clk)
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begin
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if rising_edge(clk) then
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-- synchronize CSYNC to the sampling clock
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-- if link fitted sync is inverted. If +ve vsync connected to link & +ve hsync to S then generate -ve composite sync
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csync1 <= mux_sync xor invert;
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-- De-glitch CSYNC
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-- csync1 is the possibly glitchy input
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-- csync2 is the filtered output
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if csync1 = csync2 then
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-- output same as input, reset the counter
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csync_counter <= to_unsigned(0, csync_counter'length);
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else
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-- output different to input
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csync_counter <= csync_counter + 1;
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-- if the difference lasts for N-1 cycles, update the output
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if csync_counter = 3 then
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csync2 <= csync1;
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end if;
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end if;
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-- Counter is used to find sampling point for first pixel
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last <= csync2;
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-- reset counter on the rising edge of csync
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if last = '0' and csync2 = '1' then
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counter(6 downto 3) <= "10" & delay;
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if half = '1' then
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counter(2 downto 0) <= "000";
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elsif divider = '1' then
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counter(2 downto 0) <= "100";
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else
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counter(2 downto 0) <= "011";
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end if;
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elsif divider = '1' or counter(2 downto 0) /= 5 then
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if counter(counter'left) = '1' then
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counter <= counter + 1;
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else
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counter(counter'left - 1 downto 0) <= counter(counter'left - 1 downto 0) + 1;
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end if;
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else
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if counter(counter'left) = '1' then
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counter <= counter + 3;
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else
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counter(counter'left - 1 downto 0) <= counter(counter'left - 1 downto 0) + 3;
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end if;
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end if;
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-- Sample point offset index
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if counter(counter'left) = '1' then
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index <= "000";
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else
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-- so index offset changes at the same time counter wraps 7->0
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-- so index offset changes at the same time counter wraps ->0
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if (divider = '0' and counter(2 downto 0) = 4) or (divider = '1' and counter(2 downto 0) = 6) then
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case index is
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when "000" =>
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index <= "001";
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when "001" =>
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index <= "010";
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when "010" =>
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index <= "011";
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when "011" =>
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index <= "100";
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when "100" =>
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index <= "101";
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when others =>
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index <= "000";
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end case;
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end if;
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end if;
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-- Sample point offset
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case index is
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when "000" =>
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offset <= offset_B;
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when "001" =>
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offset <= offset_C;
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when "010" =>
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offset <= offset_D;
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when "011" =>
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offset <= offset_E;
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when "100" =>
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offset <= offset_F;
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when others =>
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offset <= offset_A;
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end case;
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-- sample/shift control
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if counter(counter'left) = '0' and counter(2 downto 0) = unsigned(offset) then
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sample <= '1';
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else
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sample <= '0';
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end if;
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if sample = '1' then
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if rate = "11" and sp_data = '1' then
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shift_R <= R1_I & G2_I & B3_I & B0_I; -- 12 bpp
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elsif rate = "11" and sp_data = '0' then
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shift_R <= R1_I & G2_I & B3_I & B3_I; -- 9 bpp
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elsif rate = "10" and sp_data = '1' then
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shift_R <= shift_B(3) & G2_I & B3_I & shift_B(0); -- 6x2 multiplex 12 bpp
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elsif rate = "10" and sp_data = '0' then
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shift_R <= R2 & R3 & shift_R(3 downto 2); -- 6 bpp 4 level
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elsif rate = "01" then
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shift_R <= R2_I & R3_I & shift_R(3 downto 2); -- 6 bpp
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else
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shift_R <= R3_I & shift_R(3 downto 1); -- 3 bpp
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end if;
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end if;
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-- G Sample/shift register
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if sample = '1' then
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if rate = "11" and sp_data = '1' then
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shift_G <= R2_I & G3_I & G0_I & B1_I; -- 12 bpp
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elsif rate = "11" and sp_data = '0' then
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shift_G <= R2_I & G3_I & G3_I & B1_I; -- 9 bpp
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elsif rate = "10" and sp_data = '1' then
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shift_G <= R2_I & G3_I & shift_R(2) & shift_R(1); -- 6x2 multiplex 12 bpp
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elsif rate = "10" and sp_data = '0' then
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shift_G <= G2 & G3 & shift_G(3 downto 2); -- 6 bpp 4 level
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elsif rate = "01" then
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shift_G <= G2_I & G3_I & shift_G(3 downto 2); -- 6 bpp
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else
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shift_G <= G3_I & shift_G(3 downto 1); -- 3 bpp
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end if;
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end if;
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-- B Sample/shift register
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if sample = '1' then
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if rate = "11" and sp_data = '1' then
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shift_B <= R3_I & R0_I & G1_I & B2_I; -- 12 bpp
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elsif rate = "11" and sp_data = '0' then
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shift_B <= R3_I & R3_I & vsync_I & B2_I; -- 9 bpp with G1 on vsync_I
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elsif rate = "10" and sp_data = '1' then
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shift_B <= R3_I & shift_G(3) & shift_G(2) & B2_I; -- 6x2 multiplex 12 bpp
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elsif rate = "10" and sp_data = '0' then
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shift_B <= B2 & B3 & shift_B(3 downto 2); -- 6 bpp 4 level
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elsif rate = "01" then
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shift_B <= B2_I & B3_I & shift_B(3 downto 2); -- 6 bpp
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else
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shift_B <= B3_I & shift_B(3 downto 1); -- 3 bpp
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end if;
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end if;
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-- Pipeline when to update the quad
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if counter(counter'left) = '0' and (
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(rate = "00" and counter(4 downto 0) = 0) or -- single
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(rate = "01" and counter(3 downto 0) = 0) or -- double
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(rate = "10" and counter(3 downto 0) = 0) or -- double
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(rate = "11" and counter(2 downto 0) = 0) ) then -- quadruple
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-- toggle is asserted in cycle 1
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toggle <= '1';
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else
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toggle <= '0';
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end if;
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-- Output quad register
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if version = '0' then
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if analog = '1' then
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quad <= VERSION_NUM_RGB_ANALOG;
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else
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quad <= VERSION_NUM_RGB_TTL;
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end if;
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elsif counter(counter'left) = '1' then
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quad <= (others => '0');
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elsif toggle = '1' then
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-- quad changes at the start of cycle 2
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quad(11) <= shift_B(3);
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quad(10) <= shift_G(3);
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quad(9) <= shift_R(3);
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quad(8) <= shift_B(2);
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quad(7) <= shift_G(2);
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quad(6) <= shift_R(2);
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quad(5) <= shift_B(1);
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quad(4) <= shift_G(1);
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quad(3) <= shift_R(1);
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quad(2) <= shift_B(0);
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quad(1) <= shift_G(0);
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quad(0) <= shift_R(0);
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end if;
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-- Output a skewed version of psync
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if version = '0' then
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psync <= vsync_I;
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elsif counter(counter'left) = '1' then
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psync <= '0';
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elsif counter(2 downto 0) = 2 then -- comparing with N gives N-1 cycles of skew
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if rate = "00" then
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psync <= counter(5); -- normal
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elsif rate = "11" then
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psync <= counter(3); -- quadruple
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else
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psync <= counter(4); -- double
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end if;
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end if;
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end if;
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end process;
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csync <= csync2; -- output the registered version to save a macro-cell
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-- csync2 is cleaned but delayed so OR with csync1 to remove delay on trailing edge of sync pulse
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-- clamp not usable in 4 LEVEL mode (rate = 10) or 8/12 bit mode (rate = 11) so use as multiplex signal instead
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clamp_pulse <= not(sample) when rate = "10" or rate = "11" else not(csync1 or csync2);
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clamp_enable <= '1' when mux = '1' else version;
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-- spdata is overloaded as clamp on/off
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analog <= 'Z' when clamp_enable = '0' else clamp_pulse and sp_data;
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end Behavorial;
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