kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
250 wiersze
12 KiB
ArmAsm
250 wiersze
12 KiB
ArmAsm
#include "rpi-base.h"
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#include "defs.h"
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#include "macros.S"
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.text
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.global capture_line_fast_eightbits_8bpp
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.global capture_line_fast_ninebitslo_16bpp
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.global capture_line_fast_ninebitshi_16bpp
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.global capture_line_fast_twelvebits_16bpp
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// The capture line function is provided the following:
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// r0 = pointer to current line in frame buffer
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// r1 = number of complete psync cycles to capture (=param_chars_per_line)
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// r2 = frame buffer line pitch in bytes (=param_fb_pitch)
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// r3 = flags register
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// r4 = GPLEV0 constant
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// r5 = line number count down to 0 (initial value =param_nlines)
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// r6 = scan line count modulo 10
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// r7 = number of psyncs to skip
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// r8 = frame buffer height (=param_fb_height)
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//
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// All registers are available as scratch registers (i.e. nothing needs to be preserved)
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.ltorg
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// *** 8 bit ***
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.align 6
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b preload_capture_line_fast_eightbits_8bpp
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capture_line_fast_eightbits_8bpp:
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push {lr}
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SETUP_VSYNC_DEBUG_R11_R12
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SKIP_PSYNC_NO_OLD_CPLD_HIGH_LATENCY
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mov r1, r1, lsr #3
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SETUP_EIGHT_BITS_MASK_R14
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loop_8bpp:
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_EIGHT_BITS_8BPP_0 r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_EIGHT_BITS_8BPP_1 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_EIGHT_BITS_8BPP_2 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_EIGHT_BITS_8BPP_3 r5 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_EIGHT_BITS_8BPP_0 r12 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_EIGHT_BITS_8BPP_1 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_EIGHT_BITS_8BPP_2 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_EIGHT_BITS_8BPP_3 r6 // input in r8
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stmia r0!, {r5, r6}
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subs r1, r1, #1
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bne loop_8bpp
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pop {r0, pc}
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preload_capture_line_fast_eightbits_8bpp:
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SETUP_DUMMY_PARAMETERS
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b capture_line_fast_eightbits_8bpp
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.ltorg
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.align 6
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// *** 16 bit ***
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b preload_capture_line_fast_twelvebits_16bpp
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capture_line_fast_twelvebits_16bpp:
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push {lr}
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SETUP_VSYNC_DEBUG_16BPP_R11
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tst r3, #BITDUP_ENABLE_FFOSD | BITDUP_ENABLE_GREY_DETECT
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bne TEST_capture_line_fast_twelvebits_16bpp
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SKIP_PSYNC_NO_OLD_CPLD_HIGH_LATENCY
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mov r1, r1, lsr #3
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SETUP_TWELVE_BITS_MASK_R14
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loop_16bpp:
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_TWELVE_BITS_16BPP_HI r5 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_TWELVE_BITS_16BPP_HI r6 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_TWELVE_BITS_16BPP_HI r7 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_TWELVE_BITS_16BPP_HI r10 // input in r8
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stmia r0!, {r5, r6, r7, r10}
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subs r1, r1, #1
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bne loop_16bpp
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pop {r0, pc}
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TEST_capture_line_fast_twelvebits_16bpp:
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tst r3, #BIT_OSD | BITDUP_ENABLE_GREY_DETECT
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bne OSD_capture_line_fast_twelvebits_16bpp
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SKIP_PSYNC_NO_OLD_CPLD_HIGH_LATENCY
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mov r1, r1, lsr #3
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SETUP_TWELVE_BITS_MASK_R14
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TEST_loop_16bpp:
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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TEST_CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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TEST_CAPTURE_TWELVE_BITS_16BPP_HI r5 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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TEST_CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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TEST_CAPTURE_TWELVE_BITS_16BPP_HI r6 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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TEST_CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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TEST_CAPTURE_TWELVE_BITS_16BPP_HI r7 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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TEST_CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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TEST_CAPTURE_TWELVE_BITS_16BPP_HI r10 // input in r8
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stmia r0!, {r5, r6, r7, r10}
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subs r1, r1, #1
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bne TEST_loop_16bpp
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pop {r0, pc}
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OSD_capture_line_fast_twelvebits_16bpp:
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tst r3, #BITDUP_ENABLE_GREY_DETECT
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orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
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SKIP_PSYNC_NO_OLD_CPLD_HIGH_LATENCY
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mov r1, r1, lsr #3
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SETUP_TWELVE_BITS_MASK_R14
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OSD_loop_16bpp:
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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OSD_CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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OSD_CAPTURE_TWELVE_BITS_16BPP_HI r5 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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OSD_CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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OSD_CAPTURE_TWELVE_BITS_16BPP_HI r6 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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OSD_CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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OSD_CAPTURE_TWELVE_BITS_16BPP_HI r7 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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OSD_CAPTURE_TWELVE_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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OSD_CAPTURE_TWELVE_BITS_16BPP_HI r10 // input in r8
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stmia r0!, {r5, r6, r7, r10}
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subs r1, r1, #1
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bne OSD_loop_16bpp
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pop {r0, pc}
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preload_capture_line_fast_twelvebits_16bpp:
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SETUP_DUMMY_PARAMETERS
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b capture_line_fast_twelvebits_16bpp
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.ltorg
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.align 6
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// *** 16 bit ***
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b preload_capture_line_fast_ninebitslo_16bpp
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capture_line_fast_ninebitslo_16bpp:
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push {lr}
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SETUP_VSYNC_DEBUG_16BPP_R11
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SKIP_PSYNC_NO_OLD_CPLD_HIGH_LATENCY
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mov r1, r1, lsr #3
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SETUP_NINELO_BITS_MASK_R14
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loop_16lobpp:
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINELO_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINELO_BITS_16BPP_HI r5 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINELO_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINELO_BITS_16BPP_HI r6 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINELO_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINELO_BITS_16BPP_HI r7 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINELO_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINELO_BITS_16BPP_HI r10 // input in r8
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stmia r0!, {r5, r6, r7, r10}
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subs r1, r1, #1
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bne loop_16lobpp
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pop {r0, pc}
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preload_capture_line_fast_ninebitslo_16bpp:
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SETUP_DUMMY_PARAMETERS
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b capture_line_fast_ninebitslo_16bpp
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.ltorg
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.align 6
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// *** 16 bit ***
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b preload_capture_line_fast_ninebitshi_16bpp
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capture_line_fast_ninebitshi_16bpp:
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push {lr}
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SETUP_VSYNC_DEBUG_16BPP_R11
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SKIP_PSYNC_NO_OLD_CPLD_HIGH_LATENCY
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mov r1, r1, lsr #3
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SETUP_NINEHI_BITS_MASK_R14
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loop_16hibpp:
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINEHI_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINEHI_BITS_16BPP_HI r5 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINEHI_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINEHI_BITS_16BPP_HI r6 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINEHI_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINEHI_BITS_16BPP_HI r7 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINEHI_BITS_16BPP_LO r11 // input in r8
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WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
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CAPTURE_NINEHI_BITS_16BPP_HI r10 // input in r8
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stmia r0!, {r5, r6, r7, r10}
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subs r1, r1, #1
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bne loop_16hibpp
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pop {r0, pc}
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preload_capture_line_fast_ninebitshi_16bpp:
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SETUP_DUMMY_PARAMETERS
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b capture_line_fast_ninebitshi_16bpp |