David Banks b2ed64acee CPLD: Start counting off leading edge of HSYNC ... Change-Id: I3c1baa29f3db2183ce6920870bcb4e7c936c1b6b		2018-07-15 15:36:02 +01:00
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RGBtoHDMI.ucf	CPLD: final pinout changes	2018-06-12 12:39:06 +01:00
RGBtoHDMI.vhdl	CPLD: Start counting off leading edge of HSYNC	2018-07-15 15:36:02 +01:00
RGBtoHDMI.xise	CPLD: Mostly cosmetic seperation of the logic into several blocks	2018-06-07 17:14:02 +01:00
fitting.notes	Normal CPLD: de-glitch csync (needs to be low for 3 samples)	2018-06-22 11:45:05 +01:00