{"st", FloatReg|FloatAcc, 0, 0},
  /* 8 bit regs */
#define AL_INDEX 1
  {"al", Reg8|Acc, 0, 0},
  {"cl", Reg8|ShiftCntReg, 0, 1},
  {"dl", Reg8, 0, 2},
  {"bl", Reg8, 0, 3},
  {"ah", Reg8, 0, 4},
  {"ch", Reg8, 0, 5},
  {"dh", Reg8, 0, 6},
  {"bh", Reg8, 0, 7},
  {"axl", Reg8|Acc, RegRex64, 0},
  {"cxl", Reg8, RegRex64, 1},
  {"dxl", Reg8, RegRex64, 2},
  {"bxl", Reg8, RegRex64, 3},
  {"spl", Reg8, RegRex64, 4},
  {"bpl", Reg8, RegRex64, 5},
  {"sil", Reg8, RegRex64, 6},
  {"dil", Reg8, RegRex64, 7},
  {"r8b", Reg8, RegRex64|RegRex, 0},
  {"r9b", Reg8, RegRex64|RegRex, 1},
  {"r10b", Reg8, RegRex64|RegRex, 2},
  {"r11b", Reg8, RegRex64|RegRex, 3},
  {"r12b", Reg8, RegRex64|RegRex, 4},
  {"r13b", Reg8, RegRex64|RegRex, 5},
  {"r14b", Reg8, RegRex64|RegRex, 6},
  {"r15b", Reg8, RegRex64|RegRex, 7},
  /* 16 bit regs */
#define AX_INDEX 25
  {"ax", Reg16|Acc, 0, 0},
  {"cx", Reg16, 0, 1},
  {"dx", Reg16|IOPortReg, 0, 2},
  {"bx", Reg16|BaseIndex, 0, 3},
  {"sp", Reg16, 0, 4},
  {"bp", Reg16|BaseIndex, 0, 5},
  {"si", Reg16|BaseIndex, 0, 6},
  {"di", Reg16|BaseIndex, 0, 7},
  {"r8w", Reg16, RegRex, 0},
  {"r9w", Reg16, RegRex, 1},
  {"r10w", Reg16, RegRex, 2},
  {"r11w", Reg16, RegRex, 3},
  {"r12w", Reg16, RegRex, 4},
  {"r13w", Reg16, RegRex, 5},
  {"r14w", Reg16, RegRex, 6},
  {"r15w", Reg16, RegRex, 7},
  /* 32 bit regs */
#define EAX_INDEX 41
  {"eax", Reg32|BaseIndex|Acc, 0, 0},
  {"ecx", Reg32|BaseIndex, 0, 1},
  {"edx", Reg32|BaseIndex, 0, 2},
  {"ebx", Reg32|BaseIndex, 0, 3},
  {"esp", Reg32, 0, 4},
  {"ebp", Reg32|BaseIndex, 0, 5},
  {"esi", Reg32|BaseIndex, 0, 6},
  {"edi", Reg32|BaseIndex, 0, 7},
  {"r8d", Reg32|BaseIndex, RegRex, 0},
  {"r9d", Reg32|BaseIndex, RegRex, 1},
  {"r10d", Reg32|BaseIndex, RegRex, 2},
  {"r11d", Reg32|BaseIndex, RegRex, 3},
  {"r12d", Reg32|BaseIndex, RegRex, 4},
  {"r13d", Reg32|BaseIndex, RegRex, 5},
  {"r14d", Reg32|BaseIndex, RegRex, 6},
  {"r15d", Reg32|BaseIndex, RegRex, 7},
  {"rax", Reg64|BaseIndex|Acc, 0, 0},
  {"rcx", Reg64|BaseIndex, 0, 1},
  {"rdx", Reg64|BaseIndex, 0, 2},
  {"rbx", Reg64|BaseIndex, 0, 3},
  {"rsp", Reg64, 0, 4},
  {"rbp", Reg64|BaseIndex, 0, 5},
  {"rsi", Reg64|BaseIndex, 0, 6},
  {"rdi", Reg64|BaseIndex, 0, 7},
  {"r8", Reg64|BaseIndex, RegRex, 0},
  {"r9", Reg64|BaseIndex, RegRex, 1},
  {"r10", Reg64|BaseIndex, RegRex, 2},
  {"r11", Reg64|BaseIndex, RegRex, 3},
  {"r12", Reg64|BaseIndex, RegRex, 4},
  {"r13", Reg64|BaseIndex, RegRex, 5},
  {"r14", Reg64|BaseIndex, RegRex, 6},
  {"r15", Reg64|BaseIndex, RegRex, 7},
  /* segment registers */
  {"es", SegReg2, 0, 0},
  {"cs", SegReg2, 0, 1},
  {"ss", SegReg2, 0, 2},
  {"ds", SegReg2, 0, 3},
  {"fs", SegReg3, 0, 4},
  {"gs", SegReg3, 0, 5},
  /* control registers */
  {"cr0", CtrlReg, 0, 0},
  {"cr1", CtrlReg, 0, 1},
  {"cr2", CtrlReg, 0, 2},
  {"cr3", CtrlReg, 0, 3},
  {"cr4", CtrlReg, 0, 4},
  {"cr5", CtrlReg, 0, 5},
  {"cr6", CtrlReg, 0, 6},
  {"cr7", CtrlReg, 0, 7},
  {"cr8", CtrlReg, RegRex, 0},
  {"cr9", CtrlReg, RegRex, 1},
  {"cr10", CtrlReg, RegRex, 2},
  {"cr11", CtrlReg, RegRex, 3},
  {"cr12", CtrlReg, RegRex, 4},
  {"cr13", CtrlReg, RegRex, 5},
  {"cr14", CtrlReg, RegRex, 6},
  {"cr15", CtrlReg, RegRex, 7},
  /* debug registers */
  {"db0", DebugReg, 0, 0},
  {"db1", DebugReg, 0, 1},
  {"db2", DebugReg, 0, 2},
  {"db3", DebugReg, 0, 3},
  {"db4", DebugReg, 0, 4},
  {"db5", DebugReg, 0, 5},
  {"db6", DebugReg, 0, 6},
  {"db7", DebugReg, 0, 7},
  {"db8", DebugReg, RegRex, 0},
  {"db9", DebugReg, RegRex, 1},
  {"db10", DebugReg, RegRex, 2},
  {"db11", DebugReg, RegRex, 3},
  {"db12", DebugReg, RegRex, 4},
  {"db13", DebugReg, RegRex, 5},
  {"db14", DebugReg, RegRex, 6},
  {"db15", DebugReg, RegRex, 7},
  {"dr0", DebugReg, 0, 0},
  {"dr1", DebugReg, 0, 1},
  {"dr2", DebugReg, 0, 2},
  {"dr3", DebugReg, 0, 3},
  {"dr4", DebugReg, 0, 4},
  {"dr5", DebugReg, 0, 5},
  {"dr6", DebugReg, 0, 6},
  {"dr7", DebugReg, 0, 7},
  {"dr8", DebugReg, RegRex, 0},
  {"dr9", DebugReg, RegRex, 1},
  {"dr10", DebugReg, RegRex, 2},
  {"dr11", DebugReg, RegRex, 3},
  {"dr12", DebugReg, RegRex, 4},
  {"dr13", DebugReg, RegRex, 5},
  {"dr14", DebugReg, RegRex, 6},
  {"dr15", DebugReg, RegRex, 7},
  /* test registers */
  {"tr0", TestReg, 0, 0},
  {"tr1", TestReg, 0, 1},
  {"tr2", TestReg, 0, 2},
  {"tr3", TestReg, 0, 3},
  {"tr4", TestReg, 0, 4},
  {"tr5", TestReg, 0, 5},
  {"tr6", TestReg, 0, 6},
  {"tr7", TestReg, 0, 7},
  /* mmx and simd registers */
  {"mm0", MMXReg, 0, 0},
  {"mm1", MMXReg, 0, 1},
  {"mm2", MMXReg, 0, 2},
  {"mm3", MMXReg, 0, 3},
  {"mm4", MMXReg, 0, 4},
  {"mm5", MMXReg, 0, 5},
  {"mm6", MMXReg, 0, 6},
  {"mm7", MMXReg, 0, 7},
  {"xmm0", XMMReg, 0, 0},
  {"xmm1", XMMReg, 0, 1},
  {"xmm2", XMMReg, 0, 2},
  {"xmm3", XMMReg, 0, 3},
  {"xmm4", XMMReg, 0, 4},
  {"xmm5", XMMReg, 0, 5},
  {"xmm6", XMMReg, 0, 6},
  {"xmm7", XMMReg, 0, 7},
  {"xmm8", XMMReg, RegRex, 0},
  {"xmm9", XMMReg, RegRex, 1},
  {"xmm10", XMMReg, RegRex, 2},
  {"xmm11", XMMReg, RegRex, 3},
  {"xmm12", XMMReg, RegRex, 4},
  {"xmm13", XMMReg, RegRex, 5},
  {"xmm14", XMMReg, RegRex, 6},
  {"xmm15", XMMReg, RegRex, 7},
  {"st(0)", FloatReg|FloatAcc, 0, 0},
  {"st(1)", FloatReg, 0, 1},
  {"st(2)", FloatReg, 0, 2},
  {"st(3)", FloatReg, 0, 3},
  {"st(4)", FloatReg, 0, 4},
  {"st(5)", FloatReg, 0, 5},
  {"st(6)", FloatReg, 0, 6},
  {"st(7)", FloatReg, 0, 7},
  {"rip", BaseIndex, 0, 0},
  {NULL, 0, 0, 0}