1. Original design: Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 27/54 69/90 6/ 9 FB2 18/18* 34/54 60/90 8/ 9 FB3 18/18* 19/54 32/90 5/ 9 FB4 18/18* 37/54 56/90 7/ 7* ----- ----- ----- ----- 72/72 117/216 217/360 26/34 2. New design, with RGB mux, switch pass throughs, etc commented out (failed to map sp_reg<9>, hence one less macrocell) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 26/54 51/90 7/ 9 FB2 18/18* 25/54 33/90 6/ 9 FB3 18/18* 35/54 61/90 8/ 9 FB4 17/18 53/54 70/90 4/ 7 ----- ----- ----- ----- 71/72 139/216 215/360 25/34 3. Change from csync=>S to csync=>CSYNC1 (as passthroughs still use up a macro cell). (now fits) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 17/18 33/54 64/90 7/ 9 FB2 18/18* 25/54 33/90 6/ 9 FB3 18/18* 35/54 61/90 8/ 9 FB4 18/18* 37/54 58/90 4/ 7 ----- ----- ----- ----- 71/72 130/216 216/360 25/34 4. Add in RGB mux: (still fits) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 17/18 33/54 64/90 7/ 9 FB2 18/18* 25/54 33/90 9/ 9* FB3 18/18* 37/54 61/90 8/ 9 FB4 18/18* 41/54 61/90 5/ 7 ----- ----- ----- ----- 71/72 136/216 219/360 29/34 5. Add in SW2out <= SW2: (still fits) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 28/54 62/90 8/ 9 FB2 18/18* 25/54 33/90 9/ 9* FB3 18/18* 37/54 61/90 8/ 9 FB4 18/18* 48/54 64/90 6/ 7 ----- ----- ----- ----- 72/72 138/216 220/360 31/34 6. Change to optimization effort normal->high: (no difference) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 28/54 62/90 8/ 9 FB2 18/18* 25/54 33/90 9/ 9* FB3 18/18* 37/54 61/90 8/ 9 FB4 18/18* 48/54 64/90 6/ 7 ----- ----- ----- ----- 72/72 138/216 220/360 31/34 7. Change to optimization effort speed->area: (no difference) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 28/54 62/90 8/ 9 FB2 18/18* 25/54 33/90 9/ 9* FB3 18/18* 37/54 61/90 8/ 9 FB4 18/18* 48/54 64/90 6/ 7 ----- ----- ----- ----- 72/72 138/216 220/360 31/34 8. Fitter Implmenetation Template: Optimize Balance-> Optimize Speed: (no difference) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 28/54 62/90 8/ 9 FB2 18/18* 25/54 33/90 9/ 9* FB3 18/18* 37/54 61/90 8/ 9 FB4 18/18* 48/54 64/90 6/ 7 ----- ----- ----- ----- 72/72 138/216 220/360 31/34 9. Fitter Implmenetation Template: Optimize Speed -> Optimize Density: (no difference) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 28/54 62/90 8/ 9 FB2 18/18* 25/54 33/90 9/ 9* FB3 18/18* 37/54 61/90 8/ 9 FB4 18/18* 48/54 64/90 6/ 7 ----- ----- ----- ----- 72/72 138/216 220/360 31/34 10. Reverted to original .xise file Cleaned up design to remove SW2/3 pass throughs Used gpio22/23 for mode7 / sp_data Used gpio19/26 for sw2/3 (not via cpld) (same result as 4 above) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 17/18 33/54 64/90 5/ 9 FB2 18/18* 25/54 33/90 9/ 9* FB3 18/18* 37/54 61/90 8/ 9 FB4 18/18* 41/54 61/90 7/ 7* ----- ----- ----- ----- 71/72 136/216 219/360 29/34 11. Final design on 5/6/2018 (Added SW2, SW3, Link as unused inputs) (Added LED1 as output, driven to Z, still uses one macro cell) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 27/54 61/90 5/ 9 FB2 18/18* 25/54 33/90 9/ 9* FB3 18/18* 37/54 61/90 9/ 9* FB4 18/18* 48/54 64/90 7/ 7* ----- ----- ----- ----- 72/72 137/216 219/360 30/34 12. Minor changes 1.15pm on 5/5/2018 (Removed SW1Out passthrough) (csync output is back to being passthrough) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 25/54 35/90 4/ 9 FB2 18/18* 34/54 65/90 9/ 9* FB3 18/18* 37/54 61/90 9/ 9* FB4 18/18* 39/54 58/90 7/ 7* ----- ----- ----- ----- 72/72 135/216 219/360 29/34 13. Removed SW1 from sp_reg assignment block (the is prone to noise on the prototype, as it clamped at 2V by an LED) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 25/54 35/90 3/ 9 FB2 18/18* 34/54 65/90 9/ 9* FB3 18/18* 37/54 61/90 9/ 9* FB4 18/18* 39/54 58/90 7/ 7* ----- ----- ----- ----- 72/72 135/216 219/360 28/34 14. Added sp_clken and spare Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 30/54 63/90 5/ 9 FB2 18/18* 26/54 46/90 9/ 9* FB3 18/18* 35/54 60/90 8/ 9 FB4 18/18* 47/54 71/90 7/ 7* ----- ----- ----- ----- 72/72 138/216 240/360 29/34 15. Replaced counter2(5..3) with load saving two registers Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 40/54 72/90 5/ 9 FB2 17/18 24/54 49/90 9/ 9* FB3 18/18* 34/54 60/90 8/ 9 FB4 17/18 35/54 63/90 7/ 7* ----- ----- ----- ----- 70/72 133/216 244/360 29/34 16. Mostly cosmetic seperation of the logic into several blocks Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 38/54 56/90 5/ 9 FB2 16/18 21/54 45/90 9/ 9* FB3 18/18* 33/54 57/90 8/ 9 FB4 18/18* 37/54 70/90 7/ 7* ----- ----- ----- ----- 70/72 129/216 228/360 29/34 17. Update counter to hopefully implement more efficiently Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 38/54 54/90 5/ 9 FB2 16/18 21/54 45/90 9/ 9* FB3 18/18* 30/54 49/90 8/ 9 FB4 18/18* 35/54 65/90 7/ 7* ----- ----- ----- ----- 70/72 124/216 213/360 29/34 18. Load always in cycle 0 Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 38/54 53/90 5/ 9 FB2 16/18 21/54 45/90 9/ 9* FB3 18/18* 30/54 45/90 8/ 9 FB4 18/18* 37/54 63/90 7/ 7* ----- ----- ----- ----- 70/72 126/216 206/360 29/34 19. Dropped seperate sp_default stage Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 30/54 42/90 5/ 9 FB2 17/18 25/54 34/90 9/ 9* FB3 18/18* 29/54 55/90 8/ 9 FB4 13/18 35/54 44/90 7/ 7* ----- ----- ----- ----- 66/72 119/216 175/360 29/34 20. Added CPLD version output on Quad() Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 31/54 45/90 5/ 9 FB2 17/18 26/54 35/90 9/ 9* FB3 18/18* 30/54 61/90 9/ 9* FB4 13/18 36/54 47/90 7/ 7* ----- ----- ----- ----- 66/72 123/216 188/360 30/34 21. Added configurable half-pixel delay Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 31/54 45/90 5/ 9 FB2 18/18* 27/54 37/90 9/ 9* FB3 18/18* 31/54 65/90 9/ 9* FB4 13/18 38/54 48/90 7/ 7* ----- ----- ----- ----- 67/72 127/216 195/360 30/34 22. Final pinout changes - remove LED1 and LED2 as outputs Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 32/54 47/90 6/ 9 FB2 18/18* 32/54 41/90 8/ 9 FB3 18/18* 31/54 65/90 9/ 9* FB4 11/18 32/54 41/90 5/ 7 ----- ----- ----- ----- 65/72 127/216 194/360 28/34 23. Made csync output registered and de-glitch csync (csync1..csync3) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 35/54 50/90 6/ 9 FB2 16/18 25/54 34/90 8/ 9 FB3 16/18 30/54 81/90 9/ 9* FB4 16/18 40/54 61/90 5/ 7 ----- ----- ----- ----- 66/72 130/216 226/360 28/34 24. Increased de-glitch to include csync4 Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 40/54 54/90 6/ 9 FB2 18/18* 29/54 43/90 8/ 9 FB3 15/18 35/54 81/90 9/ 9* FB4 17/18 32/54 83/90 5/ 7 ----- ----- ----- ----- 68/72 136/216 261/360 28/34 25. Increased de-glitch to include csync5 ... doesn't fit ... 26. Revert to 23, then use a 3-bit counter for csync deglitch Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 35/54 49/90 6/ 9 FB2 18/18* 29/54 43/90 8/ 9 FB3 17/18 33/54 81/90 9/ 9* FB4 14/18 36/54 61/90 5/ 7 ----- ----- ----- ----- 67/72 133/216 234/360 28/34 27. Increase csync de-glitch counter to 4 bits Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 40/54 54/90 6/ 9 FB2 17/18 26/54 36/90 8/ 9 FB3 16/18 32/54 82/90 9/ 9* FB4 17/18 37/54 80/90 5/ 7 ----- ----- ----- ----- 68/72 135/216 252/360 28/34 28. De-glitch both states of csync Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 31/54 45/90 6/ 9 FB2 16/18 25/54 34/90 8/ 9 FB3 18/18* 29/54 79/90 9/ 9* FB4 18/18* 46/54 71/90 5/ 7 ----- ----- ----- ----- 70/72 131/216 229/360 28/34 29. Reduce csync de-glitch counter to 3 bits Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 31/54 45/90 6/ 9 FB2 16/18 25/54 34/90 8/ 9 FB3 18/18* 29/54 79/90 9/ 9* FB4 17/18 45/54 67/90 5/ 7 ----- ----- ----- ----- 69/72 130/216 225/360 28/34 30. Reduce csync de-glitch counter to 2 bits Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 31/54 45/90 6/ 9 FB2 16/18 25/54 34/90 8/ 9 FB3 18/18* 29/54 79/90 9/ 9* FB4 16/18 44/54 63/90 5/ 7 ----- ----- ----- ----- 68/72 129/216 221/360 28/34 31. Added 4-bit mode 7 delay register to the scan chain Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 18/18* 29/54 43/90 6/ 9 FB2 18/18* 27/54 38/90 8/ 9 FB3 18/18* 36/54 81/90 9/ 9* FB4 18/18* 52/54 70/90 5/ 7 ----- ----- ----- ----- 72/72 144/216 232/360 28/34