David Banks
|
87eb7535d6
|
CPLD: Mostly cosmetic seperation of the logic into several blocks
Change-Id: Ifacf6b9ad74eead8a4f0f48d59335d28fb1f9740
|
2018-06-07 17:14:02 +01:00 |
David Banks
|
082f772e55
|
Moved to 6 sampling points in Mode 7
Change-Id: I888d9911fe6be96f48bf9429650b4a13ae3c185d
|
2017-05-25 17:23:49 +01:00 |
David Banks
|
e3dbea5b30
|
VHDL: Updated .xise file
Change-Id: I8d8fdbac96ed32383779f61b69c88800ee6bfcf9
|
2017-04-25 09:52:49 +01:00 |
David Banks
|
7fa14552bd
|
Initial version of VHDL
Change-Id: I2fbdf73bc0feb8955a2b4b70856203e370cbad30
|
2017-04-24 20:21:18 +01:00 |