Normal CPLD: de-glitch csync (needs to be low for 3 samples)

Change-Id: I6d071cdd003536bc13dfa7fd24ede67a1a25d56c

vhdl/RGBtoHDMI.vhdl

@@ -94,6 +94,8 @@ architecture Behavorial of RGBtoHDMI is
     signal shift_B  : std_logic_vector(3 downto 0);
 
     signal csync1   : std_logic;
+    signal csync2   : std_logic;
+    signal csync3   : std_logic;
 
     -- The sampling counter runs at 96MHz
     -- - In modes 0..6 it is 6x  the pixel clock
@@ -175,9 +177,11 @@ begin
 
             -- synchronize CSYNC to the sampling clock
             csync1 <= S;
+            csync2 <= csync1;
+            csync3 <= csync2;
 
             -- Counter is used to find sampling point for first pixel
-            if csync1 = '0' then
+            if csync1 = '0' and csync2 = '0' and csync3 = '0' then
                 if mode7 = '1' then
                     if half = '1' then
                         counter <= mode7_offset_A;
@@ -200,7 +204,7 @@ begin
             end if;
 
             -- Sample point offset index
-            if csync1 = '0' then
+            if counter(11) = '1' then
                 index <= "000";
             else
                 -- so index offset changes at the same time counter wraps 7->0
@@ -288,6 +292,6 @@ begin
         end if;
     end process;
 
-    csync  <= S;      -- pass through, as clock might not be running
+    csync  <= csync1; -- output the registered version to save a macro-cell
 
 end Behavorial;

vhdl/fitting.notes

@@ -252,3 +252,25 @@ FB3          18/18*      31/54       65/90       9/ 9*
 FB4          13/18       38/54       48/90       7/ 7*
              -----       -----       -----      -----
              67/72      127/216     195/360     30/34
+
+22. Final pinout changes - remove LED1 and LED2 as outputs
+
+Function    Mcells      FB Inps     Pterms      IO
+Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot
+FB1          18/18*      32/54       47/90       6/ 9
+FB2          18/18*      32/54       41/90       8/ 9
+FB3          18/18*      31/54       65/90       9/ 9*
+FB4          11/18       32/54       41/90       5/ 7
+             -----       -----       -----      -----
+             65/72      127/216     194/360     28/34
+
+23. Made csync output registered and de-glitch csync
+
+Function    Mcells      FB Inps     Pterms      IO
+Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot
+FB1          18/18*      35/54       50/90       6/ 9
+FB2          16/18       25/54       34/90       8/ 9
+FB3          16/18       30/54       81/90       9/ 9*
+FB4          16/18       40/54       61/90       5/ 7
+             -----       -----       -----      -----
+             66/72      130/216     226/360     28/34