kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
Pi Firmware: Added pllh control (623-627 lines)
Change-Id: If1efa170a547aa2afbc5a2e108331b2f479f4092soft_delitch
David Banks
rodzic
fad4c55e76
commit
ee07893a3d
25
src/osd.c
25
src/osd.c
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@ -84,6 +84,15 @@ static const char *machine_names[] = {
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"Elk"
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};
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static const char *pllh_names[] = {
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"Original",
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"623",
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"624",
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"625",
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"626",
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"627",
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};
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// =============================================================
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// Feature definitions for OSD
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// =============================================================
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@ -95,6 +104,7 @@ enum {
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F_MUX,
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F_ELK,
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F_VSYNC,
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F_PLLH,
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F_DEBUG
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};
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@ -105,6 +115,7 @@ static param_t features[] = {
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{ "Input Mux", 0, 1 },
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{ "Elk", 0, 1 },
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{ "Vsync", 0, 1 },
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{ "PLLH", 0, 5 },
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{ "Debug", 0, 1 },
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{ NULL, 0, 0 },
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};
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@ -234,7 +245,7 @@ static int get_feature(int num) {
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return info;
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case F_PALETTE:
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return palette;
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case F_SCANLINES:
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case F_SCANLINES:
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return scanlines;
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case F_MUX:
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return mux;
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@ -242,6 +253,8 @@ static int get_feature(int num) {
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return get_elk();
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case F_VSYNC:
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return get_vsync();
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case F_PLLH:
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return get_pllh();
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case F_DEBUG:
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return debug;
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}
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@ -271,6 +284,9 @@ static void set_feature(int num, int value) {
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case F_VSYNC:
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set_vsync(value);
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break;
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case F_PLLH:
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set_pllh(value);
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break;
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case F_DEBUG:
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debug = value;
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update_palette();
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@ -286,6 +302,7 @@ static void show_feature(int num) {
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const char *valstr =
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(num == F_INFO) ? info_names[value] :
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(num == F_PALETTE) ? palette_names[value] :
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(num == F_PLLH) ? pllh_names[value] :
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value ? "On" : "Off";
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// Clear lines 2 onwards
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memset(buffer + 2 * LINELEN, 0, (NLINES - 2) * LINELEN);
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@ -535,6 +552,12 @@ void osd_init() {
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set_feature(F_ELK, val);
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log_info("config.txt: elk = %d", val);
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}
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prop = get_cmdline_prop("pllh");
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if (prop) {
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int val = atoi(prop);
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set_feature(F_PLLH, val);
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log_info("config.txt: pllh = %d", val);
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}
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prop = get_cmdline_prop("vsync");
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if (prop) {
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int val = atoi(prop);
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@ -26,5 +26,7 @@ void set_elk(int on);
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int get_elk();
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void set_vsync(int on);
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int get_vsync();
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void set_pllh(int mode);
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int get_pllh();
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#endif
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@ -51,6 +51,8 @@ static int height = 0;
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static uint32_t cpld_version_id;
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static volatile int delay;
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static int vsync;
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static int pllh;
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static double pllh_clock = 0;
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static int elk;
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static int mode7;
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static int clear;
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@ -328,57 +330,14 @@ static int calibrate_clock() {
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gpioreg[PLLH_STS]);
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// Dump the original PLLH frequency
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double f1 = 19.2 * ((double)(gpioreg[PLLH_CTRL] & 0x3ff) + ((double)gpioreg[PLLH_FRAC]) / ((double)(1 << 20)));
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log_info("Original PLLH: %lf MHz", f1);
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pllh_clock = 19.2 * ((double)(gpioreg[PLLH_CTRL] & 0x3ff) + ((double)gpioreg[PLLH_FRAC]) / ((double)(1 << 20)));
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// Correct for the Beeb's clock
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double f2 = f1 / error;
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// Correct for non-interlaced mode
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if (!(frame_time & INTERLACED_FLAG)) {
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f2 *= 626.0 / 624.0;
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}
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// Dump the target PLL frequency
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log_info(" Target PLLH: %lf MHz", f2);
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// Calculate the new fraction
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double div = gpioreg[PLLH_CTRL] & 0x3ff;
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int fract = (int) ((double)(1<<20) * (f2 / 19.2 - div));
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if (fract < 0) {
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log_warn("PLLH fraction < 0");
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fract = 0;
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}
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if (fract > (1<<20) - 1) {
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log_warn("PLLH fraction > 1");
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fract = (1<<20) - 1;
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}
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// Update the PLL
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int old_fract = gpioreg[PLLH_FRAC];
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gpioreg[PLLH_FRAC] = 0x5A000000 | fract;
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int new_fract = gpioreg[PLLH_FRAC];
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log_info("Old fract = %d (when read back)", old_fract);
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log_info("New fract = %d", fract);
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log_info("New fract = %d (when read back)", new_fract);
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log_info("PLLH: PDIV=%d NDIV=%d FRAC=%d AUX=%d RCAL=%d PIX=%d STS=%d",
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(gpioreg[PLLH_CTRL] >> 12) & 0x7,
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gpioreg[PLLH_CTRL] & 0x3ff,
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gpioreg[PLLH_FRAC],
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gpioreg[PLLH_AUX],
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gpioreg[PLLH_RCAL],
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gpioreg[PLLH_PIX],
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gpioreg[PLLH_STS]);
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// Dump the the actual PLL frequency
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double f3 = 19.2 * ((double)(gpioreg[PLLH_CTRL] & 0x3ff) + ((double)gpioreg[PLLH_FRAC]) / ((double)(1 << 20)));
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log_info(" Actual PLLH: %lf MHz", f3);
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log_info("Original PLLH: %lf MHz", pllh_clock);
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return a;
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}
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static void init_hardware() {
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int i;
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for (i = 0; i < 12; i++) {
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@ -768,6 +727,63 @@ int get_vsync() {
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return vsync;
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}
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int get_pllh() {
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return pllh;
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}
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void set_pllh(int mode) {
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pllh = mode;
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double error = 1.0 + (clock_error_ppm / 1e6);
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double f2 = pllh_clock;
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if (mode > 0) {
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// Correct for clock error
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f2 /= error;
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// Correct for specified number of lines (mode 1..5)
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f2 *= 625.0 / (622.0 + mode);
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}
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// Dump the target PLL frequency
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log_info(" Target PLLH: %lf MHz", f2);
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// Calculate the new fraction
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double div = gpioreg[PLLH_CTRL] & 0x3ff;
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int fract = (int) ((double)(1<<20) * (f2 / 19.2 - div));
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if (fract < 0) {
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log_warn("PLLH fraction < 0");
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fract = 0;
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}
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if (fract > (1<<20) - 1) {
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log_warn("PLLH fraction > 1");
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fract = (1<<20) - 1;
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}
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// Update the PLL
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int old_fract = gpioreg[PLLH_FRAC];
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gpioreg[PLLH_FRAC] = 0x5A000000 | fract;
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int new_fract = gpioreg[PLLH_FRAC];
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log_info("Old fract = %d (when read back)", old_fract);
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log_info("New fract = %d", fract);
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log_info("New fract = %d (when read back)", new_fract);
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log_info("PLLH: PDIV=%d NDIV=%d FRAC=%d AUX=%d RCAL=%d PIX=%d STS=%d",
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(gpioreg[PLLH_CTRL] >> 12) & 0x7,
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gpioreg[PLLH_CTRL] & 0x3ff,
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gpioreg[PLLH_FRAC],
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gpioreg[PLLH_AUX],
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gpioreg[PLLH_RCAL],
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gpioreg[PLLH_PIX],
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gpioreg[PLLH_STS]);
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// Dump the the actual PLL frequency
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double f3 = 19.2 * ((double)(gpioreg[PLLH_CTRL] & 0x3ff) + ((double)gpioreg[PLLH_FRAC]) / ((double)(1 << 20)));
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log_info(" Actual PLLH: %lf MHz", f3);
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}
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void action_scanlines(int on) {
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if (on) {
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scanlines = BIT_SCANLINES;
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@ -58,10 +58,18 @@
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# - 0 is vsync off
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# - 1 is vsync on
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#
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# pllh: controls the HDMI clock correction mode
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# - 0 is no correction
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# - 1 is correct for 623 lines
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# - 2 is correct for 623 lines
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# - 3 is correct for 625 lines
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# - 4 is correct for 626 lines
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# - 5 is correct for 627 lines
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#
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# debug: enables debug mode
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# - 0 is debug off
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# - 1 is debug on
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#
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# Important: All the properties must be on a single line, and no blank lines!
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#
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sampling06=3 sampling7=0,2,2,2,2,2,2,0 info=1 palette=0 scanlines=0 mux=0 elk=0 vsync=0 debug=0
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sampling06=3 sampling7=0,2,2,2,2,2,2,0 info=1 palette=0 scanlines=0 mux=0 elk=0 vsync=0 pllh=0 debug=0
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