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Add 9bpp and 1bpp support for simple mode

pull/248/head
IanSB 2021-10-28 19:20:36 +01:00
rodzic 72db148cf7
commit eced2ee5a2
7 zmienionych plików z 457 dodań i 469 usunięć
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441
src/capture_line_fast_simple_16bpp.S
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@ -5,19 +5,55 @@
.text
.global capture_line_fast_simple_trailing_pos_16bpp
.global capture_line_fast_simple_leading_pos_16bpp
.global capture_line_fast_simple_trailing_neg_16bpp
.global capture_line_fast_simple_leading_neg_16bpp
.global capture_line_fast_simple_trailing_both_16bpp
.global capture_line_fast_simple_leading_both_16bpp
.global capture_line_fast_simple_16bpp
.global capture_line_default_simple_16bpp
.global capture_line_fast_simple_sixbits_8bpp
.global capture_line_fast_simple_ninebitshi_16bpp
.global capture_line_fast_simple_ninebitslo_16bpp
.global capture_line_fast_simple_ninebitslo_16bpp_blank
.global capture_line_default_simple_trailing_pos_16bpp
.global capture_line_default_simple_leading_pos_16bpp
.global capture_line_default_simple_trailing_neg_16bpp
.global capture_line_default_simple_leading_neg_16bpp
.global capture_line_default_simple_trailing_both_16bpp
.global capture_line_default_simple_leading_both_16bpp
.macro SIMPLE_CAPTURE_LOW_BITS_8BPP_WIDE reg
// Pixel 0 in GPIO 7.. 2 -> 7.. 0
// Pixel 1 in GPIO 13.. 8 -> 15.. 8
tst r8, #(0x800 << PIXEL_BASE)
moveq r10, \reg
eorne r10, \reg, #0x3f
tst r8, #(0x080 << PIXEL_BASE)
eorne r10, r10, #0x3f00
.endm
.macro SIMPLE_CAPTURE_HIGH_BITS_8BPP_WIDE reg
// Pixel 2 in GPIO 7.. 2 -> 23..16
// Pixel 3 in GPIO 13.. 8 -> 31..24
tst r8, #(0x800 << PIXEL_BASE)
eorne r10, r10, #0x3f0000
tst r8, #(0x080 << PIXEL_BASE)
eorne \reg, r10, #0x3f000000
moveq \reg, r10
.endm
.macro BLANK_CAPTURE_NINELO_BITS_16BPP_LO reg
// Pixel in GPIO 13.. 2 -> 15.. 0
tst r8, #(0x008 << PIXEL_BASE)
moveq r8, #0
and r9, r8, r14
bic r8, r8, r14, lsr #1
eor r10, \reg, r9, lsr #(PIXEL_BASE - 1)
and r8, r8, r14
eor r10, r10, r8, lsr #(PIXEL_BASE + 2)
.endm
.macro BLANK_CAPTURE_NINELO_BITS_16BPP_HI reg
// Pixel in GPIO 13.. 2 -> 31.. 16
tst r8, #(0x008 << PIXEL_BASE)
moveq r8, #0
and r9, r8, r14
bic r8, r8, r14, lsr #1
eor r10, r10, r9, lsl #(16 - (PIXEL_BASE - 1))
and r8, r8, r14
eor \reg, r10, r8, lsl #(16 - (PIXEL_BASE + 2))
.endm
.macro SIMPLE_CAPTURE_TWELVE_BITS_16BPP_LO reg
// Pixel in GPIO 13.. 2 -> 15.. 0
@ -174,7 +210,6 @@ loop_16bpp_osd_default\@:
pop {r0, pc}
.endm
// The capture line function is provided the following:
// r0 = pointer to current line in frame buffer
// r1 = number of complete psync cycles to capture (=param_chars_per_line)
@ -188,143 +223,25 @@ loop_16bpp_osd_default\@:
//
// All registers are available as scratch registers (i.e. nothing needs to be preserved)
.ltorg
.align 6
// *** 16 bit ***
b preload_capture_line_fast_simple_trailing_pos_16bpp
capture_line_fast_simple_trailing_pos_16bpp:
b preload_capture_line_fast_simple_16bpp
capture_line_fast_simple_16bpp:
push {lr}
tst r3, #BITDUP_ENABLE_GREY_DETECT
orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
SETUP_VSYNC_DEBUG_16BPP_R11
SETUP_TWELVE_BITS_MASK_R14
bic r3, r3, #PSYNC_MASK // only +ve edge (inverted later)
tst r3, #BIT_OSD | BITDUP_ENABLE_GREY_DETECT
bne OSD_capture_line_fast_simple_trailing_pos_16bpp
SKIP_PSYNC_SIMPLE_TRAILING_SINGLE_EDGE_FAST
bne OSD_capture_line_fast_simple_16bpp
SKIP_PSYNC_SIMPLE_FAST
COMMON_SIMPLE
preload_capture_line_fast_simple_trailing_pos_16bpp:
preload_capture_line_fast_simple_16bpp:
SETUP_DUMMY_PARAMETERS
b capture_line_fast_simple_trailing_pos_16bpp
OSD_capture_line_fast_simple_trailing_pos_16bpp:
SKIP_PSYNC_SIMPLE_TRAILING_SINGLE_EDGE_FAST
OSD_COMMON_SIMPLE
.ltorg
.align 6
// *** 16 bit ***
b preload_capture_line_fast_simple_leading_pos_16bpp
capture_line_fast_simple_leading_pos_16bpp:
push {lr}
tst r3, #BITDUP_ENABLE_GREY_DETECT
orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
SETUP_VSYNC_DEBUG_16BPP_R11
SETUP_TWELVE_BITS_MASK_R14
bic r3, r3, #PSYNC_MASK // only +ve edge (inverted later)
tst r3, #BIT_OSD | BITDUP_ENABLE_GREY_DETECT
bne OSD_capture_line_fast_simple_leading_pos_16bpp
SKIP_PSYNC_SIMPLE_LEADING_SINGLE_EDGE_FAST
COMMON_SIMPLE
preload_capture_line_fast_simple_leading_pos_16bpp:
SETUP_DUMMY_PARAMETERS
b capture_line_fast_simple_leading_pos_16bpp
OSD_capture_line_fast_simple_leading_pos_16bpp:
SKIP_PSYNC_SIMPLE_LEADING_SINGLE_EDGE_FAST
OSD_COMMON_SIMPLE
.ltorg
.align 6
// *** 16 bit *** *** this one used by amiga
b preload_capture_line_fast_simple_trailing_neg_16bpp
capture_line_fast_simple_trailing_neg_16bpp:
push {lr}
tst r3, #BITDUP_ENABLE_GREY_DETECT
orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
SETUP_VSYNC_DEBUG_16BPP_R11
SETUP_TWELVE_BITS_MASK_R14
orr r3, r3, #PSYNC_MASK // only -ve edge (inverted later)
tst r3, #BIT_OSD
bne OSD_capture_line_fast_simple_trailing_neg_16bpp
SKIP_PSYNC_SIMPLE_TRAILING_SINGLE_EDGE_FAST
COMMON_SIMPLE
preload_capture_line_fast_simple_trailing_neg_16bpp:
SETUP_DUMMY_PARAMETERS
b capture_line_fast_simple_trailing_neg_16bpp
OSD_capture_line_fast_simple_trailing_neg_16bpp:
SKIP_PSYNC_SIMPLE_TRAILING_SINGLE_EDGE_FAST
OSD_COMMON_SIMPLE
.ltorg
.align 6
// *** 16 bit ***
b preload_capture_line_fast_simple_leading_neg_16bpp
capture_line_fast_simple_leading_neg_16bpp:
push {lr}
tst r3, #BITDUP_ENABLE_GREY_DETECT
orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
SETUP_VSYNC_DEBUG_16BPP_R11
SETUP_TWELVE_BITS_MASK_R14
orr r3, r3, #PSYNC_MASK // only -ve edge (inverted later)
tst r3, #BIT_OSD
bne OSD_capture_line_fast_simple_leading_neg_16bpp
SKIP_PSYNC_SIMPLE_LEADING_SINGLE_EDGE_FAST
COMMON_SIMPLE
preload_capture_line_fast_simple_leading_neg_16bpp:
SETUP_DUMMY_PARAMETERS
b capture_line_fast_simple_leading_neg_16bpp
OSD_capture_line_fast_simple_leading_neg_16bpp:
SKIP_PSYNC_SIMPLE_LEADING_SINGLE_EDGE_FAST
OSD_COMMON_SIMPLE
.ltorg
.align 6
// *** 16 bit ***
b preload_capture_line_fast_simple_trailing_both_16bpp
capture_line_fast_simple_trailing_both_16bpp:
push {lr}
tst r3, #BITDUP_ENABLE_GREY_DETECT
orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
SETUP_VSYNC_DEBUG_16BPP_R11
SETUP_TWELVE_BITS_MASK_R14
tst r3, #BIT_OSD
bne OSD_capture_line_fast_simple_trailing_both_16bpp
SKIP_PSYNC_SIMPLE_TRAILING_FAST
COMMON_SIMPLE
preload_capture_line_fast_simple_trailing_both_16bpp:
SETUP_DUMMY_PARAMETERS
b capture_line_fast_simple_trailing_both_16bpp
OSD_capture_line_fast_simple_trailing_both_16bpp:
SKIP_PSYNC_SIMPLE_TRAILING_FAST
OSD_COMMON_SIMPLE
.ltorg
.align 6
// *** 16 bit ***
b preload_capture_line_fast_simple_leading_both_16bpp
capture_line_fast_simple_leading_both_16bpp:
push {lr}
tst r3, #BITDUP_ENABLE_GREY_DETECT
orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
SETUP_VSYNC_DEBUG_16BPP_R11
SETUP_TWELVE_BITS_MASK_R14
tst r3, #BIT_OSD
bne OSD_capture_line_fast_simple_leading_both_16bpp
SKIP_PSYNC_SIMPLE_LEADING_FAST
COMMON_SIMPLE
preload_capture_line_fast_simple_leading_both_16bpp:
SETUP_DUMMY_PARAMETERS
b capture_line_fast_simple_leading_both_16bpp
OSD_capture_line_fast_simple_leading_both_16bpp:
SKIP_PSYNC_SIMPLE_LEADING_FAST
b capture_line_fast_simple_16bpp
OSD_capture_line_fast_simple_16bpp:
SKIP_PSYNC_SIMPLE_FAST
OSD_COMMON_SIMPLE
//*********************************************
@ -332,139 +249,185 @@ OSD_capture_line_fast_simple_leading_both_16bpp:
.ltorg
.align 6
// *** 16 bit ***
b preload_capture_line_default_simple_trailing_pos_16bpp
capture_line_default_simple_trailing_pos_16bpp:
b preload_capture_line_default_simple_16bpp
capture_line_default_simple_16bpp:
push {lr}
tst r3, #BITDUP_ENABLE_GREY_DETECT
orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
mov r10, r2
SETUP_VSYNC_DEBUG_16BPP_R11
SETUP_TWELVE_BITS_MASK_R14
bic r3, r3, #PSYNC_MASK // only +ve edge (inverted later)
tst r3, #BIT_OSD
bne OSD_capture_line_default_simple_trailing_pos_16bpp
SKIP_PSYNC_SIMPLE_TRAILING_SINGLE_EDGE_FAST
bne OSD_capture_line_default_simple_16bpp
SKIP_PSYNC_SIMPLE_FAST
COMMON_DEFAULT
preload_capture_line_default_simple_trailing_pos_16bpp:
preload_capture_line_default_simple_16bpp:
SETUP_DUMMY_PARAMETERS
b capture_line_default_simple_trailing_pos_16bpp
OSD_capture_line_default_simple_trailing_pos_16bpp:
SKIP_PSYNC_SIMPLE_TRAILING_SINGLE_EDGE_FAST
b capture_line_default_simple_16bpp
OSD_capture_line_default_simple_16bpp:
SKIP_PSYNC_SIMPLE_FAST
OSD_COMMON_DEFAULT
.ltorg
// *** 8 bit ***
.align 6
b preload_capture_line_fast_sixbits_8bpp
capture_line_fast_simple_sixbits_8bpp:
push {lr}
SETUP_VSYNC_DEBUG_R11_R12
SKIP_PSYNC_SIMPLE_FAST
loop_8bpp:
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
SIMPLE_CAPTURE_LOW_BITS_8BPP_WIDE r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
SIMPLE_CAPTURE_HIGH_BITS_8BPP_WIDE r5 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
SIMPLE_CAPTURE_LOW_BITS_8BPP_WIDE r12 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
SIMPLE_CAPTURE_HIGH_BITS_8BPP_WIDE r6 // input in r8
cmp r1, #1
stmeqia r0, {r5, r6}
moveq r0, r2
popeq {pc}
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
SIMPLE_CAPTURE_LOW_BITS_8BPP_WIDE r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
SIMPLE_CAPTURE_HIGH_BITS_8BPP_WIDE r7 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
SIMPLE_CAPTURE_LOW_BITS_8BPP_WIDE r12 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
SIMPLE_CAPTURE_HIGH_BITS_8BPP_WIDE r10 // input in r8
stmia r0!, {r5, r6, r7, r10}
subs r1, r1, #2
bne loop_8bpp
mov r0, r2
pop {pc}
preload_capture_line_fast_sixbits_8bpp:
SETUP_DUMMY_PARAMETERS
b capture_line_fast_sixbits_8bpp
.ltorg
.align 6
// *** 16 bit ***
b preload_capture_line_default_simple_leading_pos_16bpp
capture_line_default_simple_leading_pos_16bpp:
b preload_capture_line_fast_ninebitslo_16bpp
capture_line_fast_simple_ninebitslo_16bpp:
push {lr}
tst r3, #BITDUP_ENABLE_GREY_DETECT
orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
mov r10, r2
SETUP_VSYNC_DEBUG_16BPP_R11
SETUP_TWELVE_BITS_MASK_R14
bic r3, r3, #PSYNC_MASK // only +ve edge (inverted later)
tst r3, #BIT_OSD
bne OSD_capture_line_default_simple_leading_pos_16bpp
SKIP_PSYNC_SIMPLE_LEADING_SINGLE_EDGE_FAST
COMMON_DEFAULT
preload_capture_line_default_simple_leading_pos_16bpp:
SETUP_DUMMY_PARAMETERS
b capture_line_default_simple_leading_pos_16bpp
OSD_capture_line_default_simple_leading_pos_16bpp:
SKIP_PSYNC_SIMPLE_LEADING_SINGLE_EDGE_FAST
OSD_COMMON_DEFAULT
SKIP_PSYNC_SIMPLE_FAST
SETUP_NINELO_BITS_MASK_R14
loop_16lobpp:
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINELO_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINELO_BITS_16BPP_HI r5 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINELO_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINELO_BITS_16BPP_HI r6 // input in r8
.ltorg
.align 6
// *** 16 bit *** this one used by amiga
b preload_capture_line_default_simple_trailing_neg_16bpp
capture_line_default_simple_trailing_neg_16bpp:
push {lr}
tst r3, #BITDUP_ENABLE_GREY_DETECT
orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
mov r10, r2
SETUP_VSYNC_DEBUG_16BPP_R11
SETUP_TWELVE_BITS_MASK_R14
orr r3, r3, #PSYNC_MASK // only -ve edge (inverted later)
tst r3, #BIT_OSD
bne OSD_capture_line_default_simple_trailing_neg_16bpp
SKIP_PSYNC_SIMPLE_TRAILING_SINGLE_EDGE_FAST
COMMON_DEFAULT
preload_capture_line_default_simple_trailing_neg_16bpp:
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINELO_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINELO_BITS_16BPP_HI r7 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINELO_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINELO_BITS_16BPP_HI r10 // input in r8
stmia r0!, {r5, r6, r7, r10}
subs r1, r1, #1
bne loop_16lobpp
mov r0, r2
pop {pc}
preload_capture_line_fast_ninebitslo_16bpp:
SETUP_DUMMY_PARAMETERS
b capture_line_default_simple_trailing_neg_16bpp
OSD_capture_line_default_simple_trailing_neg_16bpp:
SKIP_PSYNC_SIMPLE_TRAILING_SINGLE_EDGE_FAST
OSD_COMMON_DEFAULT
b capture_line_fast_ninebitslo_16bpp
.ltorg
.align 6
// *** 16 bit ***
b preload_capture_line_default_simple_leading_neg_16bpp
capture_line_default_simple_leading_neg_16bpp:
b preload_capture_line_fast_ninebitslo_16bpp_blank
capture_line_fast_simple_ninebitslo_16bpp_blank:
push {lr}
tst r3, #BITDUP_ENABLE_GREY_DETECT
orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
mov r10, r2
SETUP_VSYNC_DEBUG_16BPP_R11
SETUP_TWELVE_BITS_MASK_R14
orr r3, r3, #PSYNC_MASK // only -ve edge (inverted later)
tst r3, #BIT_OSD
bne OSD_capture_line_default_simple_leading_neg_16bpp
SKIP_PSYNC_SIMPLE_LEADING_SINGLE_EDGE_FAST
COMMON_DEFAULT
preload_capture_line_default_simple_leading_neg_16bpp:
SETUP_DUMMY_PARAMETERS
b capture_line_default_simple_leading_neg_16bpp
OSD_capture_line_default_simple_leading_neg_16bpp:
SKIP_PSYNC_SIMPLE_LEADING_SINGLE_EDGE_FAST
OSD_COMMON_DEFAULT
SKIP_PSYNC_SIMPLE_FAST
SETUP_NINELO_BITS_MASK_R14
loop_16lobpp_blank:
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
BLANK_CAPTURE_NINELO_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
BLANK_CAPTURE_NINELO_BITS_16BPP_HI r5 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
BLANK_CAPTURE_NINELO_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
BLANK_CAPTURE_NINELO_BITS_16BPP_HI r6 // input in r8
.ltorg
.align 6
// *** 16 bit ***
b preload_capture_line_default_simple_trailing_both_16bpp
capture_line_default_simple_trailing_both_16bpp:
push {lr}
tst r3, #BITDUP_ENABLE_GREY_DETECT
orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
mov r10, r2
SETUP_VSYNC_DEBUG_16BPP_R11
SETUP_TWELVE_BITS_MASK_R14
tst r3, #BIT_OSD
bne capture_line_default_simple_trailing_both_16bpp
SKIP_PSYNC_SIMPLE_TRAILING_FAST
COMMON_DEFAULT
preload_capture_line_default_simple_trailing_both_16bpp:
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
BLANK_CAPTURE_NINELO_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
BLANK_CAPTURE_NINELO_BITS_16BPP_HI r7 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
BLANK_CAPTURE_NINELO_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
BLANK_CAPTURE_NINELO_BITS_16BPP_HI r10 // input in r8
stmia r0!, {r5, r6, r7, r10}
subs r1, r1, #1
bne loop_16lobpp_blank
mov r0, r2
pop {pc}
preload_capture_line_fast_ninebitslo_16bpp_blank:
SETUP_DUMMY_PARAMETERS
b capture_line_default_simple_trailing_both_16bpp
OSD_capture_line_default_simple_trailing_both_16bpp:
SKIP_PSYNC_SIMPLE_TRAILING_FAST
OSD_COMMON_DEFAULT
b capture_line_fast_simple_ninebitslo_16bpp_blank
.ltorg
.align 6
// *** 16 bit ***
b preload_capture_line_default_simple_leading_both_16bpp
capture_line_default_simple_leading_both_16bpp:
b preload_capture_line_fast_ninebitshi_16bpp
capture_line_fast_simple_ninebitshi_16bpp:
push {lr}
tst r3, #BITDUP_ENABLE_GREY_DETECT
orrne r3, r3, #BITDUP_LINE_CONDITION_DETECTED
mov r10, r2
SETUP_VSYNC_DEBUG_16BPP_R11
SETUP_TWELVE_BITS_MASK_R14
tst r3, #BIT_OSD
bne OSD_capture_line_default_simple_leading_both_16bpp
SKIP_PSYNC_SIMPLE_LEADING_FAST
COMMON_DEFAULT
preload_capture_line_default_simple_leading_both_16bpp:
SETUP_DUMMY_PARAMETERS
b capture_line_default_simple_leading_both_16bpp
OSD_capture_line_default_simple_leading_both_16bpp:
SKIP_PSYNC_SIMPLE_LEADING_FAST
OSD_COMMON_DEFAULT
SKIP_PSYNC_SIMPLE_FAST
SETUP_NINEHI_BITS_MASK_R14
loop_16hibpp:
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINEHI_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINEHI_BITS_16BPP_HI r5 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINEHI_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINEHI_BITS_16BPP_HI r6 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINEHI_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINEHI_BITS_16BPP_HI r7 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINEHI_BITS_16BPP_LO r11 // input in r8
WAIT_FOR_PSYNC_EDGE_FAST // expects GPLEV0 in r4, result in r8
CAPTURE_NINEHI_BITS_16BPP_HI r10 // input in r8
stmia r0!, {r5, r6, r7, r10}
subs r1, r1, #1
bne loop_16hibpp
mov r0, r2
pop {pc}
preload_capture_line_fast_ninebitshi_16bpp:
SETUP_DUMMY_PARAMETERS
b capture_line_fast_ninebitshi_16bpp

107
src/cpld_simple.c
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@ -72,13 +72,32 @@ enum {
};
enum {
RGB_RATE_3, //00
RGB_RATE_6, //01
RGB_RATE_4_LEVEL, //10 - 6x2 in digital mode and 4 level in analog mode
RGB_RATE_12, //11
RGB_RATE_3, //000
RGB_RATE_6, //001
RGB_RATE_9V, //011
RGB_RATE_9LO, //011
RGB_RATE_9HI, //011
RGB_RATE_12, //011
RGB_RATE_9LO_BLANKED, //011
RGB_RATE_4_LEVEL, //001
RGB_RATE_1, //010
RGB_RATE_1_VSYNC, //010
NUM_RGB_RATE
};
static const char *rate_names[] = {
"3 Bits Per Pixel",
"1 Bit (R3 & G3)",
"9 Bits (V Sync)",
"9 Bits (Bits 0-2)",
"9 Bits (Bits 1-3)",
"12 Bits Per Pixel",
"9 Bits 0-2 Blanked",
"6 Bits (4 Level)",
"1 Bit Per Pixel",
"1 Bit On Vsync",
};
enum {
RGB_INPUT_HI,
RGB_INPUT_TERM,
@ -147,7 +166,7 @@ static param_t params[] = {
{ CLAMPTYPE, "Clamp Type", "clamptype", 0, 4, 1 },
//end of hidden block
{ MUX, "Sync on G/V", "input_mux", 0, 1, 1 },
{ RATE, "Sample Mode", "sample_mode", 0, NUM_RGB_RATE-1, 1 },
{ RATE, "Sample Mode", "sample_mode", 1, NUM_RGB_RATE-4, 1 },
{ TERMINATE, "75R Termination", "termination", 0, NUM_RGB_TERM-1, 1 },
{ COUPLING, "G Coupling", "coupling", 0, NUM_RGB_COUPLING-1, 1 },
{ DAC_A, "DAC-A: G Hi", "dac_a", 0, 256, 1 },
@ -186,7 +205,7 @@ static void cpld_init(int version) {
// params[EDGE].hidden = 1;
params[CLAMPTYPE].hidden = 1;
params[MUX].hidden = 1;
params[RATE].hidden = 1;
// params[RATE].hidden = 1;
params[TERMINATE].hidden = 1;
params[COUPLING].hidden = 1;
params[DAC_A].hidden = 1;
@ -223,28 +242,61 @@ static int cpld_analyse(int selected_sync_state, int analyse) {
static void cpld_update_capture_info(capture_info_t *capinfo) {
if (capinfo) {
capinfo->sample_width = SAMPLE_WIDTH_12;
switch (config->edge) {
case EDGE_TRAIL_NEG:
capinfo->capture_line = capture_line_simple_12bpp_trailing_neg_table;
break;
case EDGE_LEAD_NEG:
capinfo->capture_line = capture_line_simple_12bpp_leading_neg_table;
break;
case EDGE_TRAIL_POS:
capinfo->capture_line = capture_line_simple_12bpp_trailing_pos_table;
break;
case EDGE_LEAD_POS:
capinfo->capture_line = capture_line_simple_12bpp_leading_pos_table;
break;
case EDGE_TRAIL_BOTH:
capinfo->capture_line = capture_line_simple_12bpp_trailing_both_table;
break;
case EDGE_LEAD_BOTH:
capinfo->capture_line = capture_line_simple_12bpp_leading_both_table;
break;
switch(config->rate) {
default:
case RGB_RATE_1:
case RGB_RATE_1_VSYNC:
capinfo->sample_width = SAMPLE_WIDTH_1;
break;
case RGB_RATE_3:
capinfo->sample_width = SAMPLE_WIDTH_3;
break;
case RGB_RATE_6:
case RGB_RATE_4_LEVEL:
capinfo->sample_width = SAMPLE_WIDTH_6;
break;
case RGB_RATE_9V:
case RGB_RATE_9HI:
capinfo->sample_width = SAMPLE_WIDTH_9HI;
break;
case RGB_RATE_9LO:
case RGB_RATE_9LO_BLANKED:
capinfo->sample_width = SAMPLE_WIDTH_9LO;
break;
case RGB_RATE_12:
capinfo->sample_width = SAMPLE_WIDTH_12;
break;
}
// Update the line capture function
switch (capinfo->sample_width) {
case SAMPLE_WIDTH_1 :
capinfo->capture_line = capture_line_normal_1bpp_table;
break;
case SAMPLE_WIDTH_3:
capinfo->capture_line = capture_line_normal_3bpp_table;
break;
case SAMPLE_WIDTH_6 :
capinfo->capture_line = capture_line_simple_6bpp_table;
break;
case SAMPLE_WIDTH_9LO :
if (config->rate == RGB_RATE_9LO_BLANKED) {
capinfo->capture_line = capture_line_simple_9bpplo_blank_table;
} else {
capinfo->capture_line = capture_line_simple_9bpplo_table;
}
break;
case SAMPLE_WIDTH_9HI :
capinfo->capture_line = capture_line_simple_9bpphi_table;
break;
default:
case SAMPLE_WIDTH_12 :
capinfo->capture_line = capture_line_simple_12bpp_table;
break;
}
}
}
static param_t *cpld_get_params() {
@ -323,6 +375,9 @@ static const char *cpld_get_value_string(int num) {
if (num == CPLD_SETUP_MODE) {
return cpld_setup_names[config->cpld_setup_mode];
}
if (num == RATE) {
return rate_names[config->rate];
}
return NULL;
}

6
src/defs.h
Wyświetl plik

@ -169,8 +169,9 @@
#define O_INTENSITY 88
#define O_AUTOSWITCH 92
#define O_TIMINGSET 96
#define O_MODE7 100
#define O_CAPTURE_LINE 104
#define O_SYNCEDGE 100
#define O_MODE7 104
#define O_CAPTURE_LINE 108
#else
@ -200,6 +201,7 @@ typedef struct {
int intensity; // scanline intensity
int autoswitch; // autoswitch detect mode
int timingset; // 0 = set1, 1 = set 2
int sync_edge; // sync edge setting
int mode7; // mode7 flag
int (*capture_line)(); // the capture line function to use
int px_sampling; // whether to sample normally, sub-sample or pixel double

1
src/geometry.c
Wyświetl plik

@ -423,6 +423,7 @@ void geometry_get_fb_params(capture_info_t *capinfo) {
capinfo->video_type = geometry->video_type;
capinfo->autoswitch = get_autoswitch();
capinfo->timingset = modeset;
capinfo->sync_edge = cpld->get_sync_edge();
capinfo->sizex2 = geometry->fb_sizex2;
switch(geometry->fb_bpp) {

109
src/macros.S
Wyświetl plik

@ -300,32 +300,56 @@ skip_psync_loop_no_old_fast\@:
bne skip_psync_loop_no_old_fast\@
.endm
.macro IMPLEMENT_SIMPLE_DELAY
.macro SKIP_PSYNC_SIMPLE_FAST
ldr r8, =param_delay
ldr r8, [r8]
add r7, r7, r8
.endm
.macro SKIP_PSYNC_SIMPLE_LEADING_SINGLE_EDGE_FAST
//incoming psync state controls edge
IMPLEMENT_SIMPLE_DELAY
wait_csync_lo_fast\@:
WAIT_FOR_PSYNC_EDGE_FAST
WAIT_FOR_PSYNC_EDGE_FAST
ldr r8, =param_sync_edge
ldr r8, [r8]
orr r3, r3, #PSYNC_MASK // only -ve edge (inverted later)
cmp r8, #0
beq edge_trail_neg\@
cmp r8, #1
beq edge_lead_neg\@
bic r3, r3, #PSYNC_MASK // only +ve edge (inverted later)
cmp r8, #2
beq edge_trail_pos\@
cmp r8, #3
beq edge_lead_pos\@
cmp r8, #4
beq edge_trail_both\@
// cmp r8, #5
// beq edge_lead_both\@
//edge_lead_both\@:
// bic r3, r3, #PSYNC_MASK // wait for zero
wait_csync_lo_fast3\@:
WAIT_FOR_PSYNC_EDGE_FAST // wait for next edge of psync
tst r3, #BIT_NO_SKIP_HSYNC
tstne r8, #CSYNC_MASK
bne wait_csync_lo_fast\@
bne wait_csync_lo_fast3\@
READ_CYCLE_COUNTER r2 //store timestamp in R2 instead of stack for fast mode
// Skip the configured number of psync edges (modes 0..6: edges every 250ns, mode 7: edges ever 333ns)
skip_psync_loop_simple_leading_fast\@:
WAIT_FOR_PSYNC_EDGE_FAST // wait for next edge of psync
subs r7, r7, #1
bne skip_psync_loop_simple_leading_fast\@
.endm
b skip_psync_loop_simple_fast\@
.macro SKIP_PSYNC_SIMPLE_TRAILING_SINGLE_EDGE_FAST
edge_trail_both\@:
// bic r3, r3, #PSYNC_MASK // wait for zero
wait_csync_lo_fast4\@:
WAIT_FOR_PSYNC_EDGE_FAST // wait for next edge of psync
tst r3, #BIT_NO_SKIP_HSYNC
tstne r8, #CSYNC_MASK
bne wait_csync_lo_fast4\@
READ_CYCLE_COUNTER r2 //store timestamp in R2 instead of stack for fast mode
eor r3, r3, #BIT_NO_SKIP_HSYNC
wait_csync_hi_fast4\@:
WAIT_FOR_PSYNC_EDGE_FAST // wait for next edge of psync
tst r3, #BIT_NO_SKIP_HSYNC
tsteq r8, #CSYNC_MASK
beq wait_csync_hi_fast4\@
eor r3, r3, #BIT_NO_SKIP_HSYNC
b skip_psync_loop_simple_fast\@
edge_trail_neg\@:
edge_trail_pos\@:
//incoming psync state controls edge *** this one used by amiga
IMPLEMENT_SIMPLE_DELAY
wait_csync_lo_fast2\@:
WAIT_FOR_PSYNC_EDGE_FAST
WAIT_FOR_PSYNC_EDGE_FAST
@ -342,52 +366,25 @@ wait_csync_hi_fast\@:
beq wait_csync_hi_fast\@
eor r3, r3, #BIT_NO_SKIP_HSYNC
// Skip the configured number of psync edges (modes 0..6: edges every 250ns, mode 7: edges ever 333ns)
skip_psync_loop_simple_trailing_fast\@:
WAIT_FOR_PSYNC_EDGE_FAST // wait for next edge of psync
subs r7, r7, #1
bne skip_psync_loop_simple_trailing_fast\@
.endm
b skip_psync_loop_simple_fast\@
.macro SKIP_PSYNC_SIMPLE_LEADING_FAST
bic r3, r3, #PSYNC_MASK // wait for zero
IMPLEMENT_SIMPLE_DELAY
wait_csync_lo_fast3\@:
WAIT_FOR_PSYNC_EDGE_FAST // wait for next edge of psync
edge_lead_neg\@:
edge_lead_pos\@:
//incoming psync state controls edge
wait_csync_lo_fast\@:
WAIT_FOR_PSYNC_EDGE_FAST
WAIT_FOR_PSYNC_EDGE_FAST
tst r3, #BIT_NO_SKIP_HSYNC
tstne r8, #CSYNC_MASK
bne wait_csync_lo_fast3\@
bne wait_csync_lo_fast\@
READ_CYCLE_COUNTER r2 //store timestamp in R2 instead of stack for fast mode
// Skip the configured number of psync edges (modes 0..6: edges every 250ns, mode 7: edges ever 333ns)
skip_psync_loop_simple_leading_fast3\@:
skip_psync_loop_simple_fast\@:
WAIT_FOR_PSYNC_EDGE_FAST // wait for next edge of psync
subs r7, r7, #1
bne skip_psync_loop_simple_leading_fast3\@
bne skip_psync_loop_simple_fast\@
.endm
.macro SKIP_PSYNC_SIMPLE_TRAILING_FAST
bic r3, r3, #PSYNC_MASK // wait for zero
IMPLEMENT_SIMPLE_DELAY
wait_csync_lo_fast4\@:
WAIT_FOR_PSYNC_EDGE_FAST // wait for next edge of psync
tst r3, #BIT_NO_SKIP_HSYNC
tstne r8, #CSYNC_MASK
bne wait_csync_lo_fast4\@
READ_CYCLE_COUNTER r2 //store timestamp in R2 instead of stack for fast mode
eor r3, r3, #BIT_NO_SKIP_HSYNC
wait_csync_hi_fast4\@:
WAIT_FOR_PSYNC_EDGE_FAST // wait for next edge of psync
tst r3, #BIT_NO_SKIP_HSYNC
tsteq r8, #CSYNC_MASK
beq wait_csync_hi_fast4\@
eor r3, r3, #BIT_NO_SKIP_HSYNC
// Skip the configured number of psync edges (modes 0..6: edges every 250ns, mode 7: edges ever 333ns)
skip_psync_loop_simple_trailing_fast4\@:
WAIT_FOR_PSYNC_EDGE_FAST // wait for next edge of psync
subs r7, r7, #1
bne skip_psync_loop_simple_trailing_fast4\@
.endm
//.macro SKIP_PSYNC_NO_H_SCROLL
// // only called if in fast mode (both 3 & 6 bpp) - fast mode never called from old CPLDs v1 & v2
// WAIT_FOR_CSYNC_0_FAST_SKIP_HSYNC

250
src/rgb_to_fb.S
Wyświetl plik

@ -39,6 +39,7 @@
.global ntsc_status
.global param_delay
.global param_intensity
.global param_sync_edge
.global sw1_power_up
.global field_type_threshold
@ -80,13 +81,11 @@
.global capture_line_half_odd_3bpp_table
.global capture_line_half_even_3bpp_table
.global capture_line_simple_12bpp_trailing_pos_table
.global capture_line_simple_12bpp_leading_pos_table
.global capture_line_simple_12bpp_trailing_neg_table
.global capture_line_simple_12bpp_leading_neg_table
.global capture_line_simple_12bpp_trailing_both_table
.global capture_line_simple_12bpp_leading_both_table
.global capture_line_simple_6bpp_table
.global capture_line_simple_9bpplo_table
.global capture_line_simple_9bpplo_blank_table
.global capture_line_simple_9bpphi_table
.global capture_line_simple_12bpp_table
#define FRAME_COUNT_MAX 7
@ -154,6 +153,8 @@ rgb_to_fb:
str r2, param_autoswitch
ldr r2, [r0, #O_TIMINGSET]
str r2, param_timingset
ldr r2, [r0, #O_SYNCEDGE]
str r2, param_sync_edge
ldr r2, [r0, #O_FB_BASE]
str r2, param_framebuffer0
@ -884,6 +885,9 @@ param_autoswitch:
param_timingset:
.word 0
param_sync_edge:
.word 0
param_framebuffer0:
.word 0
@ -2358,7 +2362,6 @@ capture_line_normal_9bpplo_table:
.word capture_line_fast_ninebitslo_16bpp
.word capture_line_fast_eightbits_8bpp
capture_line_normal_9bpphi_table:
.word capture_line_default_ninebitshi_16bpp
.word capture_line_default_eightbits_8bpp
@ -2427,123 +2430,159 @@ capture_line_normal_12bpp_table:
.word capture_line_fast_twelvebits_16bpp
.word capture_line_fast_eightbits_8bpp
capture_line_simple_12bpp_trailing_pos_table:
.word capture_line_default_simple_trailing_pos_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_pos_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_pos_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_pos_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_pos_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_pos_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_pos_16bpp
.word capture_line_default_eightbits_8bpp
capture_line_simple_6bpp_table:
.word capture_line_default_sixbits_16bpp
.word capture_line_default_sixbits_8bpp
.word capture_line_default_sixbits_16bpp // placeholder inband
.word capture_line_default_sixbits_8bpp // placeholder inband
.word capture_line_default_sixbits_16bpp
.word capture_line_ntsc_sixbits_8bpp_cga
.word capture_line_default_sixbits_16bpp
.word capture_line_ntsc_sixbits_8bpp_mono
.word capture_line_default_sixbits_16bpp
.word capture_line_ntsc_sixbits_8bpp_mono_auto
.word capture_line_default_sixbits_16bpp
.word capture_line_default_sixbits_8bpp
.word capture_line_default_sixbits_16bpp
.word capture_line_atari_sixbits_8bpp
.word capture_line_default_sixbits_double_16bpp
.word capture_line_default_sixbits_double_8bpp
.word capture_line_default_sixbits_double_16bpp // placeholder inband
.word capture_line_default_sixbits_double_8bpp // placeholder inband
.word capture_line_default_sixbits_double_16bpp // placeholder ntsc
.word capture_line_ntsc_sixbits_double_8bpp_mono // placeholder ntsc
.word capture_line_default_sixbits_double_16bpp // placeholder ntsc
.word capture_line_ntsc_sixbits_double_8bpp_mono // for tandy coco 1 & 2
.word capture_line_default_sixbits_double_16bpp // placeholder ntsc
.word capture_line_ntsc_sixbits_double_8bpp_mono_auto // for tandy coco 1 & 2 auto switches if UV = no colour
.word capture_line_default_sixbits_double_16bpp
.word capture_line_default_sixbits_double_8bpp
.word capture_line_default_sixbits_double_16bpp
.word capture_line_atari_sixbits_double_8bpp
.word capture_line_fast_sixbits_16bpp
.word capture_line_fast_simple_sixbits_8bpp
.word capture_line_default_twelvebits_double_16bpp
capture_line_simple_9bpplo_table:
.word capture_line_default_ninebitslo_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_ninebitslo_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_ninebitslo_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_ninebitslo_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_ninebitslo_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_ninebitslo_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_ninebitslo_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_ninebitslo_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitslo_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitslo_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitslo_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitslo_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitslo_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitslo_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_fast_simple_trailing_pos_16bpp
.word capture_line_fast_simple_ninebitslo_16bpp
.word capture_line_fast_eightbits_8bpp
capture_line_simple_12bpp_leading_pos_table:
.word capture_line_default_simple_leading_pos_16bpp
capture_line_simple_9bpplo_blank_table:
.word capture_line_default_ninebitslo_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_pos_16bpp
.word capture_line_default_ninebitslo_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_pos_16bpp
.word capture_line_default_ninebitslo_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_pos_16bpp
.word capture_line_default_ninebitslo_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_pos_16bpp
.word capture_line_default_ninebitslo_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_pos_16bpp
.word capture_line_default_ninebitslo_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_pos_16bpp
.word capture_line_default_ninebitslo_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitslo_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitslo_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitslo_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitslo_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitslo_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitslo_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitslo_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_fast_simple_leading_pos_16bpp
.word capture_line_fast_simple_ninebitslo_16bpp_blank
.word capture_line_fast_eightbits_8bpp
capture_line_simple_12bpp_trailing_neg_table:
.word capture_line_default_simple_trailing_neg_16bpp
capture_line_simple_9bpphi_table:
.word capture_line_default_ninebitshi_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_neg_16bpp
.word capture_line_default_ninebitshi_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_neg_16bpp
.word capture_line_default_ninebitshi_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_neg_16bpp
.word capture_line_default_ninebitshi_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_neg_16bpp
.word capture_line_default_ninebitshi_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_neg_16bpp
.word capture_line_default_ninebitshi_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_neg_16bpp
.word capture_line_default_ninebitshi_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitshi_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitshi_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitshi_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitshi_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitshi_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitshi_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_ninebitshi_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_fast_simple_trailing_neg_16bpp
.word capture_line_fast_simple_ninebitshi_16bpp
.word capture_line_fast_eightbits_8bpp
capture_line_simple_12bpp_leading_neg_table:
.word capture_line_default_simple_leading_neg_16bpp
capture_line_simple_12bpp_table:
.word capture_line_default_simple_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_neg_16bpp
.word capture_line_default_simple_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_neg_16bpp
.word capture_line_default_simple_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_neg_16bpp
.word capture_line_default_simple_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_neg_16bpp
.word capture_line_default_simple_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_neg_16bpp
.word capture_line_default_simple_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_neg_16bpp
.word capture_line_default_simple_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_twelvebits_double_16bpp
@ -2561,76 +2600,9 @@ capture_line_simple_12bpp_leading_neg_table:
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_fast_simple_leading_neg_16bpp
.word capture_line_fast_simple_16bpp
.word capture_line_fast_eightbits_8bpp
capture_line_simple_12bpp_trailing_both_table:
.word capture_line_default_simple_trailing_both_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_both_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_both_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_both_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_both_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_both_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_trailing_both_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_fast_simple_trailing_both_16bpp
.word capture_line_fast_eightbits_8bpp
capture_line_simple_12bpp_leading_both_table:
.word capture_line_default_simple_leading_both_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_both_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_both_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_both_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_both_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_both_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_simple_leading_both_16bpp
.word capture_line_default_eightbits_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_default_twelvebits_double_16bpp
.word capture_line_default_eightbits_double_8bpp
.word capture_line_fast_simple_leading_both_16bpp
.word capture_line_fast_eightbits_8bpp
// tables below are deprecated and will be removed in future

12
src/rgb_to_fb.h
Wyświetl plik

@ -43,13 +43,11 @@ extern int capture_line_double_3bpp_table();
extern int capture_line_half_odd_3bpp_table();
extern int capture_line_half_even_3bpp_table();
extern int capture_line_simple_12bpp_leading_pos_table();
extern int capture_line_simple_12bpp_trailing_pos_table();
extern int capture_line_simple_12bpp_leading_neg_table();
extern int capture_line_simple_12bpp_trailing_neg_table();
extern int capture_line_simple_12bpp_leading_both_table();
extern int capture_line_simple_12bpp_trailing_both_table();
extern int capture_line_simple_6bpp_table();
extern int capture_line_simple_9bpplo_table();
extern int capture_line_simple_9bpplo_blank_table();
extern int capture_line_simple_9bpphi_table();
extern int capture_line_simple_12bpp_table();
extern int vsync_line;
extern int total_lines;