kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
vhdl_YUV: Fix sync dection bug when sync out of range (v8.1)
Change-Id: I98fbbb32ced4fdded40c14ef8f741de6f0a415bdyuv80
rodzic
7ab3e15574
commit
e95ee77dab
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@ -49,7 +49,7 @@ architecture Behavorial of RGBtoHDMI is
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-- Version number: Design_Major_Minor
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-- Design: 0 = Normal CPLD, 1 = Alternative CPLD, 2=Atom CPLD, 3=YUV6847 CPLD
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constant VERSION_NUM : std_logic_vector(11 downto 0) := x"380";
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constant VERSION_NUM : std_logic_vector(11 downto 0) := x"381";
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-- NOTE: the difference between the leading and trailing offsets is
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-- 256 clks = 32 pixel clocks.
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@ -236,7 +236,7 @@ begin
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if HS3 = '0' and HS2 = '1' then
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-- Stop sampling on the trailing edge of HSYNC
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sampling <= '0';
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elsif HS2 = '1' and counter = "1111111" then
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elsif counter = "1111111" then
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-- Start sampling when the counter expires
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sampling <= '1';
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end if;
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@ -379,8 +379,9 @@ begin
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inv_R <= '1';
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end if;
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-- generate the csync output
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csync <= HS2;
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-- generate the csync output from the most delayed version of HS
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-- (csync adds an extra register, could save this in future)
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csync <= HS5;
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end if;
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end process;
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@ -129,3 +129,14 @@ FB3 17/18 34/54 90/90* 9/ 9*
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FB4 17/18 39/54 84/90 6/ 7
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----- ----- ----- -----
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70/72 136/216 264/360 29/34
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Fix sync dection bug when sync out of range (v8.1)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 39/54 55/90 6/ 9
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FB2 18/18* 23/54 36/90 8/ 9
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FB3 17/18 34/54 90/90* 9/ 9*
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FB4 18/18* 41/54 86/90 6/ 7
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----- ----- ----- -----
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71/72 137/216 267/360 29/34
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