vhdl_YUV: Fix sync dection bug when sync out of range (v8.1)

Change-Id: I98fbbb32ced4fdded40c14ef8f741de6f0a415bd
yuv80
David Banks 2020-01-10 13:20:39 +00:00
rodzic 7ab3e15574
commit e95ee77dab
4 zmienionych plików z 16 dodań i 4 usunięć

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@ -49,7 +49,7 @@ architecture Behavorial of RGBtoHDMI is
-- Version number: Design_Major_Minor
-- Design: 0 = Normal CPLD, 1 = Alternative CPLD, 2=Atom CPLD, 3=YUV6847 CPLD
constant VERSION_NUM : std_logic_vector(11 downto 0) := x"380";
constant VERSION_NUM : std_logic_vector(11 downto 0) := x"381";
-- NOTE: the difference between the leading and trailing offsets is
-- 256 clks = 32 pixel clocks.
@ -236,7 +236,7 @@ begin
if HS3 = '0' and HS2 = '1' then
-- Stop sampling on the trailing edge of HSYNC
sampling <= '0';
elsif HS2 = '1' and counter = "1111111" then
elsif counter = "1111111" then
-- Start sampling when the counter expires
sampling <= '1';
end if;
@ -379,8 +379,9 @@ begin
inv_R <= '1';
end if;
-- generate the csync output
csync <= HS2;
-- generate the csync output from the most delayed version of HS
-- (csync adds an extra register, could save this in future)
csync <= HS5;
end if;
end process;

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@ -129,3 +129,14 @@ FB3 17/18 34/54 90/90* 9/ 9*
FB4 17/18 39/54 84/90 6/ 7
----- ----- ----- -----
70/72 136/216 264/360 29/34
Fix sync dection bug when sync out of range (v8.1)
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 39/54 55/90 6/ 9
FB2 18/18* 23/54 36/90 8/ 9
FB3 17/18 34/54 90/90* 9/ 9*
FB4 18/18* 41/54 86/90 6/ 7
----- ----- ----- -----
71/72 137/216 267/360 29/34