Update capture_line_default_8bpp.S

Simplified code slightly

src/capture_line_default_8bpp.S

@@ -39,49 +39,44 @@ capture_line_default_8bpp:
 
         push    {lr}
 
-        mov    r12, r0                   // pointer to the line in the frame buffer
-        mov    r6, r1                    // number of 8-bit characters per line
+        mov     r6, #0
+        ldr     r7, =0x01010101
 loop:
-
         WAIT_FOR_PSYNC_10
 
         CAPTURE_BITS
 
         // Orr in the VSync indicator
-        ldr    r8, =0x01010101
         tst    r3, #BIT_VSYNC_MARKER
-        orrne  r10, r10, r8
+        orrne  r10, r10, r7
 
         // Line double always in Modes 0-6 regardless of interlace
         // On the multi core Pi this introduces stalling artefacts
 #ifndef HAS_MULTICORE
         tst    r3, #BIT_SCANLINES
-        movne  r0, #0
-        moveq  r0, r10
-        str    r0, [r12, r2]
+        streq  r10, [r0, r2]
+        strne  r6, [r0, r2]
 #endif
-        str    r10, [r12], #4
+        str    r10, [r0], #4
 
         WAIT_FOR_PSYNC_01
 
         CAPTURE_BITS
 
         // Orr in the VSync indicator
-        ldr    r8, =0x01010101
         tst    r3, #BIT_VSYNC_MARKER
-        orrne  r10, r10, r8
+        orrne  r10, r10, r7
 
         // Line double always in Modes 0-6 regardless of interlace
         // On the multi core Pi this introduces stalling artefacts
 #ifndef HAS_MULTICORE
         tst    r3, #BIT_SCANLINES
-        movne  r0, #0
-        moveq  r0, r10
-        str    r0, [r12, r2]
+        streq  r10, [r0, r2]
+        strne  r6, [r0, r2]
 #endif
-        str    r10, [r12], #4
+        str    r10, [r0], #4
 
-        subs   r6, r6, #1
+        subs   r1, r1, #1
         bne    loop
 
 exit: