kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
Pi Firmware: refactor so changing PLLA/C/D is easier
Change-Id: I11dcb5d4994ebbb371af3e4fd30ececd6400034epull/105/head
David Banks
rodzic
0e671ea107
commit
cba658095c
18
src/defs.h
18
src/defs.h
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@ -96,11 +96,6 @@
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#define BIT_BOTH_BUFFERS (BIT_DRAW_BUFFER | BIT_DISP_BUFFER)
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// Define the pixel clock for sampling
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#define PLL_PER_DIVIDER 4 // This gives a default PLLA_PER clock of 600MHz
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#define GPCLK_SOURCE 4 // PLLA_PER used as source
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#define DEFAULT_GPCLK_DIVISOR 6 // 600MHz / 6 = 100MHz
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// Pi 2/3 Multicore options
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#if defined(RPI2) || defined(RPI3)
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@ -290,10 +285,21 @@ typedef struct {
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#define PIXELVALVE2_VERTA (volatile uint32_t *)(PERIPHERAL_BASE + 0x807014)
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#define PIXELVALVE2_VERTB (volatile uint32_t *)(PERIPHERAL_BASE + 0x807018)
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#define PM_RSTC (volatile uint32_t *)(PERIPHERAL_BASE + 0x10001c)
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#define PM_WDOG (volatile uint32_t *)(PERIPHERAL_BASE + 0x100024)
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#define PM_PASSWORD 0x5a000000
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#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
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#define CM_PASSWORD 0x5a000000
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#define CM_PLLA_LOADCORE (1 << 4)
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#define CM_PLLA_HOLDCORE (1 << 5)
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#define CM_PLLA_LOADPER (1 << 6)
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#define CM_PLLA_HOLDPER (1 << 7)
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#define A2W_PLL_CHANNEL_DISABLE (1 << 8)
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#define GZ_CLK_BUSY (1 << 7)
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#define GZ_CLK_ENA (1 << 4)
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#define GP_CLK1_CTL (volatile uint32_t *)(PERIPHERAL_BASE + 0x101078)
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#define GP_CLK1_DIV (volatile uint32_t *)(PERIPHERAL_BASE + 0x10107C)
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#define CM_PLLA (volatile uint32_t *)(0x20101104)
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#endif
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@ -28,17 +28,68 @@
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typedef void (*func_ptr)();
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#define CM_PASSWORD 0x5a000000
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#define CM_PLLA_LOADCORE (1 << 4)
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#define CM_PLLA_HOLDCORE (1 << 5)
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#define CM_PLLA_LOADPER (1 << 6)
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#define CM_PLLA_HOLDPER (1 << 7)
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#define A2W_PLL_CHANNEL_DISABLE (1 << 8)
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#define GZ_CLK_BUSY (1 << 7)
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#define GZ_CLK_ENA (1 << 4)
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#define GP_CLK1_CTL (volatile uint32_t *)(PERIPHERAL_BASE + 0x101078)
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#define GP_CLK1_DIV (volatile uint32_t *)(PERIPHERAL_BASE + 0x10107C)
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#define CM_PLLA (volatile uint32_t *)(0x20101104)
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// =============================================================
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// Define the PLL to be used for the sampling clock
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// =============================================================
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//
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// Choose between PLLA, PLLC and PLLD
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//
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// PLLA - not otherwise used
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// PLLC - used for the Core Clock
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// PLLD - possibly used for the SDRAM Clock, so might overclock it by 20%
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//
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// TODO: PLLA doesn't currently start on the Pi2/Pi3
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//
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// Power-on defaults are values for the Pi Zero
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// SYS_CLK_DIVIDER is the ratio between PLLC and the Core Clock
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// This is typically 3 or 4, depending on the Pi Model. We need
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// to know this to correct serial speed when PLLC used.
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#if defined(RPI3)
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#define USE_PLLC
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#define SYS_CLK_DIVIDER 3
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#elif defined(RPI2)
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#define USE_PLLC
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#define SYS_CLK_DIVIDER 4
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#else
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#define USE_PLLA
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#define SYS_CLK_DIVIDER 3
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#endif
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#ifdef USE_PLLA
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#define PLL_NAME "PLLA" // power-on default = off
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#define GPCLK_SOURCE 4 // PLLA_PER used as source
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#define DEFAULT_GPCLK_DIVISOR 6 // 600MHz / 6 = 100MHz
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#define PLL_CTRL PLLA_CTRL
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#define PLL_FRAC PLLA_FRAC
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#define PLL_SCALE 2
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#define MIN_PLL_FREQ 800000000 // PLLA_PER = 400MHz
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#define MAX_PLL_FREQ 1200000000 // PLLA_PER = 600MHz
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#endif
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#ifdef USE_PLLC
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#define PLL_NAME "PLLC" // power-on default = 1200MHz
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#define GPCLK_SOURCE 5 // PLLC_PER used as source
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#define DEFAULT_GPCLK_DIVISOR 12 // 1200MHz / 12 = 100MHz
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#define PLL_CTRL PLLC_CTRL
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#define PLL_FRAC PLLC_FRAC
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#define PLL_SCALE 1
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#define MIN_PLL_FREQ 900000000 // PLLC_PER = 900MHz
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#define MAX_PLL_FREQ 1200000000 // PLLC_PER = 1200MHz
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#endif
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#ifdef USE_PLLD
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#define PLL_NAME "PLLD" // power-on default = 500MHz
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#define GPCLK_SOURCE 6 // PLLD_PER used as source
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#define DEFAULT_GPCLK_DIVISOR 5 // 500MHz / 5 = 100MHz
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#define PLL_CTRL PLLD_CTRL
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#define PLL_FRAC PLLD_FRAC
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#define PLL_SCALE 2
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#define MIN_PLL_FREQ 800000000 // PLLD_PER = 400MHz
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#define MAX_PLL_FREQ 1200000000 // PLLD_PER = 600MHz
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#endif
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// =============================================================
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// Forward declarations
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@ -535,9 +586,9 @@ static int calibrate_sampling_clock() {
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log_info(" Error adjusted clock = %d Hz", adjusted_clock);
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// Pick the best value for pll_freq and gpclk_divisor
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int pll_scale = PLL_PER_DIVIDER / 2; // This comes from the value in PLL_PER (4)
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int min_pll_freq = 800000000; // This gives a GPCLK soource of 400MHz
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int max_pll_freq = 1200000000; // This gives a GPCLK souurce of 600MHz
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int pll_scale = PLL_SCALE; // defined at the top
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int min_pll_freq = MIN_PLL_FREQ; // defined at the top
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int max_pll_freq = MAX_PLL_FREQ; // defined at the top
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int gpclk_divisor = max_pll_freq / pll_scale / new_clock;
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int pll_freq = new_clock * pll_scale * gpclk_divisor ;
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log_info(" GPCLK Divisor = %d", gpclk_divisor);
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@ -555,15 +606,20 @@ static int calibrate_sampling_clock() {
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// If the clock has changed from it's previous value, then actually change it
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if (pll_freq != old_pll_freq) {
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set_pll_frequency(((double) pll_freq) / 1e6, PLLA_CTRL, PLLA_FRAC);
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set_pll_frequency(((double) pll_freq) / 1e6, PLL_CTRL, PLL_FRAC);
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#ifdef USE_PLLC
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// Reinitialize the UART as the Core Clock has changed
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RPI_AuxMiniUartInit_With_Freq(115200, 8, pll_freq / SYS_CLK_DIVIDER);
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#endif
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// And remember for next time
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old_pll_freq = pll_freq;
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}
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// TODO: this should be superfluous (as the GPU is not changing the core clock)
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// However, if we remove it, the next osd_update_palette() call hangs
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int core_clock = get_clock_rate(CORE_CLK_ID);
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log_info(" Core clock freq = %d Hz", core_clock);
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get_clock_rate(CORE_CLK_ID);
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// Finally, set the new divisor
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log_debug("Setting up divisor");
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@ -847,7 +903,6 @@ int recalculate_hdmi_clock_line_locked_update(int force) {
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}
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}
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// Configure PLLA so we can use it as a sampling clock source
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//
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// The logic to configure PLLA conmes from the Linux Kernel clk-bcm2835
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@ -856,7 +911,7 @@ int recalculate_hdmi_clock_line_locked_update(int force) {
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// - bcm2835_pll_divider_set_rate
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// - bcm2835_pll_divider_on
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// https://elixir.bootlin.com/linux/v4.4.70/source/drivers/clk/bcm/clk-bcm2835.c
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#ifdef USE_PLLA
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static void configure_plla(int divider) {
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// Log the before register values
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@ -882,6 +937,7 @@ static void configure_plla(int divider) {
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// Log the before register values
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log_plla();
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}
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#endif
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static void init_hardware() {
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int i;
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@ -922,8 +978,19 @@ static void init_hardware() {
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// Configure the GPCLK pin as a GPCLK
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RPI_SetGpioPinFunction(GPCLK_PIN, FS_ALT5);
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log_info("Using %s as the sampling clock", PLL_NAME);
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// Log all the PLL values
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log_plla();
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log_pllb();
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log_pllc();
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log_plld();
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log_pllh();
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#ifdef USE_PLLA
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// Enable the PLLA_PER divider
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configure_plla(PLL_PER_DIVIDER);
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configure_plla(4);
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#endif
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// The divisor us now the same for both modes
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log_debug("Setting up divisor");
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